JP2549765B2 - Microcomputer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a system configuration of a microcomputer.

[Conventional technology]

Laptop or notebook type microcomputers are becoming widespread due to their portability. By the way, one of the problems common to such microcomputers is power consumption. In other words, these microcomputers use a battery as a portable power supply, but currently only operate for about 2 to 5 hours under normal operation. Therefore, in some cases, when the input is not made within one fixed time, the CPU is automatically stopped and the display is erased to reduce the power consumption.

FIG. 8 shows a block diagram of a display system unit including a conventional CPU. Here, the LCD data 108 is the display controller 10
3 is LCD data to be output according to the contents of the VROM 104.

The LCD sync signal is a sync signal for displaying the LCD data output by the display controller 103 on the LCD 107.

In the above example, the power consumption of the CPU 102, the display controller 103, and the VRAM 104 can be reduced by stopping the CPU 102 and the display controller 103 in the figure. However, when stopped, the LCD data 108 and the LCD sync signal 109 are not output.

[Problems to be Solved by the Invention]

A conventional microcomputer has a short battery drive time and is inconvenient. Especially regarding the display, there is a problem that the battery is consumed while the user is thinking while displaying.

It is an object of the present invention to solve this problem and provide a portable microcomputer that allows a user to use the microcomputer while thinking slowly and that prevents battery consumption.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a central processing unit (CP
U), a first image display storage circuit, a display image generation circuit, and a display element, and a microcomputer having a normal power consumption display mode and a constant power consumption display mode is characterized by taking the following means.

(1) A display control circuit and a second image display storage circuit are provided, and the display control circuit is connected to the display image generation circuit, the display element and the second image display storage circuit by a signal line, and in the normal power consumption display mode. Image data based on the data stored in the first image display storage circuit output from the display image generation circuit is displayed on the display element according to a synchronization signal output from the display image generation circuit, The image display memory circuit stores the image data as fixed image data constantly or at a predetermined timing.

(2) In the low power consumption display mode, the fixed image data stored in the second image display storage circuit is continuously displayed on the display element in accordance with a newly generated synchronizing signal, and the display image generation circuit Stop the operation of.

(3) In the low power consumption display mode, the fixed image data stored in the second image display storage circuit is continuously displayed on the display element according to a synchronization signal output from the display image generation circuit, and is displayed. Stop the operation of the image generation circuit.

(4) At the time of switching from the low power consumption display mode to the normal power consumption display mode, the fixed image data stored in the second image display storage circuit is the newly generated synchronization signal or the display image generation circuit. Image data based on the data stored in the first image display storage circuit, which is continuously displayed on the display element according to the synchronization signal output from the display image generation circuit, and which is based on the data stored in the first image display storage circuit. Output from.

(5) When switching from the normal power consumption display mode to the low power consumption display mode, the image data based on the data stored in the first image display storage circuit output from the display image generation circuit is used as the display image. The fixed image data displayed on the display element according to the synchronization signal output from the generation circuit and the fixed image data stored in the second image display storage circuit is output from the newly generated synchronization signal or the display control circuit. Output according to the sync signal.

(6) A detection unit for detecting access to the first image display storage circuit or the display image generation circuit by the central processing unit (CPU) is provided, and the normal power consumption display mode and the normal power consumption display mode are set according to the detection frequency of the detection unit. Switches the low power consumption display mode.

(7) A detection unit that detects an interrupt signal to the central processing unit (CPU) is provided, and the normal power consumption display mode and the low power consumption display mode are switched according to the detection frequency of the detection unit.

(8) A detection unit for detecting an access to the first image display storage circuit or the display image generation circuit by the central processing unit (CPU) is provided, and the detection unit detects the access frequency according to the detection frequency of the detection unit together with the low power consumption display mode. Stop and drive the CPU,
Alternatively, the drive frequency is switched.

(9) A detection means for detecting an interrupt signal to the central processing unit (CPU) is provided, and together with the low power consumption display mode,
The CPU is stopped and driven, or the drive frequency is switched according to the detection frequency of the detection means.

[Action]

The current of the entire personal computer is divided into three, that is, the system current A, the display current B, and the holding current C. Considering the relationship with time t, a schematic diagram of FIG. 7a is obtained. If nothing is saved, the current of A + B + C is always flowing. Here, the system unit (about 4 times as large as the display unit), which occupies the largest percentage, can save power by finely stopping according to the software and the needs of the user. In fact, there are some products that use OS detection and bus detection.
An ideal case where the system unit is stopped finely according to the needs of the software and the user to save power is shown in the schematic diagram of FIG. 7b. Here, if the power saving of the display unit is considered and another power saving is considered, the power saving of the display unit has a great influence on the entire system. In other words, the power consumption of the system unit alone limits the operation time of the entire system to several times, but if the power consumption of the display unit is added to this, it is doubled.

In consideration of the above effect, the present system provides a method of reducing the current display on the display unit without deleting it. In this system, in the normal mode, the display controller 103 in FIG.
The holding memory circuit 106 is used to display the LCD data 108 output from the LCD data 108 according to the LCD sync signal 109.
In the power saving mode, the display controller 103, which requires a large amount of power to perform calculation based on the data in the VRAM 104 as shown in FIG. 2, is stopped, and only a small amount of power is required instead. Holding memory circuit 106
The LCD holding data 202 therein is reassembled and displayed. By switching between these two modes, for example, when the VRAM is rewritten, the normal mode is set, and the other modes are set to the power saving mode. In the case of word processing software, there is almost no time to access the VRAM 104, so most of the time is saved. It becomes effective mode and becomes effective.

[Embodiment 1] FIG. 1 is a block diagram showing an embodiment in a normal mode according to the present invention. Here, the CPU 102 is an Intel 80
It corresponds to the central processing unit such as C88. As is well known, the VRAM 104 is a video memory using a dynamic RAM used in a microcomputer, and corresponds to the first image display storage circuit. The holding memory circuit 106 is a circuit including a storage circuit element using a dynamic RAM or the like capable of storing the LCD data 108, and corresponds to a second image display storage circuit for fixed image display. The display controller 103 is a circuit for a microcomputer called an ordinary VGA controller or the like and corresponds to a display image generating circuit. The image circuit 105 performs central control of this system and corresponds to a display control circuit.
The LCD circuit 107 is a display circuit including a liquid crystal display and corresponds to a display element. The operation of the system according to this embodiment will be described below. The CPU 102, display controller 103, and VRAM 104 are connected by an address bus 101.

The display controller 103 scans the contents of the VRAM 104, performs a predetermined calculation, and displays the resulting image data on the LCD.
And outputs the LCD data 108 and the LCD sync signal 109 for driving the LCD. The image circuit 105 is an LCD
Transfers the data 108 and the LCD sync signal 109 to the LCD circuit 107, and holds the LCD data 108 and the LCD sync signal 109 in the meantime.
Transfer to 106. The holding memory circuit 106 stores the LCD data 108 from the image circuit 105 in the memory in response to the LCD synchronizing signal 109. The LCD circuit 107 outputs the LCD data 108 from the image circuit 105 as L
It is displayed on the LCD according to the CD sync signal 109. The image circuit
The LCD data 108 and the LCD synchronization signal 109 may be transferred from 105 to the holding memory circuit 106 at all times, or the contents immediately before entering the power saving mode.

[Embodiment 2] FIG. 2 shows a block diagram of an embodiment in the power saving mode according to the present invention. The display controller 103 is stopped. At this time, the contents of the control register in the display controller 103 and the VRAM 104 are held. Image circuit 1
05 generates the pseudo sync signal 201 and transfers it to the LCD circuit 107, and at the same time, the holding memory circuit 1 is synchronized with the pseudo sync signal 201.
The LCD holding data 202 stored in 06 is repeatedly transferred to the LCD circuit 107. The LCD circuit 107 displays the LCD hold data 202 from the image circuit 105 on the LCD according to the pseudo LCD sync signal 201.

[Embodiment 3] FIG. 3 shows a block diagram of another embodiment in the power saving mode according to the present invention. Display controller 103 is an LCD sync signal
While outputting 109, other functions are stopped. At this time, the contents in the display controller 103 are retained. The image circuit 105 transfers the LCD synchronizing circuit 109 to the LCD circuit 107, and at the same time, repeatedly transfers the LCD holding data 202 stored in the holding memory circuit 106 to the LCD circuit 107 in synchronization with the LCD synchronizing signal 109. The LCD circuit 107 is the LCD from the image circuit 105.
The held data 202 is displayed on the LCD according to the LCD sync signal 109. Here, the VRAM 104 holds the data as it is when the display controller is stopped.

[Embodiment 4] FIG. 4 (a) shows a block diagram of an embodiment when switching from the power saving mode according to Embodiment 2 to the normal mode according to Embodiment 1 according to the present invention. The display controller 103 is driven to scan the contents of the VRAM 104 to perform a predetermined calculation, and the resulting image data is converted to an LCD for conversion to the LCD.
At the same time as outputting the data 108, the LCD synchronizing signal 109 for driving the LCD is output. The image circuit 105 generates the pseudo sync signal 201 and transfers it to the LCD circuit 107, and at the same time, the pseudo sync signal 201.
The LCD holding data 202 stored in the holding memory circuit 106 is repeatedly transferred to the LCD circuit 107 in synchronization with 201. LCD circuit
107 displays the LCD holding data 202 from the image circuit 105 on the LCD according to the pseudo LCD synchronizing signal 201. This is because a period for displaying in the power saving mode must be provided while driving the display controller 103 from the time when the display controller 103 is driven until the normal operation is performed.

As a reverse case, FIG. 4 (b) shows a block diagram of an embodiment when switching from the normal mode according to the first embodiment of the present invention to the power saving mode according to the second embodiment. The display controller 103 is driven to scan the contents of the VRAM 104 to perform a predetermined calculation, and the resulting image data is displayed on the LCD.
And outputs the LCD data 108 and the LCD sync signal 109 for driving the LCD. The image circuit 105 generates a pseudo sync signal 201 and transfers it to the holding memory circuit 106.

The LCD circuit 107 displays the LCD data 108 from the image circuit 105 on the LCD according to the LCD synchronization signal 109.

[Embodiment 5] FIG. 5 shows a block diagram of an embodiment for judging switching between the power saving mode and the normal mode based on the present invention. Judgment circuit 501 uses interrupt signal INTR503 to address bus and CPU
If it is determined that there is no change in the display by monitoring the, the signal for setting the display to the power saving mode is output as the determination signal A502, and if it is determined that there is a change in the display, the signal for setting the display in the normal mode is determined. Output as A502. The criteria here is
VRAM access frequency, INTR frequency, etc. In the figure, the hardware is switched according to the determination signal A502,
Of course, it is also possible to provide a register inside the determination circuit, periodically detect and then switch by software.

[Sixth Embodiment] FIG. 6 shows a block diagram of another embodiment for judging whether to switch between the power saving mode and the normal mode according to the present invention. The monitoring circuit 602 is an interrupt signal to the address bus and CPU
If the INTR503 is monitored and it is determined that there is no change in the display, a signal for setting the display to the power saving mode is output as the determination signal A502, and if it is determined that there is a change in the display, the signal for setting the display in the normal mode is determined. Output as signal A502. further,
The monitoring circuit 602 is an interrupt signal INTR to the address bus and CPU
If it is determined that there is no change in the input by monitoring, the signal for setting the CPU to the power saving mode is output as the determination signal B601. Here, the criterion is the frequency of access to the input / output function in the OS in addition to that described in the fifth embodiment. In this way, by saving power to the CPU as well, the power saving of the entire system described in the operation is dramatically improved.

〔The invention's effect〕

With the microcomputer according to the present invention, there is no problem of turning off the display on the display unit even in the low power-off mode, the user can operate without interrupting his thoughts, and the power consumption can be greatly saved.

[Brief description of drawings]

FIG. 1 shows a block diagram of a first embodiment according to the present invention. FIG. 2 shows a block diagram of a second embodiment according to the present invention. FIG. 3 shows a block diagram of Embodiment 3 according to the present invention. 4 (a) and 4 (b) show block diagrams of Embodiment 4 according to the present invention. FIG. 5 shows a block diagram of Embodiment 5 according to the present invention. FIG. 6 shows a block diagram of Embodiment 6 according to the present invention. FIG. 7 shows a schematic diagram of the effect of the present invention. FIG. 8 shows a block diagram of a conventional microcomputer display unit. 102 ... CPU, 103 ... Display controller, 104 ... VRAM, 105 ... Image circuit, 106 ... Holding memory circuit, 107 ... LCD circuit.

Claims (8)

(57) [Claims] 1. A central processing unit, a first image display storage circuit,
In a microcomputer having a display image generation circuit and a display element and having a normal power consumption display mode and a low power consumption display mode, a display control circuit and a second image display storage circuit are provided, and the display control circuit is a display image generation circuit, Connected to the display element and the second image display storage circuit by a signal line,
In the normal power consumption display mode, the image data based on the data stored in the first image display storage circuit output from the display image generation circuit is output according to the synchronization signal output from the display image generation circuit. While displaying on the display element via the display control circuit, the second image display storage circuit is caused to store the image data as fixed image data constantly or at a predetermined timing, and in the low power consumption display mode, The fixed image data stored in the second image display storage circuit is continuously displayed on the display element via the display control circuit according to a synchronization signal newly generated from the display control circuit, and a display image is generated. A microcomputer characterized by stopping the operation of a circuit. 2. The microcomputer according to claim 1, wherein in the low power consumption display mode, the fixed image data stored in the second image display storage circuit is used as a synchronization signal output from the display control circuit. Therefore, the microcomputer is characterized by continuously displaying on the display element and stopping the operation of the display image generating circuit. 3. The microcomputer according to claim 1, wherein when the low power consumption display mode is switched to the normal power consumption display mode, the fixed image data stored in the second image display storage circuit is newly generated. Data stored in the first image display storage circuit which is continuously displayed on the display element in accordance with the generated synchronizing signal or the synchronizing signal output from the display image generating circuit, and which is output from the display image generating circuit. And a period for outputting the image data based on the above from the display image generating circuit. 4. The microcomputer according to claim 1, wherein when the normal power consumption display mode is switched to the low power consumption display mode, the first image display storage circuit output from the display image generation circuit stores the information. Image data based on the generated data is displayed on the display element according to a synchronization signal output from the display image generation circuit, and the fixed image data stored in the second image display storage circuit is newly generated. A microcomputer which outputs according to a synchronizing signal or a synchronizing signal outputted from the display image generating circuit. 5. The microcomputer according to claim 1, further comprising detection means for detecting an access of said first image display storage circuit or display image generation circuit by a central processing unit, and depending on a detection frequency by said detection means. A microcomputer that switches between the normal power consumption display mode and the low power consumption display mode. 6. The microcomputer according to claim 1, further comprising detection means for detecting an interrupt signal to the central processing unit, wherein the normal power consumption display mode and the low power consumption display are provided according to the detection frequency of the detection means. A microcomputer characterized by switching modes. 7. The microcomputer according to claim 1, further comprising detection means for detecting access to said first image display storage circuit or display image generation circuit by a central processing unit, together with a low power consumption display mode. A microcomputer characterized in that the CPU is stopped and driven, or the drive frequency is switched according to the detection frequency of the detection means. 8. The microcomputer according to claim 1, further comprising detection means for detecting an interrupt signal to the central processing unit, and in addition to the low power consumption display mode, stop the CPU according to the detection frequency by the detection means. And a drive frequency, or a drive frequency is switched.