JP4491408B2 - Portable information terminal - Google Patents

Description

  The present invention relates to a portable information terminal such as a cellular phone, and more particularly to an improvement of a portable information terminal in which a display controller is interposed between a display device that displays an image and a host controller that generates image data.

  Generally, a liquid crystal display (LCD) is adopted as a display device of a portable information terminal such as a mobile phone. This type of liquid crystal display is provided as a pre-moduleized LCD display device including a liquid crystal display panel and a driver circuit, and is used with an LCD controller (display controller) interposed between it and a host controller that generates image data. Is done. The LCD controller has a built-in video RAM for storing the image data generated by the host controller, reads the image data in the video RAM at a predetermined timing, and outputs it to the LCD display device 3.

  Further, in recent mobile phones, a display processor is introduced in addition to the host processor in the host controller in order to cope with an increase in size and definition of the liquid crystal display and an increase in the drawing update speed. The display processor is a circuit dedicated to display processing that executes image data generation and transfer at a high speed, which was conventionally performed by the host processor, and reduces the processing load on the display system by the host processor. Has improved.

  FIG. 9 is a block diagram showing an example of the configuration of the main part of a conventional portable information terminal. The host controller 1, LCD controller 2, LCD display device 3, I / O (Input / Output) controller 4 and data storage are shown in FIG. Parts 12 and 13 are shown. The parallel communication line 51 is the only data communication line connecting the host controller 1 and the LCD controller 2, and all data communication between these controllers is performed via the parallel communication line 51. .

  The host controller 1 includes a host processor 10 and a display processor 11. The display processor 11 generates image data to be displayed on the liquid crystal display panel 33 based on an instruction from the host processor 10 and transfers the image data to the LCD controller 2 through the parallel communication line 51 at a high speed. Also, the control data of the LCD controller 2 and the LCD display device 3 generated by the host processor 10 is once transmitted from the host processor 10 to the display processor 11 and then output to the LCD controller 2 via the parallel communication line 51. Is done.

  The LCD controller 2 includes a video RAM (VRAM) 24 that stores image data and a register group 27 that stores control data. Image data transferred from the display processor 11 is received by the communication unit 20 and written to the video RAM 24 by the VRAM access unit 23. Further, the image data held in the video RAM 24 is read out by the image data output unit 25 at a predetermined timing and output to the LCD display device 3. On the other hand, control data output from the display processor 11 is received by the communication unit 20 and written to the register group 27 by the register access unit 26. In the register group 27, write control data, output control data, and LCD control data are held as control data.

  The write control data is control data that defines the operation of the VRAM access unit 23 and includes, for example, information such as a pixel position at which writing is started, a writing range, and a writing direction. The VRAM access unit 23 automatically generates an address of the video RAM 24 based on the write control data, and writes the image data continuously input from the display processor 11 to the video RAM 24. Therefore, the write control data is generated by the display processor 11 and output to the LCD controller 2 prior to the transfer of a series of image data.

  The output control data is control data that defines the operation of the image data output unit 25. The image data output unit 25 adjusts the timing for outputting the image data in the video RAM 24 to the LCD display device 3 based on the output control data.

  The LCD control data is control data that defines the operation of the communication unit 31 and the driver circuit 32 in the LCD display device 3, and is transmitted to the LCD display device 3 by the control data output unit 28. The output control data and the LCD control data are generated by the host processor 10 and input to the LCD controller 2 via the display processor 11.

  The I / O controller 4 is connected to the host processor 10 via the serial communication line 50, and performs signal input / output and control for peripheral devices (not shown) based on peripheral device control data output from the host processor 10. Yes. The peripheral device includes not only an external device that is detachably attached to the mobile phone, such as a USB device or an SD card, but also an internal device that is built in the mobile phone in advance.

  As described above, recent mobile phones have introduced the display processor 11 in the host controller 1 to cope with the increase in size and definition of the liquid crystal display. The amount of power consumed by the battery is also increasing.

  In general, a portable information terminal using a battery power source has an operation mode, a so-called power saving mode, in which power consumption is reduced by temporarily reducing the operating frequency of the host controller 1 to reduce performance or limiting functions. In many cases. In particular, since the power consumption for image display greatly affects the total power consumption, the backlight of the LCD display device 3 is turned off and the image data is updated by suppressing the image quality in the power saving mode. The processing load is also reduced.

  For this reason, it is not always necessary to generate image data using the display processor 11 in the power saving mode, and it is desirable to reduce power consumption by the display processor 11. That is, in the power saving mode, the load of the image data generation process is reduced and the load of the host processor 10 itself is also reduced. For this reason, if the host processor 10 can perform image data generation processing in the power saving mode, the power supply or clock supply to the display processor 11 is cut off to further reduce the power consumption of the portable information terminal as a whole. It is considered possible.

  However, in the conventional mobile phone, the parallel communication line 51 is the only data communication line connecting the host controller 1 and the LCD controller 2, and the host controller can be provided by cutting off the power supply or clock supply to the display processor 11. There is a problem that data communication cannot be performed between 1 and the LCD controller 2 and the image data in the video RAM 24 cannot be updated.

  The present invention has been made in view of the above circumstances. In the normal power mode, the display processor is used to generate high-definition image data at high speed and transfer it to the LCD controller at high speed, while in the power saving mode. An object is to cut power supply or clock supply to the display processor to reduce power consumption. In particular, it is an object to reduce power consumption by cutting off the power supply or clock supply to the display processor in the power saving mode without increasing the number of data communication lines or complicating the circuit configuration. Another object of the present invention is to provide such a portable information terminal.

  A portable information terminal according to the present invention includes a display device that displays an image, a host controller that generates image data, a display controller that is interposed between the display device and the host controller, and the host controller and the display. The controller is connected by the first data communication line and the second data communication line, and switches between the normal power mode and the power saving mode in which the amount of image data displayed on the display device is updated per unit time. It is possible and has the following features.

  In the portable information terminal according to the first aspect of the present invention, the host controller generates image data in the normal power mode, and a display processor in which power supply is cut off in the power saving mode, and image data in the power saving mode. And a host processor for generation. A video RAM in which the display controller holds image data input from the display processor via the first data communication line and image data input from the host processor via the second data communication line; A register group for holding peripheral device control data input from the host processor via the second data communication line; and a peripheral device detachably connected to the portable information terminal based on the peripheral device control data And a peripheral device control unit that inputs and outputs signals to and from the device.

  When the display controller and the host controller are connected by two data communication lines and in the normal power mode, the image data generated by the display processor in the host controller is transferred to the display controller via the first data communication line. On the other hand, in the power saving mode in which the amount of updated image data is reduced, the image data generated by the host processor in the host controller is transferred to the display controller via the second data communication line. For this reason, in the power saving mode, the power supply to the display processor can be cut off while the image display is continued. Moreover, since the image data in the power saving mode is transferred using the second data communication line for transferring the peripheral device control data to the display controller, the number of signal lines is remarkably increased, or the circuit This can be realized without significantly increasing the scale.

  Note that the LCD display device 3 to be described later is an example of the display device, and the LCD controller 2N is an example of the display controller. The present invention is not limited to a mobile phone having an LCD display device.

  In the portable information terminal according to the second aspect of the present invention, the host controller generates image data in the normal power mode and the display processor in which power supply is cut off in the power saving mode, and the image data in the power saving mode. And a host processor for generation. A video RAM in which the display controller holds image data input from the display processor via the first data communication line and image data input from the host processor via the second data communication line; A register group for holding peripheral device control data input from the host processor via the second data communication line; and a peripheral device detachably connected to the portable information terminal based on the peripheral device control data And a peripheral device control unit that inputs and outputs signals to and from the device.

  When the display controller and the host controller are connected by two data communication lines and in the normal power mode, the image data generated by the display processor in the host controller is transferred to the display controller via the first data communication line. On the other hand, in the power saving mode in which the amount of updated image data is reduced, the image data generated by the host processor in the host controller is transferred to the display controller via the second data communication line. For this reason, in the power saving mode, the clock supply to the display processor can be cut off while the image display is continued. Moreover, since the image data in the power saving mode is transferred using the second data communication line for transferring the peripheral device control data to the display controller, the number of signal lines is remarkably increased, or the circuit This can be realized without significantly increasing the scale.

  In addition to the above-described configuration, the portable information terminal according to the third aspect of the present invention provides a VRAM access that generates an address of the video RAM serving as a write destination based on write control data when writing image data in the normal power mode. And the register group is configured to hold the write control data input from the host controller. With such a configuration, transfer of image data in the normal power mode can be speeded up.

  In the portable information terminal according to the fourth aspect of the present invention, in addition to the above configuration, in the normal power mode, the storage area in the video RAM corresponding to the entire display screen of the display device is updated. Only a storage area in the video RAM corresponding to a part of the display screen is updated.

  In addition to the above configuration, the portable information terminal according to the fifth aspect of the present invention has a smaller amount of information per pixel constituting the image data stored in the video RAM in the power saving mode than in the normal power mode. It is comprised so that it may become.

  In addition to the above configuration, the portable information terminal according to the sixth aspect of the present invention is configured such that, in the power saving mode, the update cycle of the image data stored in the video RAM is longer than that in the normal power mode.

  With such a configuration, the amount of image data generated by the host controller and transferred to the display controller can be made different depending on the power saving mode and the normal power mode. Accordingly, the power supply or clock supply to the display processor is interrupted in the power saving mode, and image data can be generated and transferred by the host processor.

  According to the present invention, in the normal power mode, high-definition image data is generated at high speed using the display processor and transferred to the display controller at a high speed. On the other hand, in the power saving mode, power or clock is supplied to the display processor. It can be cut off and power consumption can be effectively reduced. In particular, the power supply or clock supply to the display processor can be shut off in the power saving mode without increasing the number of data communication lines or complicating the circuit configuration. Another object of the present invention is to provide such a portable information terminal.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a schematic configuration example of a portable information terminal according to Embodiment 1 of the present invention. Here, a cellular phone is shown as an example of the portable information terminal. The host controller 1 operates based on a program held in the program storage unit 13 and controls each block constituting the mobile phone. The wireless communication unit 14 performs wireless communication with a base station (not shown), and the user can talk using the handset 17. Such call processing and outgoing / incoming processing are controlled by the host controller 1. When the user performs a key operation, the host controller 1 executes a predetermined process based on an operation signal from the key operation unit 16. The image data captured by the camera unit 15 is temporarily stored in the image data storage unit 12 by the host controller 1 and compressed according to an existing image compression method such as the JPEG format, and then stored in a nonvolatile memory such as a flash memory or an SD card. Stored in sex memory.

  Further, image data displayed on the screen of the LCD display device 3 is also generated by the host controller 1. For example, the host controller 1 reads out image data held in an SDRAM, flash memory, SD card, or the like, and processes the image data to generate image data to be displayed on the screen. Stored. The image data generated in this way is temporarily stored in the LCD controller 2N and output to the LCD display device 3 at a predetermined timing. The LCD controller 2N also performs signal input / output and control for peripheral devices based on instructions from the host controller 1.

  Further, this mobile phone has a normal power mode and a power saving mode as operation modes with different power consumption. Switching of these operation modes is performed by the host controller 1 based on an operation signal from the key operation unit 16 or an incoming signal from the wireless communication unit 14. For example, when the user does not perform a key operation for a certain period, the mode shifts to the power saving mode, and when the key operation is performed or an incoming call is received after that, the normal power mode is restored.

  The power saving mode is an operation mode that consumes less power than the normal power mode. The backlight of the LCD display device 3 is turned off, and the amount of data updated per unit time of image data displayed by the LCD display device 3 Have reduced. This reduction in the amount of update data can be achieved, for example, by limiting the area where image data is updated to a part of the display screen (partial display), delaying the screen data update cycle, or selecting colors This is done by reducing the number (color type) or the like to reduce the amount of information for each pixel. In particular, when the LCD display device 3 realizes the number of colors of 256 or more by combining gradation representations of three primary colors (for example, RGB: Red / Green / Blue), the combination of these three primary colors 8 By limiting the number of colors to colors, not only the amount of image data can be reduced, but also the current consumption in a D / A converter (not shown) in the driver circuit 32 used for gradation expression is simultaneously reduced. Can do.

  FIG. 2 is a block diagram showing in more detail the main part of the mobile phone shown in FIG. 1, and shows each block related to screen display, that is, host controller 1, LCD controller 2N, LCD display device 3, and image data storage unit. 12 and a program storage unit 13 are shown. That is, it is a block diagram showing an example of the configuration of the display system built in the mobile phone of FIG.

  The LCD controller 2N in the figure is a semiconductor device in which the functions of the conventional LCD controller 2 and the I / O controller 4 are integrated. The LCD controller 2N is provided as a semiconductor device different from the host controller 1, and is disposed so as to be interposed between the host controller 1 and the LCD display device 3 and also between the host controller 1 and peripheral devices (not shown). Has been. The host controller 1 and the LCD controller 2N are connected by two data communication lines, that is, a serial communication line 50 and a parallel communication line 51. Note that the semiconductor device in this specification means circuit elements that are formed on a single semiconductor substrate and are independent from each other until they are fixed onto a printed circuit board.

  The serial communication line 50 is a data communication line for performing serial communication between the host processor 10 and the LCD controller 2N. Here, it is composed of a clock signal line SCL (Serial Clock Line) for transmitting a clock signal from the host processor 10 and a data signal line SDA (Serial Data line) for transmitting and receiving a data signal. It is assumed that I2C (registered trademark) is adopted.

  The parallel communication line 51 is a data communication line for performing parallel communication between the display processor 11 and the LCD controller 2N, and has a higher bit rate than the serial communication line 50 and is suitable for transferring image data having a large amount of data. . Here, it is composed of a chip select signal line CS indicating access to the LCD controller 2N, a write signal line WRB indicating data fetch timing, and a plurality of data signal lines D0 to D7. Can be sent at the same time. Further, the parallel communication line 51 only transmits data from the display processor 11 to the LCD controller 2N, and can transfer image data at a higher speed than image data transfer from the serial communication line 50.

  The image data storage unit 12 is a storage device that holds image data. For example, an SDRAM (Synchronous Dynamic RAM) that operates in synchronization with a clock signal of the host controller 1 is used. The image data is read by the host processor 10 or the display processor 11 and subjected to desired image processing, whereby image data to be displayed on the liquid crystal display panel 33 is generated. Note that the image data is pixel data or vector data defining a still image or an operation image, or a collection of these.

  The program storage unit 13 is a storage device that holds programs and data. For example, a flash memory that is an electrically rewritable nonvolatile semiconductor memory is used. The host processor 10 sequentially executes the program read from the program storage unit 13. Further, after initializing the display processor 11, the host processor 10 reads a program or microcode for the display processor 11 from the program storage unit 13 and writes it in the memory in the display processor 11.

  The host controller 1 includes a host processor 10, a display processor 11, and a timing control unit 18. The host processor 10, the display processor 11, and the timing control unit 18 can be configured as different semiconductor devices, but can also be configured as one semiconductor device.

  When the operation mode is the normal power mode, the display processor 11 generates image data to be displayed on the LCD display device 3 based on the image data read from the image data storage unit 12. For example, MPEG4, H.264. Decoding processing that expands moving image data encoded in a format such as H.263 into image data for each frame, enlargement processing, reduction processing, rotation processing, inversion processing, format conversion processing, color space correction processing, superposition of image data Processing is performed. The image data generated in this way is transferred to the LCD controller 2N at high speed via the parallel communication line 51. At this time, prior to the transfer of a series of image data by the display processor 11, write control data defining the operation of the VRAM access unit 23 is output from the host processor 10 to the LCD controller 2N.

  The host processor 10 outputs control data to the LCD controller 2N via the serial communication line 50, and performs various controls on the LCD controller 2N and the LCD display device 3 except for the processing performed by the display processor 11. Here, for the LCD controller 2N, write control data defining the operation of the VRAM access unit 23, output control data defining the operation of the image data output unit 25, LCD control data defining the operation of the LCD display device 3, Peripheral device control data defining the operation of the peripheral device control unit 29 is output.

  In addition, the host processor 10 performs operation mode switching control. That is, the operation signal from the key operation unit 16 and the incoming signal from the wireless communication unit 14 are monitored to switch between the normal power mode and the power saving mode. When the operation mode is shifted to the power saving mode, the host processor 10 cuts off the power supply or clock supply to the display processor 11 and reduces the load of the image data generation processing by partial display or the reduction of the number of colors. During the power saving mode, the host processor 10 generates image data and transfers it to the LCD controller 2N via the serial communication line 50 instead of the stopped display processor 11.

  The timing control unit 18 controls the access timing to the LCD controller 2N by the host processor 10 and the display processor 11 in the normal power mode. Here, the operation timing of both is adjusted so that the image data is transferred by the display processor 11 after the transfer of the write control data by the host processor 10 is completed.

  The LCD controller 2N includes a display communication unit 21, a control communication unit 22, a VRAM access unit 23, a video RAM 24, an image data output unit 25, a register access unit 26, a register group 27, a control data output unit 28, and a peripheral device control unit. 29.

  The display communication unit 21 is connected to the parallel communication line 51 and performs a process of receiving image data sent from the display processor 11. The image data received by the display communication unit 21 is output to the VRAM access unit 23 and written in the video RAM 24.

  The control communication unit 22 is connected to the serial communication line 50 and performs transmission / reception processing of control data and image data with the host processor 10. That is, when write control data, output control data, LCD control data, and peripheral device control data are received from the host processor 10, they are output to the register access unit 26. When control data in the register group 27 is input from the register access unit 26 or image data in the video RAM 24 is input from the VRAM access unit 23, these data are transmitted to the host processor 10. Further, in the power saving mode, the image data generated by the host processor 10 is received and output to the VRAM access unit 23. Furthermore, when the two-wire communication standard I2C (registered trademark) is adopted for the serial communication line 50, the control communication unit 22 has a slave address for accessing the register group 27 and a slave address for accessing the VRAM 24. Whether the access to the register group 27 or the access to the VRAM 24 is made based on the slave address prepared and received from the host processor 10.

  The VRAM access unit 23 writes the image data received by the display communication unit 21 or the control communication unit 22 to the video RAM 24, and outputs the image data read from the video RAM 24 to the control communication unit 22. The image data is written by sequentially writing a series of image data into the video RAM 24 based on the write control data in the register group 27. Since the series of image data transferred from the display processor 11 and the host processor 10 has a continuous pixel position, the VRAM access unit 23 writes each image data based on the write control data. The addresses on the video RAM 24 are generated in order, and the image data is written at high speed. The write control data includes, for example, information such as the format of the image data, the pixel position where writing to the video RAM 24 is started, the writing direction, the writing range, and writing prohibition permission.

  The video RAM 24 is a semiconductor storage device that stores image data in a rewritable manner, and stores the image data received by the display communication unit 21 in association with the pixel position designated by the VRAM access unit 23. The image data stored in the video RAM 24 is read by the image data output unit 25 and output to the LCD display device 3. The video RAM 24 is provided with an input buffer for reducing overhead during writing, and the average writing speed is faster than that of the register group 27.

  The image data output unit 25 is connected to the LCD display device 3 through the data communication line 53, processes the image data read from the video RAM 24 based on the output control data in the register group 27, and registers The processed image data is output to the data communication line 53 at a timing based on the output control data in the group 27. This output control data includes, for example, information such as the color palette of image data, transfer speed, format, horizontal / vertical signal output timing, and pixel data output timing. Further, the transmission of image data through the data communication line 53 employs RGB666 parallel communication or LVDS (Low Voltage Differential Signaling) system, for example, image data is transmitted at a frame rate of 60 frames per second. Transferred.

  The register group 27 is a rewritable semiconductor memory device including a plurality of registers that hold control data. The register access unit 26 writes the control data input from the host controller 1 to the register group 27. The control data read from the register group 27 is output to the control communication unit 22. That is, write control data, output control data, LCD control data, and peripheral device control data input from the host processor 10 via the serial communication line 50 are sent to any register in the register group 27 by the register access unit 26. Is written to.

  The control data output unit 28 is connected to the LCD display device 3 via the data communication line 52 and outputs the LCD control data in the register group 27 to the LCD display device 3. The LCD control data includes various control information except image data input to the LCD display device 3 via the data communication line 53. For example, it includes information such as image data transfer speed and format information, horizontal and vertical signal output timing, pixel data output timing, voltage control of the driver circuit 32 in the LCD display device 3, and gamma correction. These pieces of information are output to the LCD display device 3.

  The peripheral device control unit 29 performs signal input / output and control for peripheral devices (not shown) based on the peripheral device control data in the register group 27. For example, the peripheral device control unit 29 functions as a USB transceiver and a level shifter for converting signal levels. Have. That is, it corresponds to the I / O controller 4 in the conventional mobile phone shown in FIG. The peripheral devices targeted by the peripheral device control unit 29 include not only external devices that are detachably attached, such as USB devices and SD cards, but also internal devices that are built in the mobile phone in advance. .

  The LCD display device 3 is a display device that displays the image data transferred from the video RAM 24 of the LCD controller 2N on the screen. The LCD display device 3 includes a communication unit 31 that receives image data via a data communication line 53, a driver circuit 32 that drives a liquid crystal display panel 33 based on the received image data, and a liquid crystal display panel having a display screen. 33. The communication unit 31 and the driver circuit 32 can be configured as different semiconductor devices, but can also be configured as a single semiconductor device.

  The communication unit 31 and the driver circuit 32 operate based on LCD control data input via the data communication line 52. If the image data cannot be correctly received from the LCD controller 2N, the communication unit 31 generates an interrupt signal (interrupt signal) as a control signal for notifying a reception error, and outputs the interrupt signal to the LCD controller 2N or the host controller 1. .

  FIG. 3 is a block diagram showing a more detailed configuration example of the register access unit 26 and the register group 27 of FIG.

  The register group 27 includes two or more registers 71 and an RA (Read Address) register 72, both of which are accessed from the host processor 10 via the serial communication line 50. The register 71 stores write control data, output control data, LCD control data, and peripheral device control data. On the other hand, the RA register 72 is a register in which an address (read address) of a register to be read is written in advance when the control data held in the register 71 is read.

  The register access unit 26 includes an input buffer 61, an address decoder 64, and a selector 65. The input buffer 61 temporarily stores a data write request from the control communication unit 22. The input buffer 61 includes an address storage unit 62 and a data storage unit 63, a register address as a write destination is stored in the address storage unit 62, and data to be written is stored in the data storage unit 63.

  The address decoder 64 decodes a register address that specifies a register in the register group 27. At the time of writing, the register address in the address storage unit 62 is decoded. The selector 65 selects one of the registers constituting the register group 27 based on the decoding result. Data in the data storage unit 63 is written to the register thus selected.

  Steps S101 to S104 in FIG. 4 are flowcharts illustrating an example of the operation in the register access unit 26 in FIG. 3, and a processing procedure at the time of data writing (writing) to the register group 27 is shown. First, the input buffer 61 stores the register address and data input from the host processor 10 via the serial communication line 50 in the address storage unit 62 and the data storage unit 63, respectively. (Step S101).

  Next, the register address in the address storage unit 62 is output to the address decoder 64, and the data in the data storage unit 63 is output to the selector 65. The address decoder 64 decodes the register address and outputs the decoding result to the selector 65 (step S102). Based on the decoding result, the selector 65 selects a register as a write destination, and writes the data in the data storage unit 63 to the register (steps S103 and S104).

  Steps S201 to S204 in FIG. 5 are flowcharts illustrating an example of the operation in the register access unit 26 in FIG. 3, and a processing procedure at the time of data reading (reading) from the register group 27 is shown.

  First, the host controller 1 writes the address (read address) of the register to be read into the RA register 72 in the register group 27 (steps S201 and S202). Next, when a read request for the register group 27 is input from the host processor 11 to the control communication unit 22, the control data held in the register at the address specified by the RA register 72 is read (step S203). Then, the register address (read address) stored in the RA register 72 and the data read from the register are output to the host processor 10 via the serial communication line 50 (step S204).

  Steps S301 to S305 in FIG. 6 are flowcharts showing an example of the image data sending operation in the host controller 1 in FIG. It is assumed that the operation timing of the display processor 11 is controlled by the host processor 10 via the timing control unit 18.

  First, the host processor 10 sends write control data to the serial communication line 50 and writes it to the register group 27 of the LCD controller 2N (step S301). This write control data includes image data format information, write permission information for the video RAM 24, and information necessary for generating an address when writing the image data. When transmission of the write control data is completed, a series of image data is generated and transferred to the LCD controller 2N (steps S302 to S304). The image data generation processing and transfer processing are executed by the display processor 11 in the normal power mode, and executed by the host processor 10 in the power saving mode.

  In the normal power mode, when transmission of the write control data is completed, the host processor 10 notifies the timing control unit 18 of permission to transmit image data, and the display processor 11 starts generating image data (step S302). Next, the display processor 11 sequentially sends the generated image data to the parallel communication line 51 and writes it in the video RAM 24 of the LCD controller 2N (step S303). At this time, the write destination address in the video RAM 24 is generated by the VRAM access unit 23 based on the write control data. The transmission of the image data is repeated until all the image data is transmitted (step S304). When the transmission of all the image data is completed, the timing control unit 18 notifies the host processor 10 of the completion of the image data transfer.

  On the other hand, in the power saving mode, when transmission of the write control data is completed in step S301, the host processor 10 generates image data (step S302), and sequentially transmits the generated image data to the serial communication line 50. Writing to the video RAM 24 of the LCD controller 2N (step S303). At this time, the write destination address in the video RAM 24 is generated by the VRAM access unit 23 based on the write control data. The transmission of the image data is repeated until all the image data is transmitted (step S304).

  When the display processor 11 or the host processor 10 completes sending all the image data, the host processor 10 sends the write control data to the serial communication line 50 again and writes it to the register group 27 of the LCD controller 2N (step S305). This write control data includes information for prohibiting writing to the video RAM 24.

  In this manner, the image data is written by the host controller 1 via the serial communication line 50 or the parallel communication line 51 depending on the operation mode. However, the image data is read serially regardless of the operation mode. This is done via the communication line 50. That is, the image data in the video RAM 24 read by the VRAM access unit 23 is output to the control communication unit 22 and output to the host processor 10 through the serial communication line 50 regardless of the operation mode.

  When displaying an image using the LCD display device 3, it is necessary to write image data from the host controller 1 to the video RAM 24, but it is not necessary for the host controller 1 to read out the image data in the video RAM 24. However, for example, when designing a portable information terminal, it may be necessary to read arbitrary image data in the video RAM 24 for debugging work. By reading such image data through the serial communication line 50, the parallel communication line 51 can be dedicated to data transmission to the LCD controller 2N. Therefore, it is possible to further speed up the transfer of image data performed via the parallel communication line 51 without complicating the control procedure and circuit configuration of the display processor 11.

  Also, when debugging, connecting an external device to the data communication line 50 or 51 between the host controller 1 and the LCD controller 2N and monitoring the transmission data is more compatible with the multi-master bus than the parallel communication line 51. When the serial communication line 50 such as the I2C interface is used, it is easier to connect the external device and read the video RAM 24 from the external device. Therefore, outputting image data read from the video RAM 24 to the serial communication line 50 is also suitable for debugging work.

  Further, the peripheral device control unit 29 is provided in the LCD controller 2N, and the write communication data is transferred using the serial communication line 50 used for transferring the peripheral device control data. The transfer of image data can be speeded up without increasing the number of lines.

  In the power saving mode, the power supply or clock supply to the display processor 11 is cut off and only the host processor 10 operates, so that the power supply or clock supply to the timing control unit 18 is also cut off. Furthermore, power consumption can be reduced.

  In the present embodiment, an example in which the communication line 50 is a parallel communication line and the communication line 51 is a serial communication line has been described, but the present invention is not limited to this. For example, when the communication line 50 is a serial communication line and the communication line is a parallel communication line, or when the two data communication lines 50 and 51 are both parallel communication lines or both are serial communication lines. can do.

  Furthermore, in the present embodiment, the timing processor 18 notifies the host processor 11 of the completion of image data transfer after the display processor 11 finishes transferring one frame of image data to the LCD controller 2N. It is not limited to. For example, a register including a bit indicating whether or not the display processor 11 is transmitting image data is provided in the timing control unit 18, and the host processor 10 polls the register to complete the image data transfer by the display processor 11. You may be the structure which confirms whether it did.

Embodiment 2. FIG.
In the first embodiment, the case where the host processor 10 controls the operation timing of the display processor 11 by transmitting an image data transmission permission signal to the timing control unit 18 has been described. On the other hand, in the present embodiment, a case will be described in which the host processor 10 and the display processor 11 are operating at their own timing.

  The configuration of the second embodiment is the same as that of FIG. 2 described in the first embodiment, but the operations of the host processor 10 and the display processor 11 are operating at their own timing. . Further, it is assumed that the timing control unit 18 manages the state of each processor 10 and 11 and controls each processor 10 and 11 while communicating with the host processor 10 and the display processor 11.

  FIG. 7 is a sequence diagram showing an example of the operation of the timing control unit 18 of FIG. 2, and shows a procedure for transmitting image data generated by the display processor 11 to the LCD controller 2N in the normal power mode. Yes. When outputting the write control data to the serial communication line 50, the host processor 10 outputs a write control data transmission request signal to the timing control unit 18. The timing control unit 18 determines whether or not write control data can be transmitted from the host processor 10 to the LCD controller 2N based on the access status of the display processor 11 to the LCD controller 2N.

  When the host processor 10 receives the transmission permission signal from the timing control unit 18, the host processor 10 transmits the write control data to the LCD controller 2N via the serial communication line 50. When the transmission of the write control data is completed, the host processor 10 outputs a transmission completion notification signal to the timing control unit 18. When the timing control unit 18 receives the transmission completion notification signal from the host processor 10, the timing control unit 18 returns an ACK signal (response signal) to the host controller, and a series of processing for transmitting the write control data to the LCD controller 2N ends.

  On the other hand, the display processor 11 reads out image data in the image data storage unit 12 and generates image data to be written in the video RAM 24. The display processor 11 outputs an image data transmission request signal to the timing controller 18 when transmitting the generated image data to the LCD controller 2N. At this time, if transmission of the write control data by the host processor 10 is not completed, the timing control unit 18 returns a transmission rejection signal to the display processor 11 and does not permit transmission of the image data.

  If the display processor 11 outputs the image data transmission request signal after the transmission of the write control data is completed, the timing control unit 18 determines that the display processor 11 can transmit the image data to the LCD controller 2N, and the display processor 11 11, a transmission permission signal is returned. When the display processor 11 receives the transmission permission signal from the timing control unit 18, the display processor 11 starts transmission of image data to the LCD controller 2N via the parallel communication line 51. When the transmission of the image data is completed, the display processor 11 outputs a transmission completion notification signal to the timing control unit 18, and an ACK signal is returned to the display processor 11 from the timing control unit 18 that has received the transmission completion notification signal. A series of image data transmission processing to the LCD controller 2N is completed.

  According to the present embodiment, even when the host processor 10 and the display processor 11 are operating at independent timings in the normal power mode, after the transmission of the write control data to the LCD controller 2N is completed, Image data can be transmitted.

  In the power saving mode, the display processor 11 is stopped, and the writing control data and the image data are both transferred by the host processor 10, so that the timing control unit 18 is not required. Therefore, it is possible to further reduce power consumption by shutting off the power supply or clock supply to the timing control unit 18.

Embodiment 3 FIG.
In the first and second embodiments, the example in which the write control data is transmitted from the host processor 10 to the LCD controller 2N via the serial communication line 50 regardless of the operation mode has been described. In contrast, in the present embodiment, a case will be described in which the write control data is transferred from the display processor 11 to the LCD controller 2N via the parallel communication line 51 in the normal power mode.

  FIG. 8 is a block diagram showing an example of the configuration of the main part of the portable information terminal according to Embodiment 3 of the present invention. Compared with FIG. 2, the host controller 1 does not include the timing control unit 18. The difference is that the register access unit 26 is connected to both the display communication unit 21 and the control communication unit 22 in the LCD controller 2N.

  In the present embodiment, the display processor 11 transmits write control data to the LCD controller 2N via the parallel communication line 51 prior to transfer of image data. For this reason, the timing control unit 18 for adjusting the operation timing with the host processor 10 is not necessary.

  The parallel communication line 51 includes a select signal line RSP for designating the video RAM 24 or the register group 27 as a write destination. Based on this select signal line RSP, the display communication unit 21 determines whether the received data is image data or write control data, and outputs the data to the VRAM access unit 23 in the case of image data. In the case of embedded control data, it is output to the register access unit 26.

  Further, if there is a conflict in data writing to the register group 27 from the host processor 10 and the display processor 11, the register access unit 26 arbitrates these data writing and sequentially writes to the register group 27. .

It is the block diagram which showed the example of schematic structure of the mobile telephone by embodiment of this invention. FIG. 2 is a block diagram illustrating in detail a main part of the mobile phone in FIG. 1. FIG. 3 is a block diagram showing a more detailed configuration example of a register access unit 26 and a register group 27 in FIG. 4 is a flowchart showing an example of a data write operation in the register access unit 26 of FIG. 3. 4 is a flowchart showing an example of a data read operation in the register access unit 26 of FIG. 3. 3 is a flowchart illustrating an example of an image data transmission operation in the host controller 1 of FIG. 2. FIG. 3 is a sequence diagram illustrating an example of the operation of the timing control unit 18 of FIG. 2, and illustrates a state in which image data is transmitted to the LCD controller 2N in the normal power mode. It is the block diagram which showed one structural example about the principal part of the portable information terminal by Embodiment 3 of this invention. It is the block diagram which showed one structural example about the principal part of the conventional portable information terminal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host controller 2 LCD controller 3 LCD display device 10 Host processor 11 Display processor 12 Image data storage part 13 Program storage part 14 Wireless communication part 15 Camera part 16 Key operation part 18 Timing control part 19 Analog control part 21 Communication part 22 for a display Control communication unit 23 VRAM access unit 24 Video RAM
25 Image data output unit 26 Register access unit 27 Register group 28 Control data output unit 29 Peripheral device control unit 31 Communication unit 32 Driver circuit 33 Liquid crystal display panel 50 to 53 Data communication line 61 Input buffer 62 Address storage unit 63 Data storage unit 64 Address decoder 65 Selector 71 Register 72 RA register

Claims (6)

A display device that displays an image, a host controller that generates image data, and a display controller that is interposed between the display device and the host controller. The image data displayed on the display device is updated per unit time. In portable information terminals that can switch between the normal power mode and the power saving mode with different amounts of data,
The host controller and the display controller are connected by a first data communication line and a second data communication line,
The host controller includes a display processor that generates image data in a normal power mode and a power supply that is cut off in a power saving mode, and a host processor that generates image data in a power saving mode,
A video RAM in which the display controller holds image data input from the display processor via the first data communication line and image data input from the host processor via the second data communication line;
A group of registers for holding peripheral device control data input from the host processor via the second data communication line;
A portable information terminal comprising: a peripheral device control unit that performs signal input / output with a peripheral device that is detachably connected to the portable information terminal based on the peripheral device control data. A display device that displays an image, a host controller that generates image data, and a display controller that is interposed between the display device and the host controller. The image data displayed on the display device is updated per unit time. In portable information terminals that can switch between the normal power mode and the power saving mode with different amounts of data,
The host controller and the display controller are connected by a first data communication line and a second data communication line,
The host controller includes a display processor that generates image data in the normal power mode and a clock supply is cut off in the power saving mode, and a host processor that generates image data in the power saving mode,
A video RAM in which the display controller holds image data input from the display processor via the first data communication line and image data input from the host processor via the second data communication line;
A group of registers for holding peripheral device control data input from the host processor via the second data communication line;
A portable information terminal comprising: a peripheral device control unit that performs signal input / output with a peripheral device that is detachably connected to the portable information terminal based on the peripheral device control data. A VRAM access unit that generates an address of the video RAM as a writing destination based on write control data when writing image data in the normal power mode;
The portable information terminal according to claim 1 or 2, wherein the register group holds the write control data input from the host controller. In the normal power mode, the storage area in the video RAM corresponding to the entire display screen of the display device is updated,
3. The portable information terminal according to claim 1, wherein only a storage area in the video RAM corresponding to a part of the display screen is updated in the power saving mode.   3. The portable information terminal according to claim 1, wherein the amount of information per pixel constituting the image data stored in the video RAM is smaller in the power saving mode than in the normal power mode.   3. The portable information terminal according to claim 1, wherein the update period of the image data stored in the video RAM is longer in the power saving mode than in the normal power mode.

Images