JP2016105520A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which enables the increase in yield of semiconductor devices.SOLUTION: A method for manufacturing semiconductor device comprises the steps of: forming an insulative film 11 over a semiconductor substrate 1; polishing an upper surface of the insulative film 11 according to a chemical mechanical polishing method; forming holes 11a in the insulative film 11; forming a first conductive film 17 on the upper surface of the insulative film 11, and inner faces of the holes 11a; forming a mask film 41a of photoresist in each hole 11a; removing, by etching, the first conductive film 17 on the upper surface of the insulative film 11; removing the mask film 41a; and forming a second conductive film on the first conductive film 17 in each hole 11a.SELECTED DRAWING: Figure 17

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A semiconductor device such as an LSI is manufactured by laminating a plurality of wirings and insulating films. Irregularities that reflect the underlying wiring, gate electrodes, and the like are formed on the upper surface of the insulating film, but the irregularities reduce the patterning accuracy of the insulating film and prevent miniaturization of the semiconductor device.

  Therefore, after forming an insulating film, the insulating film may be polished by chemical mechanical polishing (CMP). CMP is to polish the insulating film with a polishing pad while supplying slurry to the upper surface of the insulating film, and the upper surface of the insulating film can be flattened by the polishing.

  However, when foreign matter such as polishing scraps or particles is mixed in the slurry, the foreign matter may cause fine scratches called scratches on the upper surface of the insulating film. When the conductive material is embedded in the scratch, adjacent contact plugs are electrically short-circuited, and the yield of the semiconductor device is reduced.

  In order to prevent such a short circuit, methods for removing the conductive material embedded in the scratches have been provided, but there is room for improvement in any case.

  For example, a method has been proposed in which a contact plug made of tungsten is embedded in an insulating film, and then the entire surface of the insulating film is etched back by plasma etching to remove tungsten embedded in the scratches on the insulating film. . However, in this method, since the contact plug is exposed to the etching atmosphere, the surface of the contact plug may be altered and a contact failure may occur.

JP-A-10-56014

  An object of the method for manufacturing a semiconductor device is to improve the yield of the semiconductor device.

  According to one aspect of the following disclosure, a step of forming a first insulating film above a semiconductor substrate, a step of polishing an upper surface of the first insulating film by a chemical mechanical polishing method, and after the polishing, Forming a first hole in the first insulating film; forming a first conductive film on an upper surface of the first insulating film; and an inner surface of the first hole; and A step of applying a photoresist on the film; a step of exposing the photoresist; and developing the photoresist after the exposure to leave the photoresist as a mask film in the first hole. However, the step of removing the photoresist from above the first insulating film, and etching the portion of the first conductive film that is not covered with the mask film on the upper surface of the first insulating film. Removing the process, After the step of removing the first conductive film by etching, the step of removing the mask film in the first hole and the step of removing the mask film, then the first film in the first hole. There is provided a method for manufacturing a semiconductor device including a step of forming a second conductive film over one conductive film.

  According to the following disclosure, the first conductive film on the upper surface of the first insulating film is removed, and the second conductive film is formed on the first conductive film left on the inner surface of the first hole. . Therefore, even when a scratch is formed on the upper surface of the first insulating film during polishing by the chemical mechanical polishing method, the first conductive film and the second conductive film are not embedded in the scratch. As a result, the risk of an electrical short between the second conductive films in the plurality of first holes due to the first conductive film and the second conductive film in the scratch is reduced, and the yield of the semiconductor device is reduced. Can be improved.

FIGS. 1A and 1B are cross-sectional views (part 1) of the semiconductor device used for the investigation in the middle of manufacture. FIGS. 2A and 2B are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device used for the investigation. 3A and 3B are cross-sectional views (part 3) of the semiconductor device used for the investigation in the course of manufacturing. FIGS. 4A and 4B are cross-sectional views (part 4) in the middle of manufacturing the semiconductor device used for the investigation. FIGS. 5A and 5B are cross-sectional views (part 5) in the middle of manufacturing the semiconductor device used for the investigation. 6A and 6B are cross-sectional views (part 6) of the semiconductor device used for the investigation in the middle of manufacture. FIG. 7 is a sectional view (No. 7) of the semiconductor device used for the investigation in the middle of manufacture. FIG. 8 is a plan view drawn based on an SEM (Scanning Electron Microscope) image of the upper surface of the first interlayer insulating film after the process of FIG. FIGS. 9A and 9B are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 10A and 10B are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device according to the first embodiment. FIGS. 11A and 11B are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view (part 4) of the semiconductor device according to the first embodiment during manufacture. FIG. 13 is a sectional view (No. 5) of the semiconductor device according to the first embodiment in the middle of manufacture. FIG. 14 is a plan view schematically showing the upper surface of the first interlayer insulating film in which scratches are formed in the first embodiment. 15A and 15B are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the second embodiment. 16A and 16B are cross-sectional views (part 2) of the semiconductor device according to the second embodiment during manufacture. FIGS. 17A and 17B are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device according to the second embodiment. FIG. 18 is a cross-sectional view (part 4) of the semiconductor device according to the second embodiment in the middle of manufacture. FIG. 19 is a cross-sectional view showing an exposure light irradiation region when a positive photoresist is used in the second embodiment.

  Prior to the description of the present embodiment, the investigation results of the inventors will be described.

  1-7 is sectional drawing in the middle of manufacture of the semiconductor device used for the investigation.

  In order to manufacture this semiconductor device, first, as shown in FIG. 1A, an element isolation trench is formed in a silicon substrate 1, and silicon oxide is used as an element isolation insulating film 2 that defines an active region in the trench. Embed the membrane. Such an element isolation structure is called STI (Shallow Trench Isolation). Alternatively, element isolation may be performed by LOCOS (Local Oxidation of Silicon). The silicon substrate 1 is an example of a semiconductor substrate.

  Next, p-type impurities are ion-implanted into the active region of the silicon substrate 1 to form a p-well 3.

  Further, a thermal oxide film to be the gate insulating film 4 is formed by thermally oxidizing the silicon substrate 1 in the active region. Then, a polysilicon film is formed on the thermal oxide film by a CVD method, and the polysilicon film is patterned to form the gate electrode 5.

  Subsequently, using the gate electrode 5 as a mask, an n-type impurity is ion-implanted into the silicon substrate 1 to form an n-type source / drain extension 6.

  Next, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to form an insulating sidewall 7 next to the gate electrode 5. As the insulating film, for example, a silicon oxide film is formed by a CVD method.

  Then, an n-type source / drain region 8 is formed by ion-implanting n-type impurities into the silicon substrate 1 using the insulating sidewall 7 and the gate electrode 5 as a mask.

  Further, after a metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 1 by sputtering, the metal film is heated and reacted with silicon, thereby forming a cobalt silicide layer as the metal silicide layer 9.

  Thereafter, the unreacted metal film on the element isolation insulating film 2 and the like is removed by wet etching.

  As described above, the MOS transistor TR including the gate electrode 5 and the n-type source / drain region 8 is formed on the silicon substrate 1.

  Next, as shown in FIG. 1B, a silicon oxide film is formed on the silicon substrate 1 and the gate electrode 5 by a CVD method to a thickness of about 1 nm to 7 nm, and the silicon oxide film is formed on the first interlayer. The insulating film 11 is used.

  Here, a convex portion 11 y reflecting the underlying gate electrode 5 is formed on the upper surface x of the first interlayer insulating film 11. The convex portion 11y prevents the first interlayer insulating film 11 from being patterned with high accuracy, and prevents the formation of a fine contact hole in the first interlayer insulating film 11 in a later step.

  Therefore, in the next step, as shown in FIG. 2A, the convex portion 11y is removed by performing CMP on the upper surface 11x of the first interlayer insulating film 11, and the upper surface 11x is flattened.

  Further, when CMP is performed in this manner, foreign matters such as polishing scraps and particles may be mixed in the slurry, and the foreign matter may form scratches 11z on the upper surface 11x.

  Subsequently, as shown in FIG. 2B, a first resist film 15 having an opening 15a is formed by applying a photoresist on the flattened upper surface 11x, exposing and developing it. To do.

  Here, in this example, since the upper surface 11x is planarized beforehand by CMP before forming the first resist film 15, the flatness of the first resist film 15 is also improved, and the first resist film 15 The processing accuracy of the opening 15a is improved.

Then, the first interlayer insulating film 11 is dry-etched through the opening 15 a by RIE (Reactive Ion Etching) method to form a contact hole 11 a on the n-type source / drain region 8. As an etching gas used in this dry etching, for example, there is a mixed gas of C ₄ F ₈ gas, Ar gas, and O ₂ gas.

  Since the processing accuracy of the opening 15a is good as described above, the contact hole 11a can also be formed with high accuracy.

  Thereafter, as shown in FIG. 3A, the first resist film 15 is removed by ashing.

  Next, as shown in FIG. 3B, a titanium film and a titanium nitride film are sputtered in this order as the first conductive film 17 on the upper surface 11x of the first interlayer insulating film 11 and the inner surface of the contact hole 11a. Form by law. Although the thickness of these films is not particularly limited, the titanium film is formed to a thickness of about 5 nm to 30 nm, and the titanium nitride film is formed to a thickness of about 5 nm to 10 nm.

  Further, since the scratch 11z is formed on the upper surface 11x as described above, the first conductive film 17 is also formed in the scratch 11z.

  Note that the first conductive film 17 is not limited to a stacked film of a titanium film and a titanium nitride film. As the first conductive film 17, a single layer film of a titanium film, a tantalum film, a titanium nitride film, and a tantalum nitride film, or a stacked film thereof can be formed.

  Subsequently, as shown in FIG. 4A, a tungsten film is formed as a second conductive film 18 on the first conductive film 17 by a thermal CVD method, and the contact hole 11a is formed by the second conductive film 18. Completely fill.

The tungsten film is formed under the conditions that the pressure of the film formation atmosphere is 40 Torr and the substrate temperature is 390 ° C. As a tungsten film deposition gas, a mixed gas of tungsten hexafluoride (WF ₆ ) gas having a flow rate of 50 sccm, hydrogen gas having a flow rate of 200 sccm, and silane (SiH ₄ ) gas having a flow rate of 200 sccm is used. To do.

  When such conditions are employed, the tungsten film grows on the entire upper surface of the silicon substrate 1 regardless of the underlying material. However, when the first conductive film 17 is formed as a base as in this example, the first conductive film 17 serves as a nucleus to promote the growth of the tungsten film, and the tungsten film and the first interlayer insulating film 11 is also improved. Thus, the first conductive film 17 responsible for promoting growth and improving adhesion is also called a glue film.

  In addition, since the scratch 11z is formed on the upper surface 11x of the first interlayer insulating film 11 as described above, the second conductive film 18 is also formed in the scratch 11z.

  Next, as shown in FIG. 4B, by performing CMP on the first conductive film 17 and the second conductive film 18, the extra first conductive film 17 and the first conductive film 17 on the upper surface 11x. The two conductive films 18 are removed, and these films are left as contact plugs 18a in the contact holes 11a.

  In this CMP, even if the polishing amount is large, the first conductive film 17 and the second conductive film 18 may remain in the scratch 11z.

  Subsequently, as shown in FIG. 5A, a second interlayer insulating film 19 is formed on the contact plug 18a and the first interlayer insulating film 11 to a thickness of about 150 nm to 300 nm. As the second insulating film 18, it is preferable to form a low dielectric constant insulating film having a dielectric constant lower than that of the silicon oxide film in order to increase the device speed. In this example, the second interlayer insulating film 19 is made of SiOC. A film is formed.

  Thereafter, a silicon carbide (SiC) film is formed to a thickness of about 30 nm to 70 nm on the second interlayer insulating film 19 by the CVD method, and the silicon carbide film is used as the first antireflection insulating film 20. Note that a silicon nitride (SiN) film may be formed as the first antireflection insulating film 20 instead of the silicon carbide film.

  Subsequently, as shown in FIG. 5B, a second resist film 21 having an opening 21a is formed by applying a photoresist on the first antireflection insulating film 20, exposing and developing it. Form.

  Further, the second interlayer insulating film 19 and the first antireflection insulating film 20 are dry-etched through the opening 21a to form the first wiring groove 19a.

  Thereafter, the second resist film 21 is removed by ashing.

  Next, as shown in FIG. 6A, a tantalum nitride film is formed on the inner surface of the first wiring groove 19a and the upper surface of the first antireflection insulating film 20 as a barrier metal film 23 by a sputtering method to a thickness of about 5 nm to 30 nm. Form to thickness. Note that any of a titanium film, a titanium nitride film, and a tantalum film may be formed as the barrier metal film 23 instead of the tantalum nitride film.

  Next, as shown in FIG. 6B, after forming a copper film (not shown) on the barrier metal film 23 by sputtering, the third conductive film 24 is formed by electrolytic plating using the copper film as a power feeding layer. A copper plating film is formed, and the first wiring groove 19a is filled with the third conductive film 24.

  Note that the third conductive film 24 is not limited to a copper plating film, and an aluminum film may be formed as the third conductive film 24 by a sputtering method.

  Then, as shown in FIG. 7, the excess barrier metal film 23 and the third conductive film 24 on the first antireflection insulating film 20 are removed by polishing with CMP, and these films are removed from the first antireflection insulating film 20. The first wiring 24a is left only in the wiring groove 19a. Note that the method of forming the wiring in the groove by polishing in this way is called a damascene method.

  Thus, the basic structure of the semiconductor device used for this investigation was completed.

  In the above example, as shown in FIG. 4B, the first conductive film 17 and the second conductive film 18 may remain in the scratch 11z generated by CMP.

  FIG. 8 is a plan view drawn based on an SEM (Scanning Electron Microscope) image of the upper surface of the first interlayer insulating film 11 after the process of FIG.

  As shown in FIG. 8, the scratch 11z is linear in a plan view, and in a part of the first interlayer insulating film 11, the scratch 11z is formed across a plurality of contact plugs 18a. In this case, the plurality of contact plugs 18a are electrically short-circuited by the first conductive film 17 and the second conductive film 18 remaining in the scratch 11z, and the semiconductor device becomes defective.

  In order to prevent such a short circuit, it is considered that the first conductive film 17 and the second conductive film 18 in the scratch 11z may be removed. However, if the contact plug 18a is damaged when the first conductive film 17 and the second conductive film 18 are removed, a contact failure may occur in the contact plug 18a.

  Hereinafter, an embodiment capable of preventing a short circuit between the contact plugs 18a while suppressing such contact failure will be described.

(First embodiment)
9 to 13 are cross-sectional views of the semiconductor device according to the first embodiment being manufactured. 9 to 13, the same elements as those described in FIGS. 1 to 7 are denoted by the same reference numerals as those in FIGS. 1 to 7, and description thereof is omitted below.

  In this embodiment, first, by performing the steps shown in FIGS. 1A to 3B, the upper surface 11x of the first interlayer insulating film 11 and the contact hole 11a as shown in FIG. 9A. A first conductive film 17 is formed on the inner surface.

  At this time, the scratch 11z is formed on the upper surface 11x due to the CMP performed on the first interlayer insulating film 11 in the step of FIG. A first conductive film 17 is formed.

  Next, as shown in FIG. 9B, a mask film 30 is formed on the first conductive film 17. As a material of the mask film 30, there is a resin or a photoresist. Among these, photoresist is particularly suitable as a material for the mask film 30 because it is easily available. When a photoresist is used, the mask film 30 can be formed by forming a photoresist coating and then baking the coating.

  Subsequently, as shown in FIG. 10A, the entire surface of the mask film 30 is etched back by RIE, so that the mask film 30 remains in the contact hole 11a and the upper surface 11x of the first interlayer insulating film 11 is formed. The upper mask film 30 is removed.

The conditions for this RIE are not particularly limited. In this embodiment, O ₂ gas having a flow rate of 950 sccm is supplied to the etching chamber as an etching gas, and the pressure in the etching chamber is maintained at about 200 mTorr. Then, the substrate temperature is maintained at 25 ° C., and high-frequency power having a frequency of 13.56 MHz and a power of 600 W is applied to the O ₂ gas to generate oxygen plasma and perform the RIE.

  Next, as shown in FIG. 10B, the portion of the first conductive film 17 not covered with the mask film 30 is removed by etching in an unillustrated ICP (Inductively Coupled Plasma) etching chamber. Then, the upper surface 11x and the scratch 11z of the first interlayer insulating film 11 are exposed.

As an etching gas in this step, a mixed gas of BCl ₃ gas, Cl ₂ gas, CHF ₃ gas, and Ar gas can be used. The flow rates of these gases are, for example, 80 sccm for BCl ₃ gas, 200 sccm for Cl ₂ gas, 10 sccm for CHF ₃ gas, and 80 sccm for Ar gas.

  In this embodiment, the pressure in the etching chamber is maintained at 6 mTorr while supplying these gases to the ICP etching chamber. In addition, a high frequency power for bias having a frequency of 13.56 MHz or 800 Hz and a power of 125 W is applied to the silicon substrate 1 side, and a high frequency power for plasma formation having a frequency of 13.56 MHz and a power of 700 W is applied to the etching gas. This etching is performed.

  Note that this step may be performed by wet etching instead of RIE. As an etchant that can be used in the wet etching, for example, there is a nitric acid-based liquid.

  Thereafter, as shown in FIG. 11A, the mask film 30 in the contact hole 11a is removed by dry etching by RIE using a mixed gas of ammonia gas and nitrogen gas as an etching gas.

  Although the flow rate of the etching gas is not particularly limited, in this embodiment, the flow rate of ammonia gas is 300 sccm, the flow rate of nitrogen gas is 50 sccm, and the pressure in the etching chamber is maintained at 300 mTorr. Further, by applying high frequency power having a frequency of 13.56 MHz and a power of 100 W in the etching chamber, the etching gas is turned into plasma and the above RIE is performed.

  Subsequently, as shown in FIG. 11B, a tungsten film is formed on the first conductive film 17 left in the contact hole 11a by a thermal CVD method, and the tungsten film is used as a contact plug 18a. Note that the tungsten film is an example of a second conductive film.

  As a method for growing the tungsten film, in addition to the method for growing the tungsten film on the entire upper surface of the silicon substrate 1 as shown in FIG. 4A, the selective growth for selectively growing the tungsten film only on the conductive film. There is a law.

  In this embodiment, by adopting the selective growth method, a tungsten film is selectively grown only on the first conductive film 17 and no tungsten film is grown on the first interlayer insulating film 11.

  The conditions for forming the tungsten film are not particularly limited. However, as compared with the case where a tungsten film is formed on the entire upper surface of the silicon substrate 1 as shown in FIG. 4A, the substrate temperature is lowered, the flow rate of the silane gas is lowered, the pressure of the deposition atmosphere is lowered, and the like. It becomes easy to prevent the tungsten film from being formed on the one insulating film 11.

  Therefore, in the present embodiment, the substrate temperature when forming the tungsten film is set to 300 ° C., and the pressure of the film forming atmosphere is set to 300 mTorr. Further, as a film forming gas for the tungsten film, a mixed gas of tungsten hexafluoride gas having a flow rate of 50 sccm, hydrogen gas having a flow rate of 200 sccm, and silane gas having a flow rate of 10 sccm is used.

  By adopting such conditions, the tungsten film is not embedded in the scratch 11z in which the first conductive film 17 is not formed, and the plurality of contact plugs 18a are electrically connected by the tungsten film in the scratch 11z. Can reduce the risk.

  Next, as shown in FIG. 12, by performing the same steps as FIG. 5A to FIG. 7, the second interlayer insulating film 19 and the first antireflection insulating film 20 are formed in this order. The first wiring 24a is embedded in the insulating film by a damascene method.

  Next, steps required until a sectional structure shown in FIG.

  First, a SiOC film having a thickness of 150 nm to 250 nm is formed as the third interlayer insulating film 32 on each of the first wiring 24a and the first antireflection insulating film 20 by the CVD method.

  Then, by patterning the third interlayer insulating film 32, a hole 32a is formed on the first wiring 24a, and a conductor plug 33 is formed in the hole 32a. As with the contact plug 18a, the conductor plug 33 forms a glue film and a tungsten film in this order in the hole 32a, and then forms an extra glue film and tungsten film on the third interlayer insulating film 32 by CMP. It is formed by polishing and removing.

  Further, a fourth interlayer insulating film 34 and a second antireflection insulating film 35 are formed in this order on the conductor plug 33 and the third interlayer insulating film 32 by the CVD method. Among these, the fourth interlayer insulating film 34 is a SiOC film having a thickness of about 150 nm to 300 nm, and the second antireflection insulating film 35 is a silicon carbide film or a silicon nitride film having a thickness of about 50 nm to 100 nm. .

  Then, the fourth interlayer insulating film 34 and the second antireflection insulating film 35 are patterned to form a second wiring groove 34a in these insulating films. Thereafter, a copper plating film is embedded in the second wiring groove 34a as the second wiring 40 by the damascene method. The second wiring 40 is not limited to a copper plating film, and an aluminum film may be formed as the second wiring 40 by a sputtering method.

  As described above, the basic structure of the semiconductor device according to this embodiment is completed.

  According to the above-described embodiment, since the first conductive film 17 in the scratch 11z is removed in the step of FIG. 10B, the tungsten film is formed by the selective growth method in the step of FIG. Furthermore, no tungsten film grows in the scratch 11z.

  FIG. 14 is a plan view schematically showing the upper surface of the first interlayer insulating film 11 in which the scratch 11z is formed in the present embodiment.

  As shown in FIG. 14, even if the scratch 11z is formed across the plurality of contact plugs 18a, the tungsten film does not exist in the scratch 11z as described above, so that the contact plugs 18a are electrically connected to each other by the tungsten film. The risk of short circuiting can be reduced.

  Thereby, it is possible to prevent the semiconductor device from being defective due to a short circuit between the contact plugs 18a, and it is possible to improve the yield of the semiconductor device.

  Moreover, according to this method, tungsten is not already present in the scratch 11z when the contact plug 18a is formed in the step of FIG. 11B. Therefore, after the contact plug 18a is formed, it is not necessary to perform plasma etching for the purpose of removing tungsten in the scratch 11z, and there is no possibility that the contact plug 18a is damaged by the plasma etching and a contact failure occurs.

  In this embodiment, the tungsten film is prevented from being embedded in the scratch 11z on the upper surface 11x of the first interlayer insulating film 11, but this is applied to the interlayer insulating film above the first interlayer insulating film 11. May be. The same applies to the second embodiment described later.

(Second Embodiment)
In the first embodiment, as shown in FIG. 10A, the mask film 30 is etched back to leave the mask film 30 only in the contact hole 11a.

  On the other hand, in the present embodiment, the mask film is left only in the contact hole 11a by exposing and developing the photoresist as follows.

  15 to 18 are cross-sectional views in the middle of manufacturing the semiconductor device according to this embodiment. 15 to 18, the same elements as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted below.

  To manufacture the semiconductor device according to the present embodiment, first, the first interlayer insulation is performed as shown in FIG. 15A by performing the steps shown in FIGS. A first conductive film 17 is formed on the upper surface 11x of the film 11 and the inner surface of the contact hole 11a.

  Next, as shown in FIG. 15B, a negative photoresist 41 is applied on the first conductive film 17, and after filling the contact hole 11 a with the photoresist 41, the photoresist 41 is heated. Bake.

  Next, as shown in FIG. 16A, the photoresist 41 is exposed by irradiating the exposure light L to the photoresist 41 in the contact hole 11a. Note that the photoresist 41 outside the contact hole 11a is not irradiated with the exposure light L, and the photoresist 41 is left unexposed.

  The irradiation area of the exposure light L on the surface of the photoresist 41 is determined by a reticle (not shown). However, by using a reticle for the contact hole 11a as the reticle, there is no need to manufacture a dedicated reticle for this process, and the semiconductor The cost of the apparatus can be reduced.

  The photoresist 41 is a negative type, but a positive type photoresist 41 may be used instead.

  FIG. 19 is a cross-sectional view showing an irradiation region of the exposure light L when a positive photoresist 41 is used. As shown in FIG. 19, in this case, the photoresist 41 outside the contact hole 11a is exposed with the exposure light L, and the photoresist 41 in the contact hole 11a is not irradiated with the exposure light L, and the photoresist 41 is exposed. Is unexposed.

  Next, as shown in FIG. 16B, the photoresist 41 is developed to leave the photoresist 41 as a mask film 41a in the contact hole 11a, and above the upper surface 11x of the first interlayer insulating film 11. The photoresist 41 is removed.

  Then, as shown in FIG. 17A, a portion of the first conductive film 17 that is not covered with the mask film 41a is etched and removed in an ICP etching chamber (not shown), thereby providing a first interlayer insulation. The upper surface 11x and the scratch 11z of the film 11 are exposed.

The etching conditions in this step are not particularly limited. In this embodiment, a mixed gas of BCl ₃ gas, Cl ₂ gas, CHF ₃ gas, and Ar gas is used as an etching gas for this etching. The flow rate of BCl ₃ gas is 80 sccm, the flow rate of Cl ₂ gas is 200 sccm, the flow rate of CHF ₃ gas is 10 sccm, and the flow rate of Ar gas is 80 sccm.

  Further, while supplying these gases to the ICP etching chamber, the pressure in the etching chamber is maintained at 6 mTorr. In addition, a high frequency power for bias having a frequency of 13.56 MHz and a power of 125 W is applied to the silicon substrate 1 side, and a high frequency power for plasma formation having a frequency of 13.56 MHz and a power of 700 W is applied to the etching gas. This etching is performed.

  As in the first embodiment, this step may be performed by wet etching instead of RIE.

  Next, as shown in FIG. 17B, the mask film 41a in the contact hole 11a is removed by dry etching by RIE using a mixed gas of ammonia gas and nitrogen gas as an etching gas.

  Since the etching conditions are the same as those in FIG. 11A of the first embodiment, they are omitted here.

  Then, as shown in FIG. 18, a thermal CVD method is performed on the first conductive film 17 remaining in the contact hole 11a by a selective growth method under the same conditions as in FIG. 11B of the first embodiment. A tungsten film is formed, and the tungsten film is used as a contact plug 18a.

  As described in the first embodiment, in the selective growth method, a tungsten film grows only on the first conductive film 17, and no tungsten film grows in the scratch 11z.

  Thereafter, the same steps as those in FIGS. 12 to 13 described in the first embodiment are performed to complete the basic structure of the semiconductor device according to the present embodiment.

  Also in the present embodiment described above, since the tungsten film is not grown in the scratch 11z, the risk that the plurality of contact plugs 18a are electrically short-circuited due to the tungsten film in the scratch 11z can be reduced.

  The following additional notes are disclosed with respect to the above-described embodiments.

(Additional remark 1) The process of forming a 1st insulating film above a semiconductor substrate,
Polishing the upper surface of the first insulating film by a chemical mechanical polishing method;
Forming a first hole in the first insulating film after the polishing;
Forming a first conductive film on an upper surface of the first insulating film and an inner surface of the first hole;
Removing the first conductive film on the top surface of the first insulating film while leaving the first conductive film on the inner surface of the first hole;
After the step of removing the first conductive film, forming a second conductive film on the first conductive film in the first hole;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary note 2) In the step of forming the second conductive film, a tungsten film is selectively grown as the second conductive film on the first conductive film. A method for manufacturing a semiconductor device.

(Supplementary Note 3) The step of removing the first conductive film includes:
Forming a mask film covering the first conductive film on the inner surface of the first hole;
The method according to claim 1 or 2, further comprising: etching and removing the portion of the first conductive film that is not covered with the mask film on the upper surface of the first insulating film. A method for manufacturing a semiconductor device.

(Supplementary Note 4) The step of forming the mask film includes:
Forming the mask film on the first conductive film;
Etching the mask film to remove the mask film above the upper surface of the first insulating film while leaving the mask film in the first hole. A manufacturing method of a semiconductor device according to attachment 3.

  (Additional remark 5) Resin or a photoresist is used as a material of the said mask film | membrane, The manufacturing method of the semiconductor device of Additional remark 4 characterized by the above-mentioned.

(Supplementary Note 6) The step of forming the mask film includes:
Applying a photoresist on the first conductive film;
Exposing the photoresist;
After the exposure, the photoresist is developed to remove the photoresist from above the first insulating film while leaving the photoresist as the mask film in the first hole. A method for manufacturing a semiconductor device according to Supplementary Note 3.

(Appendix 7) The photoresist is a negative type,
7. The semiconductor according to appendix 6, wherein in the step of exposing the photoresist, the photoresist in the first hole is exposed, and the photoresist outside the first hole is unexposed. Device manufacturing method.

  (Appendix 8) The photoresist is a positive type, and in the step of exposing the photoresist, the photoresist outside the first hole is exposed, and the photoresist in the first hole is unexposed. A method for manufacturing a semiconductor device, comprising:

  (Additional remark 9) The said 1st electrically conductive film is a single layer film in any one of a titanium film, a tantalum film, a titanium nitride film, and a tantalum nitride film, or these laminated films, 9. A method for manufacturing a semiconductor device according to claim 8.

(Supplementary Note 10) After the step of forming the second conductive film, a step of forming a second insulating film on the first insulating film;
Forming a second hole in the second insulating film;
The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, further comprising a step of forming a third conductive film inside the second hole.

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... p well, 4 ... gate insulating film, 5 ... gate electrode, 6 ... n-type source / drain extension, 7 ... insulating side wall, 8 ... n-type source / drain region , 9 ... Metal silicide layer, 11 ... First interlayer insulating film, 11a ... Contact hole, 11x ... Upper surface, 11y ... Projection, 11z ... Scratches, 15 ... First resist film, 15a ... Opening, 17 ... First , 18 ... second conductive film, 18a ... contact plug, 19 ... second interlayer insulating film, 19a ... first wiring groove, 20 ... first antireflection insulating film, 21 ... second resist Film, 21a ... opening, 23 ... barrier metal film, 24 ... third conductive film, 24a ... first wiring, 30 ... mask film, 32 ... third interlayer insulating film, 32a ... hole, 33 ... conductor plug, 34. Fourth interlayer insulating film, 3 ... second dielectric antireflective film, 40 ... second wiring 41 ... photoresist, 41a ... mask film.

Claims (2)

Forming a first insulating film over the semiconductor substrate;
Polishing the upper surface of the first insulating film by a chemical mechanical polishing method;
Forming a first hole in the first insulating film after the polishing;
Forming a first conductive film on an upper surface of the first insulating film and an inner surface of the first hole;
Applying a photoresist on the first conductive film;
Exposing the photoresist;
Developing the photoresist after the exposure, removing the photoresist from above the first insulating film while leaving the photoresist as a mask film in the first hole;
Etching and removing the portion of the first conductive film that is not covered with the mask film on the upper surface of the first insulating film;
After removing the first conductive film by etching, removing the mask film in the first hole;
Forming a second conductive film on the first conductive film in the first hole after the step of removing the mask film;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the same reticle as that used for forming the first hole is used as a reticle for exposing the photoresist.

Images