JP2012503884A - 3次元ic積層のための、ウェハとダイとの低コストのアライメント及びボンディング - Google Patents
3次元ic積層のための、ウェハとダイとの低コストのアライメント及びボンディング Download PDFInfo
- Publication number
- JP2012503884A JP2012503884A JP2011529131A JP2011529131A JP2012503884A JP 2012503884 A JP2012503884 A JP 2012503884A JP 2011529131 A JP2011529131 A JP 2011529131A JP 2011529131 A JP2011529131 A JP 2011529131A JP 2012503884 A JP2012503884 A JP 2012503884A
- Authority
- JP
- Japan
- Prior art keywords
- dies
- die
- stacked
- wafer
- aligning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 38
- 238000010586 diagram Methods 0.000 description 19
- 230000002950 deficient Effects 0.000 description 12
- 238000007796 conventional method Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Die Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Dicing (AREA)
Abstract
【選択図】図6
Description
Claims (18)
- 積層IC装置のためにダイを配置する方法であって、
第1の複数のダイが対称軸を有するように前記積層IC装置の第1の層についての前記第1の複数のダイの方向を合わせることと、
第2の複数のダイが対称軸を有するように、前記積層ICの第2の層についての前記第2の複数のダイの方向を合わせることと、
前記積層IC装置の製造中に前記第1及び前記第2の複数のダイを積層可能とするよう、前記第2の複数のダイの前記対称軸に前記第1の複数のダイの前記対称軸をアライメントさせることと、を備えた方法。 - 前記第1及び前記第2の複数のダイの前記対称軸は、水平方向で対称である請求項1の方法。
- 前記第1及び前記第2の複数ダイに対する他の対称軸は、垂直方向に対して対称である請求項2の方法。
- 前記第1及び前記第2の複数のダイに対する前記対称軸は、垂直方向に対して対称である請求項1の方法。
- 前記第1の複数のダイは、少なくとも2つのダイを備え、
前記第2の複数のダイは、少なくとも2つのダイを備える請求項1の方法。 - 前記第1の複数のダイは、前記第2の複数のダイと同じ数のダイを含む請求項1の方法。
- 前記第1のダイは、少なくとも4つのダイを備え、
前記第2の複数のダイは、少なくとも4つのダイである請求項1の方法。 - 前記第1の複数のダイは、ウェハから切り取られたダイである請求項1の方法。
- 前記第2の複数のダイは、ウェハから切り取られたダイである請求項8の方法。
- 前記第2の複数のダイは、ウェハから切り取られていないダイである請求項8の方法。
- 前記第1の複数のダイは、モノリシックウェハから切り取れられる請求項8の方法。
- スクライブされる際に、スクライブラインが切り取られるよう、前記複数のダイの各々の前記スクライブラインに前記アライメントインジケータが配置される請求項1の方法。
- 第1の複数のダイの個々のダイの各々の歩留まりに基づいて第1の層について第1のビン(bin)に前記第1の複数のダイを入れること(binning)と、
第2の複数のダイの歩留まりに対応する前記第1の複数のダイ、及び前記第2の複数のダイの個々のダイの各々の歩留まりに基づいて、第2の層のために第2のビンに第2の複数のダイを入れることと、を備えた積層IC装置の製造工程における歩留まりの改良方法。 - 更に、第1の共通の始点を有するよう、前記第1の複数のダイの方向を合わせ、第2の共通の始点を有するよう、前記第2のダイの方向を合わせること、を備えた請求項13の方法。
- 更に、単一アライメントに基づいて、前記第2のダイから取り出した前記第2の複数のダイと前記第1のビンから取り出した前記第1の複数のダイとを積層させること、を備える請求項14の方法。
- 第1のアライメントポイントに基づいて積層IC装置の第1の層についての、第1のダイのグループをアライメントことと、
前記第1のアライメントポイントに基づいて前記第1のダイのグループを備えた前記積層IC装置の第2の層についての、第2のダイのグループをアライメントすることと、を備えた複数のダイをアライメントする方法。 - 第1の複数のダイが、水平方向及び垂直方向に対して対称軸を有するよう、積層IC装置の第1層についての前記第1の複数のダイの方向を合わせることと、
第2の複数のダイが、水平方向及び垂直方向に対して対称軸を有するよう、前記IC装置の第2層についての前記第2の複数のダイの方向を合わせることと、
前記積層IC装置の製造中に前記第1及び前記第2の複数のダイを積層可能とするよう、前記第2の複数のダイの前記対称軸に対して前記第1の複数のダイの前記対称軸をアライメントすること
と、を備えたステップによって製造される積層IC装置。 - レシーバダイグループ間の距離に基づき、テンプレートブロック上に予めドナーダイグループの集合体をアライメントすることと、
前記集合体の単一のドナーダイグループ及び単一のレシーバダイグループのアライメントに基づき複数のレシーバダイグループをドナーダイグループの集合体に積層することと、を備えた積層IC装置の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/236,967 | 2008-09-24 | ||
US12/236,967 US8796073B2 (en) | 2008-09-24 | 2008-09-24 | Low cost die-to-wafer alignment/bond for 3d IC stacking |
PCT/US2009/057515 WO2010036579A2 (en) | 2008-09-24 | 2009-09-18 | Low cost die-to-wafer alignment/bond for 3d ic stacking |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2012503884A true JP2012503884A (ja) | 2012-02-09 |
Family
ID=41210963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011529131A Pending JP2012503884A (ja) | 2008-09-24 | 2009-09-18 | 3次元ic積層のための、ウェハとダイとの低コストのアライメント及びボンディング |
Country Status (7)
Country | Link |
---|---|
US (1) | US8796073B2 (ja) |
EP (1) | EP2342748A2 (ja) |
JP (1) | JP2012503884A (ja) |
KR (1) | KR101252036B1 (ja) |
CN (1) | CN102160173A (ja) |
TW (1) | TW201029085A (ja) |
WO (1) | WO2010036579A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016139914A1 (en) | 2015-03-05 | 2016-09-09 | Sony Corporation | Semiconductor device and manufacturing method, and electronic appliance |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8127185B2 (en) * | 2009-01-23 | 2012-02-28 | Micron Technology, Inc. | Memory devices and methods for managing error regions |
CN103178052B (zh) * | 2011-12-22 | 2015-11-18 | 奇景光电股份有限公司 | 晶片对晶片接合结构 |
US10636767B2 (en) * | 2016-02-29 | 2020-04-28 | Invensas Corporation | Correction die for wafer/die stack |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003023138A (ja) * | 2001-07-10 | 2003-01-24 | Toshiba Corp | メモリチップ及びこれを用いたcocデバイス、並びに、これらの製造方法 |
JP2005026346A (ja) * | 2003-06-30 | 2005-01-27 | Nikon Corp | 半導体チップの積層方法 |
WO2005122706A2 (en) * | 2004-05-31 | 2005-12-29 | Joon-Mo Kang | Method of aligning semiconductor device and semiconductor structure thereof |
US20060234473A1 (en) * | 2005-04-18 | 2006-10-19 | Lawrence Wong | Thin passivation layer on 3D devices |
WO2007018850A2 (en) * | 2005-07-29 | 2007-02-15 | Freescale Semiconductor | Fabrication of three dimensional integrated circuit employing multiple die panels |
JP2007081296A (ja) * | 2005-09-16 | 2007-03-29 | Fujitsu Ltd | 半導体部品製造システム、制御装置、およびコンピュータプログラム |
US20080157405A1 (en) * | 2007-01-03 | 2008-07-03 | International Business Machines Corporation | Chip stack with precision alignment, high yield assembly and thermal conductivity |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6133582A (en) | 1998-05-14 | 2000-10-17 | Lightspeed Semiconductor Corporation | Methods and apparatuses for binning partially completed integrated circuits based upon test results |
KR100713579B1 (ko) * | 2004-05-31 | 2007-05-02 | 강준모 | 반도체소자 얼라인 방법 및 그에 의해 형성된 반도체 구조물 |
JP4377300B2 (ja) * | 2004-06-22 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体ウエハおよび半導体装置の製造方法 |
US20060249859A1 (en) | 2005-05-05 | 2006-11-09 | Eiles Travis M | Metrology system and method for stacked wafer alignment |
US7492179B2 (en) | 2006-04-10 | 2009-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Systems and methods for reducing testing times on integrated circuit dies |
-
2008
- 2008-09-24 US US12/236,967 patent/US8796073B2/en not_active Expired - Fee Related
-
2009
- 2009-09-18 CN CN2009801366332A patent/CN102160173A/zh active Pending
- 2009-09-18 WO PCT/US2009/057515 patent/WO2010036579A2/en active Application Filing
- 2009-09-18 EP EP09792721A patent/EP2342748A2/en not_active Withdrawn
- 2009-09-18 KR KR1020117009357A patent/KR101252036B1/ko not_active IP Right Cessation
- 2009-09-18 JP JP2011529131A patent/JP2012503884A/ja active Pending
- 2009-09-24 TW TW098132345A patent/TW201029085A/zh unknown
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003023138A (ja) * | 2001-07-10 | 2003-01-24 | Toshiba Corp | メモリチップ及びこれを用いたcocデバイス、並びに、これらの製造方法 |
JP2005026346A (ja) * | 2003-06-30 | 2005-01-27 | Nikon Corp | 半導体チップの積層方法 |
WO2005122706A2 (en) * | 2004-05-31 | 2005-12-29 | Joon-Mo Kang | Method of aligning semiconductor device and semiconductor structure thereof |
US20060234473A1 (en) * | 2005-04-18 | 2006-10-19 | Lawrence Wong | Thin passivation layer on 3D devices |
WO2007018850A2 (en) * | 2005-07-29 | 2007-02-15 | Freescale Semiconductor | Fabrication of three dimensional integrated circuit employing multiple die panels |
JP2007081296A (ja) * | 2005-09-16 | 2007-03-29 | Fujitsu Ltd | 半導体部品製造システム、制御装置、およびコンピュータプログラム |
US20080157405A1 (en) * | 2007-01-03 | 2008-07-03 | International Business Machines Corporation | Chip stack with precision alignment, high yield assembly and thermal conductivity |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016139914A1 (en) | 2015-03-05 | 2016-09-09 | Sony Corporation | Semiconductor device and manufacturing method, and electronic appliance |
KR20170124526A (ko) | 2015-03-05 | 2017-11-10 | 소니 주식회사 | 반도체 장치 및 제조 방법 및 전자 기기 |
KR20230054494A (ko) | 2015-03-05 | 2023-04-24 | 소니그룹주식회사 | 반도체 장치 및 제조 방법 및 전자 기기 |
Also Published As
Publication number | Publication date |
---|---|
US20100075460A1 (en) | 2010-03-25 |
KR101252036B1 (ko) | 2013-04-10 |
US8796073B2 (en) | 2014-08-05 |
WO2010036579A2 (en) | 2010-04-01 |
EP2342748A2 (en) | 2011-07-13 |
WO2010036579A3 (en) | 2010-05-20 |
TW201029085A (en) | 2010-08-01 |
KR20110057268A (ko) | 2011-05-31 |
CN102160173A (zh) | 2011-08-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11458717B2 (en) | Four D device process and structure | |
US8557680B2 (en) | Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers | |
TWI397132B (zh) | 使用多晶粒面板之三維積體電路之製造 | |
JP2938370B2 (ja) | 電子モジュールの製造方法 | |
US11728266B2 (en) | Die stitching and harvesting of arrayed structures | |
JP2012503884A (ja) | 3次元ic積層のための、ウェハとダイとの低コストのアライメント及びボンディング | |
US9893018B2 (en) | Alignment mark for semiconductor device | |
US20150028482A1 (en) | Device layout for reducing through-silicon-via stress | |
KR20120098032A (ko) | 반도체 장치 및 이의 제조방법 | |
US20120233510A1 (en) | High memory density, high input/output bandwidth logic-memory structure and architecture | |
CN111696968B (zh) | 半导体结构的制造方法 | |
US20240379578A1 (en) | Semiconductor structure, dicing method thereof, and memory | |
US20120225538A1 (en) | Methods of disposing alignment keys and methods of fabricating semiconductor chips using the same | |
US20240203848A1 (en) | Semiconductor structures and method for manufacturing a semiconductor structure | |
JP5423862B2 (ja) | 積層半導体素子製造方法および積層半導体素子製造装置 | |
JP2009272388A (ja) | 積層半導体素子製造方法および積層半導体素子製造装置 | |
KR101544319B1 (ko) | 3차원 반도체의 제조방법 | |
JP2000228488A (ja) | チップオンチップの半導体チップ、半導体装置および実装方法 | |
JP5720761B2 (ja) | 積層半導体素子製造方法および積層半導体素子製造装置 | |
CN118213353A (zh) | 半导体结构与制造半导体结构的方法 | |
JP2016115690A (ja) | 積層半導体装置の製造方法 | |
JP2014239143A (ja) | 積層チップ及びその形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120723 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120731 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20121029 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20121105 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130104 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130111 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130130 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131029 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140128 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140204 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140624 |