JP2011159925A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that prevents a short circuit between wires. <P>SOLUTION: The method of manufacturing a semiconductor device includes the steps of: forming a first insulation film 20 on a semiconductor substrate 10; polishing the upper surface of the first insulation film; forming connection holes 30 on the polished first insulation film; forming a first conductive layer 32 on the inner surfaces of the connection holes and the first insulation film; forming a second conductive layer 34 on the first conductive layer in the connection holes; polishing the first conductive layer on the first insulation film to expose the upper surface of the first insulation film; etching the first conductive layer in upper parts of the inner parts of the connection holes by using an etchant in which the etching rate of the first conductive layer is larger than that of the second conductive layer; and forming a wiring layer 50 on the insulation film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, for example, a method for manufacturing a semiconductor device in which a conductive layer is formed in an insulating film.

  In the manufacturing process of a semiconductor device, the insulating film may be polished in order to planarize the upper surface of the insulating film. The insulating film is provided with a connection hole in which a conductive layer is embedded. A wiring layer is formed on the insulating film, and the wiring layer is connected to the connection hole. Thereby, the wiring layer and the wiring under the insulating film or the transistor are electrically connected.

  It is known to etch a TiN film using sulfuric acid (for example, Patent Document 1).

JP 2003-234307 A

  When polishing the upper surface of the insulating film, a scratch may be formed on the upper surface of the insulating film. When the conductive layer is formed in the connection hole in the insulating film, the conductive layer may remain in the scratch. Thereby, there is a problem that the wiring layer on the insulating film is electrically short-circuited through the conductive layer in the scratch.

  An object of the manufacturing method of the semiconductor device is to suppress an electrical short circuit due to a scratch formed on the surface of an insulating film.

  For example, a step of forming a first insulating film on a semiconductor substrate, a step of polishing an upper surface of the first insulating film, a step of forming a connection hole in the polished first insulating film, Forming a first conductive layer on an inner surface and the first insulating film; forming a second conductive layer on the first conductive layer in the connection hole; and Polishing the first conductive layer to expose the upper surface of the first insulating film; and using an etchant having an etching rate of the first conductive layer larger than the etching rate of the second conductive layer; A method of manufacturing a semiconductor device is used, which includes a step of etching the first conductive layer and a step of forming a wiring layer on the insulating film.

  According to the method for manufacturing a semiconductor device, even when a scratch is formed on the surface of the insulating film, an electrical short circuit due to the scratch can be suppressed.

1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a comparative example. FIG. 2 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the comparative example. FIG. 3 is a plan view of the wiring layer, the connection hole, and the scratch. 4A and 4B are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 5A to 5C are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 6A to 6C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 7A to 7C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 8A to 8C are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 9A to 9C are cross-sectional views (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment.

  Embodiments will be described below with reference to the drawings.

  First, a comparative example will be described. 1A to 2 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a comparative example. Referring to FIG. 1A, for example, a first interlayer insulating film 20 (first insulating film) mainly including silicon oxide is formed as an insulating film on, for example, a Si semiconductor substrate 10. The first interlayer insulating film 20 is formed using, for example, a CVD (Chemical Vapor Deposition) method. The first interlayer insulating film 20 may be formed on the semiconductor substrate 10 via another insulating film or the like. In order to planarize the upper surface of the first interlayer insulating film 20, the upper surface of the first interlayer insulating film 20 is polished using, for example, a CMP (Chemical Mechanical Polish) method. At this time, scratch 80 (scratches) may enter the upper surface of the first interlayer insulating film 20. The scratch 80 has various shapes and sizes. For example, the scratch 80 has a width of several tens of nanometers and a length of several hundreds of nanometers as viewed from above.

  Referring to FIG. 1B, a connection hole 30 penetrating the first interlayer insulating film 20 is formed. For example, a first intermediate layer 32 is formed as a first conductive layer on the inner surface of the connection hole 30 and the first interlayer insulating film 20. The first intermediate layer 32 mainly contains Ti, for example, and is formed using a CVD method. At this time, the first intermediate layer 32 is also formed in the scratch 80. For example, a connection metal layer 34 is formed as a second conductive layer in the first intermediate layer 32 in the connection hole 30 and on the first intermediate layer 32 on the first interlayer insulating film 20. The connection metal layer 34 is formed so as to fill the connection hole 30 in the first intermediate layer 32. The connection metal layer 34 mainly contains W, for example, and is formed using a CVD method. The first intermediate layer 32 may have a function as an adhesion layer between the connection metal layer 34 and the first interlayer insulating film 20.

  Referring to FIG. 1C, the connection metal layer 34 and the first intermediate layer 32 on the first interlayer insulating film 20 are polished by CMP to expose the upper surface of the first interlayer insulating film 20. The first intermediate layer 32 a remains in the scratch 80.

  Referring to FIG. 2, a second interlayer insulating film 40 (second insulating film) mainly including, for example, silicon oxide is formed on the first interlayer insulating film 20. A wiring trench penetrating the second interlayer insulating film 40 is formed. A wiring layer 50 is formed in the through hole. Thereby, the wiring layer 50 to which the connection metal layer 34 in the connection hole 30 is connected is formed on the first interlayer insulating film 20.

  FIG. 3 is a plan view of the wiring layer 50, the connection hole 30, and the scratch 80. As shown in FIG. 3, when the scratch 80 is formed on the first interlayer insulating film 20 and the first intermediate layer 32 a remains in the scratch 80, the wiring layer 50 is formed on the first interlayer insulating film 20. The wiring layer 50 and the first intermediate layer 32a are electrically short-circuited. A first embodiment that solves such a problem will be described below.

  4A and 4B are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. As shown in FIG. 4A, after the comparative example of FIG. 1C, the first intermediate layer 32 is etched. At this time, an etchant having a higher etching rate of the first intermediate layer 32 than the connection metal layer 34 and the first interlayer insulating film 20 is used. Thereby, the first intermediate layer 32 in the upper part of the connection hole 30 is etched. As a result, a cavity 36 is formed above the connection hole 30. When the scratch 80 is formed, at least the upper first intermediate layer 32a in the scratch 80 is etched. FIG. 4A shows a case where the first intermediate layer 32 b remains in the lower part in the scratch 80.

  Referring to FIG. 4B, a second interlayer insulating film 40 and a wiring layer 50 are formed on the first interlayer insulating film 20. According to the first embodiment, in FIG. 4A, at least the upper first intermediate layer 32a in the scratch 80 is removed. Therefore, an electrical short between the wiring layers 50 via the first intermediate layer 32b in the scratch 80 can be suppressed. 4A, since the etching rate of the connection metal layer 34 is lower than the etching rate of the first intermediate layer 32a, the retreat amount of the upper surface of the connection metal layer 34 is larger than the retraction amount of the upper surface of the first intermediate layer 32a. Is also small. Therefore, in FIG. 4B, even when the step coverage when forming the wiring layer 50 is poor, connection failure between the connection metal layer 34 and the wiring layer 50 and formation failure of the diffusion prevention film are suppressed. be able to.

  When the first intermediate layer 32 is formed using the CVD method as shown in FIG. 1B, the first intermediate layer 32 is easily formed in the scratch 80 because the CVD method has good coverage characteristics. In order to suppress leakage between the wiring layers 50, it is preferable to remove at least the upper first intermediate layer 32b in the scratch 80 as shown in FIG.

  The second embodiment is a specific example of the first embodiment. FIG. 5A to FIG. 9C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. Referring to FIG. 5A, a transistor 70 is formed on the semiconductor substrate 10. In the transistor 70, an element isolation insulating film 11 formed using an STI (Shallow Trench Isolation) method is formed in a P-type well of the Si semiconductor substrate 10. A source region 12 a and a drain region 12 b which are doped N-type are formed between the element isolation insulating films 11. A metal silicide layer 16 such as Co silicide is formed on the surfaces of the source region 12a and the drain region 12b. A gate oxide film 18 and a gate electrode 13 are formed on the channel between the source region 12a and the drain region 12b. The gate electrode 13 includes, for example, polysilicon. On the gate electrode 13, a metal silicide layer 17 such as Co silicide is formed. Side walls 14 of an insulating film such as silicon oxide are formed on both sides of the gate electrode 13.

Referring to FIG. 5B, a silicon nitride film, for example, is formed as the etching stopper film 22 on the semiconductor substrate 10 and the transistor 70. The etching stopper film 22 is formed by CVD using, for example, N ₂ , NH ₃ and Si ₂ H as source gases. The film thickness of the etching stopper film 22 is, for example, 80 nm. A first interlayer insulating film 20 mainly containing silicon oxide is formed on the etching stopper film 22. The first interlayer insulating film 20 is formed using a CVD method. As film forming conditions, for example, the flow rates of the source gases SiH ₄ , O ₂ , H ₂ and PH ₃ are set to 108, 235, 100 and 30 sccm, respectively. The pressure and growth temperature are 0.15 MPa and 490 ° C., respectively. The grown film thickness is, for example, 720 nm. Irregularities resulting from the transistor 70 and the like are formed on the upper surface of the semiconductor substrate 10. For example, the height of the convex portion by the gate electrode 13 is about 100 nm. Therefore, irregularities are also formed on the upper surface of the first interlayer insulating film 20.

  Referring to FIG. 5C, in order to planarize the upper surface of the first interlayer insulating film 20, the first interlayer insulating film 20 is polished using a CMP method. For polishing, for example, an abrasive in which silica-based slurry and pure water are mixed at a volume ratio of 1: 1 is used. The number of rotations is, for example, 50-60 rpm, and the pressure is 3-9 psi. The thickness of the first interlayer insulating film 20 after polishing is 400 to 500 nm, for example, together with the etching stopper film 22. During this polishing, a scratch 80 may occur on the upper surface of the first interlayer insulating film 20. Similar to the first embodiment, the scratch 80 has a width of, for example, several tens of nm and a length of several hundred nm.

Referring to FIG. 6A, a photoresist 60 is formed on the first interlayer insulating film 20. Openings 61 are formed in the photoresist 60. Referring to FIG. 6B, the first interlayer insulating film 20 is etched using the photoresist 60 as a mask. As the etchant gas, for example, a fluorine-based gas such as CF ₄ or C ₄ F ₆ is used. A gas such as O ₂ may be mixed. In this etching, the etching rate of the etching stopper film 22 is smaller than the etching rate of the first interlayer insulating film 20. For the etching of the etching stopper film 22, an etchant gas such as CH ₃ F and O ₂ is used. As a result, a connection hole 30 penetrating the first interlayer insulating film 20 and the etching stopper film 22 is formed. The connection hole 30 is formed on the metal silicide layer 16 on the source region 12 a or the drain region 12 b and the metal silicide layer 17 on the gate electrode 13. By using the etching stopper film 22, it is possible to suppress the metal silicide layer 17 from being over-etched. The photoresist 60 is removed using an ashing method. The diameter of the connection hole 30 is, for example, about 100 nm.

6C, the first intermediate layer 32 is formed on the inner surface of the connection hole 30 and the upper surface of the first interlayer insulating film 20 by using, for example, a CVD method. The first intermediate layer 32 is, for example, a laminated film of a Ti film having a thickness of 10 to 20 nm, or a Ti film having a thickness of 5 to 15 nm and a TiN film having a thickness of 5 to 15 nm from below. For forming the Ti film, for example, TiCl ₄ is used as a source gas. For forming the TiN film, for example, TiCl ₄ and NH ₄ or N ₂ are used as source gases. Since the film formation by the CVD method has good coverage, the first intermediate layer 32 can be formed also on the inner surface of the connection hole 30 having a large aspect ratio. Further, when the scratch 80 exists, the first intermediate layer 32 a is also formed on the inner surface of the scratch 80.

With reference to FIG. 7A, a connection metal layer 34 is formed on the inner surface of the first intermediate layer 32 in the connection hole 30 and on the first intermediate layer 32 on the first interlayer insulating film 20. The connection metal layer 34 mainly includes, for example, W, and is formed by, for example, a CVD method using WF ₆ gas as a source gas. At this time, depending on the width of the scratch 80, the connection metal layer 34 may also be formed in the scratch 80.

  With reference to FIG. 7B, in order to remove the first intermediate layer 32 and the connection metal layer 34 on the first interlayer insulating film 20, the connection metal layer 34 and the first intermediate layer 32 are polished by a CMP method. For polishing, for example, an abrasive in which silica-based slurry and pure water are mixed at a ratio of 1: 3 is used. For example, the rotation speed is about 100 rpm and the pressure is 3.3 to 5 psi. As polishing post-treatment, ammonia water treatment is performed at room temperature. Then, it brushes with ammonia water. By these processes, dust is removed. Further, dilute hydrofluoric acid treatment is performed. By this treatment, metal dust and slurry used for polishing are removed.

  Referring to FIG. 7C, the first intermediate layer 32 is selectively etched with respect to the connection metal layer 34 and the first interlayer insulating film 20. For example, etching is performed for 10 minutes using dilute sulfuric acid at 50 ° C. to 80 ° C., here 70 ° C. Thereby, Ti is etched. The connection metal layer 34 and the first interlayer insulating film 20 have a smaller etching amount than the Ti film. Therefore, a cavity 36 in which the first intermediate layer 32 is etched is formed in the upper part of the connection hole 30. Further, the first intermediate layer 32a of the scratch 80 is removed. Although all of the first intermediate layer 32a in the scratch 80 may be removed, a part of the first intermediate layer 36b may remain in the lower portion as shown in FIG. 7C.

  When the first intermediate layer 32 mainly contains Ti, Ti is easily dissolved in a general acid. However, when nitric acid, hot concentrated sulfuric acid and hot concentrated perchloric acid are used, Ti forms a passive state, and the etching rate of Ti is reduced. On the other hand, when the connection metal layer 34 mainly contains W, W is a hardly soluble substance, and the etching rate by hydrochloric acid, nitric acid, dilute sulfuric acid, perchloric acid and the like is lower than that of the Ti film at room temperature. When the first interlayer insulating film 20 mainly contains silicon oxide, the silicon oxide is dissolved in a hydrofluoric acid chemical solution. From the above, in order to selectively etch Ti with respect to W and silicon oxide, it is preferable to use sulfuric acid, hydrochloric acid and dilute perchloric acid as an etchant. Further, hydrogen peroxide may be added to sulfuric acid, hydrochloric acid and dilute perchloric acid. For example, an etchant having a volume mixing ratio of sulfuric acid and hydrogen peroxide of about 4: 1 can be used.

When the first intermediate layer 32 mainly containing Ti is etched using a dry etching method, a chlorine-based gas can be used. For example, conditions where the flow ratios of Cl ₂ , BCl ₃ and CHF ₃ and Ar are 100, 380, 310 and 80 sccm, respectively, and the pressure is 6 mTorr can be used. As described above, if the etching rate of the first intermediate layer 32 is larger than that of the connection metal layer 34 and the first interlayer insulating film 20, a dry etching method may be used.

  The etching amount of the first intermediate layer 32 is preferably such that the first intermediate layer 32 on the side surface of the connection hole 30 is not completely removed (for example, 300 nm or less). Further, it is preferable that the upper portion of the first interlayer insulating film 20 be larger than the amount to be removed (for example, 40 nm or more) when forming the wiring trench 56 in FIG.

  In FIG. 7B, the width of the scratch 80 is relatively large, and the connection metal layer 34 may remain in the scratch 80 in some cases. Even in this case, in FIG. 7C, the connection metal layer 34 in the scratch 80 can be removed by lift-off by etching the first intermediate layer 32b.

Referring to FIG. 8A, an etching stopper film 42, a second interlayer insulating film 40, and a hard mask film 44 are formed on the first interlayer insulating film 20 by using the CVD method. The etching stopper film 42 mainly includes SiC, for example, and has a film thickness of 30 nm, for example. The second interlayer insulating film 40 mainly includes, for example, SiOC and has a film thickness of, for example, 130 nm. The hard mask film 44 mainly includes, for example, SiO _{2 and} has a film thickness of, for example, 100 nm. In this embodiment, the etching stopper film 42 and the hard mask film 44 are not essential.

Referring to FIG. 8B, a photoresist 62 is formed on the hard mask film 44. An opening 63 is formed in the photoresist 62. Referring to FIG. 8C, the hard mask film 44 is etched using the photoresist 62 as a mask. The photoresist 62 is removed using an ashing method. Using the hard mask film 44 as a mask, the second interlayer insulating film 40 is etched. In this etching, the etching stopper film 42 is not etched. For etching the hard mask film 44, the second interlayer insulating film 40, and the etching stopper film 42, for example, an etching gas appropriately selected from CF ₄ , C ₄ F ₆ , CO, and O ₂ can be used. As a result, a wiring groove 56 that penetrates the hard mask film 44, the second interlayer insulating film 40, and the etching stopper film 42 and exposes the first conductive layer 34 is formed. The width of the wiring groove 56 is, for example, 120 nm.

  Referring to FIG. 9A, a second intermediate layer 52 is formed as a third conductive layer on the inner surface of the wiring groove 56 and the upper surface of the hard mask film 44 by using, for example, a sputtering method. For example, the second intermediate layer 52 mainly contains Ta. A film mainly containing Cu may be formed on the second intermediate layer 52 as a plating seed layer by using, for example, a sputtering method. Since the sputtered film has a poorer coverage than the CVD film, the second intermediate layer 52 is hardly formed in the scratch 80.

  Referring to FIG. 9B, a wiring metal layer 54 is formed on the inner surface of the second intermediate layer 52 in the wiring groove 56 and the second intermediate layer 52 on the second interlayer insulating film 40 by using a plating method. The wiring metal layer 54 is, for example, a copper layer mainly containing Cu. Referring to FIG. 9C, the wiring metal layer 54 and the second intermediate layer 52 on the second interlayer insulating film 40 are polished using the CMP method. Thereby, the wiring layer 50 connected to the connection metal layer 34 is formed in the wiring groove 56. The wiring layer 50 is formed from the second intermediate layer 52 and the wiring metal layer 54. The second intermediate layer 52 may have a function as a barrier layer (diffusion prevention film) for suppressing, for example, a material (for example, Cu) in the wiring metal layer 54 from diffusing into the second interlayer insulating film 40. . In addition, a function as an adhesion layer between the wiring metal layer 54 and the second interlayer insulating film 40 may be provided.

  According to the second embodiment, as shown in FIG. 6C, the first intermediate layer 32 is easily formed in the scratch 80 because the first intermediate layer 32 is formed using the CVD method. On the other hand, as shown in FIG. 9A, the second intermediate layer 52 is formed by sputtering. Since the sputtering method has poor coverage characteristics, for example, in FIG. 7C, even if the first intermediate layer 32b remains in the back of the scratch 80, the second intermediate layer is in contact with the first intermediate layer 32b. Formation of the layer 52 can be suppressed. Therefore, a short circuit between the wiring layers 50 can be further suppressed.

  In this embodiment, the etchant having a lower etching rate of the connection metal layer 34 than the etching rate of the first intermediate layer 32 is used because the upper surface of the connection metal layer 34 formed in the connection hole 30 is etched and receded. This is to suppress the amount to be done. When the upper surface of the connection metal layer 34 is etched back, the second intermediate layer 52 is sufficiently formed in the connection hole 30 when the second intermediate layer 52 uses a deposition method having poor coverage characteristics such as sputtering. It may not be done. When the second intermediate layer 52 is a diffusion prevention film for the wiring metal layer 54, the metal atoms of the wiring metal layer 54 diffuse into the interlayer insulating film 20 unless the second intermediate layer 52 is sufficiently formed in the connection hole 30. There are things to do.

  The connection hole 30 formed in the interlayer insulating film 20 formed on the transistor 70 is small and the aspect ratio is small. On the other hand, the wiring groove 56 for forming the wiring layer 50 is linear and has a large aspect ratio. Therefore, it is preferable to use a CVD method with good coverage characteristics for forming the first intermediate layer 32 in the connection hole 30 for connection to the transistor 70. On the other hand, it is preferable to use a sputtering method for forming the second intermediate layer 52 in the wiring groove 56.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 1st interlayer insulation film 30 Connection hole 32 1st intermediate | middle layer 34 Connection metal layer 40 2nd interlayer insulation film 50 Wiring layer 52 2nd intermediate | middle layer 54 Wiring metal layer

Claims (7)

Forming a first insulating film on the semiconductor substrate;
Polishing an upper surface of the first insulating film;
Forming a connection hole in the polished first insulating film;
Forming the first conductive layer on the inner surface of the connection hole and the first insulating film;
Forming a second conductive layer on the first conductive layer in the connection hole;
Polishing the first conductive layer on the first insulating film to expose an upper surface of the first insulating film;
Etching the first conductive layer in the upper part of the connection hole using an etchant having an etching rate of the first conductive layer larger than that of the second conductive layer;
Forming a wiring layer on the insulating film;
A method of manufacturing a semiconductor device including:   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of etching the first conductive layer, an etching rate of the first conductive layer by the etchant is higher than an etching rate of the first insulating film by the etchant. After the step of etching the first conductive layer, forming a second insulating film on the first insulating film;
Forming a wiring groove exposing the first conductive layer in the second insulating film;
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a third conductive layer in the wiring trench using a sputtering method.   The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is formed using a CVD method.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive layer includes Ti, the second conductive layer includes W, and the insulating film includes silicon oxide.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the etchant is a solution containing sulfuric acid, hydrochloric acid, and dilute perchloric acid.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a copper layer on the third conductive layer, wherein the third conductive layer is a copper diffusion prevention film.

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