JP2010263274A - Level shift circuit, display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit which suppresses a through current and has a high flexibility in transient control. <P>SOLUTION: First and second circuits 11 and 12 including first transistors (111 and 121), second transistors (112 and 122), and third transistors (113 and 123) connected between these transistors are connected in parallel between a first power supply vdd and a second power supply vss. A gate electrode of the third transistor 113 of the first circuit 11 is connected to an output node of the second circuit 12, and a gate electrode of the third transistor 123 of the second circuit 12 is connected to an output node of the first circuit 11. In this level shift circuit, the transient of a pulse signal out having a second amplitude is controlled by a voltage value of an input node Nin1 of the first circuit 11 when a pulse signal in1 having a first amplitude, which is input to an input node Nin2 of the second circuit 12, is level-shifted to the pulse signal out having the second amplitude. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a level shift circuit, a display device, and an electronic apparatus.

  The level shift circuit is also called a level shifter or a level conversion circuit. As this level shift circuit, a current mirror type level shift circuit is widely known (for example, see Patent Document 1).

  FIG. 22 shows an example of the configuration of a current mirror type level shift circuit according to a conventional example. The current mirror type level shift circuit according to this example includes bias shift units 201 and 202 and a level conversion unit 203, and the level conversion unit 53 has a current mirror circuit configuration including transistors Tr1, Tr2, and Tr3.

  In this current mirror type level shift circuit, the gate-source voltage Vgs of the transistors Tr1 and Tr2 can be controlled by controlling the potential of the node A by the input voltage in. Therefore, the currents I1 and I2 flowing through the transistors Tr1 and Tr2 are Can be controlled. Here, assuming that the transistors Tr1 and Tr2 have the same size and no difference in transistor characteristics, I2 = I1, and the value of the output voltage out is determined by the value of the current I2.

  Further, since the resistance Rtr3 of the transistor Tr3 also changes depending on the potential of the node A corresponding to the input voltage in, the gain can be increased compared to a simple current mirror type level shift circuit. FIG. 23 shows waveforms at various parts in FIG.

In addition to the current mirror type level shift circuit, a two-phase input type level shift circuit is known as the level shift circuit (see, for example, Patent Document 2). FIG. 24 shows an example of a configuration of a two-phase input type level shift circuit according to a conventional example. FIG. 25 shows the input / output waveforms of FIG.

JP 2003-347926 A JP 2002-353804 A

  The current mirror type level shift circuit has a through path from the positive power supply vdd to the negative power supply vss at both high level output and low level output, and the through current constantly flows. Contributes to the increase. In addition, since the number of transistor elements is large, there are problems such as a large layout area and a large output response variation due to variations in transistor characteristics.

  In contrast to the current mirror type level shift circuit, the two-phase input type level shift circuit can suppress a through current because there is no through path from the positive power supply vdd to the negative power supply vss. However, since the two-phase input type level shift circuit has a circuit configuration that requires the inverted input voltage xin in addition to the input voltage in, there is a disadvantage that the number of input pulses increases. In the case of a two-phase input type level shift circuit, since the transient (transient response) of the output voltage out is determined only by the circuit constant, the degree of freedom in controlling the transient is small.

Accordingly, an object of the present invention is to provide a level shift circuit capable of suppressing a through current and having a high degree of freedom of transient control, a display device using the level shift circuit, and an electronic apparatus having the display device. And

In order to achieve the above object, the present invention provides:
First and second transistors having first and second transistors of opposite conductivity type, whose gate electrodes are connected in common and serving as input nodes, and a third transistor connected between the first and second transistors. A circuit unit is connected in parallel between the first power source and the second power source;
The gate electrode of the third transistor of the first circuit portion is at an output node of the second circuit portion, and the gate electrode of the third transistor of the second circuit portion is of the first circuit portion. In the level shift circuit connected to each output node,
When the first amplitude pulse signal input to one input node of the first and second circuit units is level-shifted to a second amplitude pulse signal larger than the first amplitude, The transient of the pulse signal having the second amplitude is controlled by the voltage value of the other input node of the second circuit unit.

By connecting a third transistor controlled by the output of the first or second circuit unit between the first and second transistors, a through path is provided between the first power source and the second power source. Since it is not formed, the through current can be suppressed. The transient of the second amplitude pulse signal is controlled by the voltage value of the other input node with respect to the first amplitude pulse signal input to one input node of the first and second circuit units. The degree of freedom in controlling the transient of the pulse signal having the second amplitude can be increased by setting the voltage value.

According to the present invention, it is possible to provide a level shift circuit that can suppress a through current and has a high degree of freedom in controlling transients.

FIG. 3 is a circuit diagram illustrating an example of a configuration of a level shift circuit according to the first embodiment. FIG. 6 is a waveform diagram for explaining the operation of the level shift circuit according to the first embodiment. FIG. 6 is a circuit diagram illustrating an example of a configuration of a level shift circuit according to a second embodiment. FIG. 10 is a waveform diagram for explaining the operation of the level shift circuit according to the second embodiment. FIG. 10 is a waveform diagram for explaining the operation of the level shift circuit according to the third embodiment. FIG. 10 is a waveform diagram for explaining the operation of the level shift circuit according to the fourth embodiment. 1 is a system configuration diagram showing an outline of a configuration of an organic EL display device using a level shift circuit according to the present invention. It is a circuit diagram which shows the circuit structure of the pixel of an organic electroluminescence display. It is a timing waveform diagram with which it uses for description of circuit operation | movement of an organic electroluminescence display. It is explanatory drawing (the 1) of the circuit operation | movement of an organic electroluminescence display. It is explanatory drawing (the 2) of the circuit operation | movement of an organic electroluminescence display. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the threshold voltage Vth of a drive transistor. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the mobility (mu) of a drive transistor. FIG. 10 is a characteristic diagram for explaining the relationship between the signal voltage Vsig of the video signal and the drain-source current Ids of the drive transistor depending on whether threshold correction and mobility correction are performed. It is a wave form diagram which shows the relationship between the falling waveform of the write pulse WS, and the optimal correction time t of mobility correction. It is a block diagram which shows an example of a structure of a writing scanning circuit. It is a perspective view which shows the external appearance of the television set to which this invention is applied. It is a perspective view which shows the external appearance of the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view illustrating an appearance of a notebook personal computer to which the present invention is applied. It is a perspective view which shows the external appearance of the video camera to which this invention is applied. BRIEF DESCRIPTION OF THE DRAWINGS It is an external view which shows the mobile telephone to which this invention is applied, (A) is the front view in the open state, (B) is the side view, (C) is the front view in the closed state, (D) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. It is a circuit diagram which shows an example of a structure of the current mirror type level shift circuit which concerns on a prior art example. It is a wave form diagram of each part of a current mirror type level shift circuit. It is a circuit diagram which shows an example of a structure of the two-phase input type level shift circuit which concerns on a prior art example. It is an input / output waveform diagram of a two-phase input type level shift circuit.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.

1. Level shift circuit 1-1. Example 1 (Example 1 of control based on DC voltage value)
1-2. Example 2 (Example 2 of control by voltage value of DC voltage)
1-3. Example 3 (Example 1 of control based on the amplitude of a pulse signal)
1-4. Example 3 (Example 2 of control based on the amplitude of a pulse signal)
2. Display device (example of organic EL display device)
2-1. System configuration 2-2. 2. Circuit operation Application example (electronic equipment)

<1. Level shift circuit>
The level shift circuit according to the present embodiment is a two-phase input type level shift circuit, and includes first and second circuit sections having the same circuit configuration. The first and second circuit units are connected in parallel between the first power source and the second power source. Each of the first and second circuit portions includes first and second transistors of opposite conductivity type, whose gate electrodes are commonly connected to serve as an input node, and first and second transistors connected between the first and second transistors. 3 transistors.

  In the first circuit portion, the gate electrode of the third transistor is connected to the output node of the second circuit portion. In the second circuit portion, the gate electrode of the third transistor is connected to the output node of the first circuit portion. An input signal is given (inputted) to each input node of the first and second circuit sections.

  In this embodiment, when the level of the pulse signal input to one input node of the first and second circuit units is level-shifted, the voltage value of the other input node of the first and second circuit units depends on the voltage value of the other input node. It is characterized by controlling the transient (transient response) of the output pulse signal. The level shift referred to here is a level shift (level shift) from a first amplitude pulse signal input to one input node of the first and second circuit units to a second amplitude pulse signal larger than the first amplitude. Conversion).

  Specific examples of the two-phase input type level shift circuit according to this embodiment will be described below.

[1-1. Example 1]
FIG. 1 is a circuit diagram illustrating an example of the configuration of the level shift circuit according to the first embodiment. As shown in FIG. 1, the level shift circuit 10A according to the first embodiment is connected in parallel between a first power supply (for example, a positive power supply vdd) and a second power supply (for example, a negative power supply vss). The first and second circuit portions 11 and 12 are provided.

  The first circuit unit 11 includes first and second transistors 111 and 112 having mutually opposite conductivity types whose gate electrodes are commonly connected to become an input node Nin1, and between the first and second transistors 111 and 112. And a third transistor 113 connected thereto. Here, as an example, an N-channel transistor is used as the first transistor 111, and a P-channel transistor is used as the second and third transistors 112 and 113.

  The second circuit unit 12 also has the same circuit configuration as the first circuit unit 11. That is, the second circuit unit 12 is connected between the first and second transistors 121 and 122 that have the gate electrodes connected in common and become the input node Nin2, and the first and second transistors 121 and 122. And a third transistor 123. Again, an N-channel transistor is used as the first transistor 121, and a P-channel transistor is used as the second and third transistors 122 and 123.

  The first input signal in1 is input to an input node Nin1 that is a common gate connection node of the first and second transistors 111 and 112 of the first circuit unit 11. The drain electrodes of the first transistor 111 and the third transistor 113 are connected in common, and this common drain connection node is the output node Nout1 of the first circuit unit 11.

  The second input signal in2 is input to an input node Nin2 that is a common gate connection node of the first and second transistors 121 and 122 of the second circuit unit 12. The drain electrodes of the first transistor 121 and the third transistor 123 are connected in common, and this common drain connection node is the output node Nout2 of the second circuit unit 12.

  The gate electrode of the third transistor 113 on the first circuit unit 11 side is connected to the output node Nout2 of the second circuit unit 12. The gate electrode of the third transistor 123 on the second circuit unit 12 side is connected to the output node Nout1 of the first circuit unit 11. The output node Nout2 of the second circuit unit 12 is an output node of the level shift circuit 10A. The output signal out of the level shift circuit 10A is derived from the output node Nout2.

  In the level shift circuit 10A according to the first embodiment having the above configuration, a DC voltage (hereinafter referred to as “DC voltage in1”) is input as the first input signal in1. The DC voltage in1 can be arbitrarily set.

  Here, as an example, the voltage value of the direct-current voltage in1 is set to a voltage value approximately equal to the amplitude of the second input signal in2, for example, 3V, and a voltage value larger than the amplitude, for example, 5V. . The voltage values of 3V and 5V are voltage values between the positive power supply voltage vdd and the negative power supply voltage vss.

  On the other hand, the second input signal in2 is described as a low-active pulse signal (hereinafter referred to as “input pulse signal in2”) in which the second circuit unit 12 is in an active state at a low level (vss level, for example, 0 V). ) Is entered. The input pulse signal in2 is a pulse signal having an amplitude determined by the power supply voltage of the circuit unit that supplies the pulse signal in2, for example, an amplitude of 0V-3V.

  The level shift circuit 10A converts the pulse signal in2 having an amplitude (first amplitude) of vss-3V into a pulse signal having an amplitude (second amplitude) of vss-vdd, using the low level period of the input pulse signal in2 as a level shift period. Level shift (level conversion). Then, the level shift circuit 10A outputs the level-shifted pulse signal with the amplitude of vss-vdd as the output pulse signal out.

  By the way, in the case of the two-phase input type level shift circuit according to the conventional example, a pulse signal xin2 having a phase opposite to that of the input pulse signal in2 is used as the first input signal in1. That is, the anti-phase pulse signal xin2 is a pulse signal that is at a high level (3 V in this example) during a level shift period in which the input pulse signal in2 is at a low level, and is at a low level during other periods.

  On the other hand, in the case of the level shift circuit 10A according to the first embodiment, a DC voltage is input as the first input signal in1, and output according to the voltage value of the DC voltage in1, that is, the voltage value of the input node Nin1. It is characterized by controlling the transient of the pulse signal out.

  Here, the principle that the transient of the output signal out can be controlled by the voltage value of the DC voltage in1 (the voltage value of the input node Nin1) in the level shift circuit 10A according to the first embodiment will be described with reference to the waveform diagram of FIG. To do. Here, it is assumed that the voltage value of the DC voltage in1 is set to 5 V, for example, and the case where the voltage value is set to 3 V will be described.

  When 5V is applied to the input node Nin1 on the first circuit unit 11 side as the voltage value of the DC voltage in1, the first transistor on the first circuit unit 11 side is compared with the case where 3V is applied. The on-resistance of 111 is lowered. As a result, the on-resistance of the third transistor 123 on the second circuit portion 12 side is lowered. Therefore, when the voltage value of the DC voltage in1 is 5V, the rising transient of the output pulse signal out is earlier than when 3V is input.

  From this, it can be seen that when the level of the input pulse signal in2 is shifted, the rising transient of the output pulse signal out can be controlled by the voltage value of the DC voltage in1 input to the input node Nin1 of the first circuit unit 11. That is, the rising transient of the output pulse signal out is determined according to the voltage value of the input node Nin1 when the input pulse signal in2 transitions from a high level to a low level.

  Incidentally, in the rising waveform of the output pulse signal out in the waveform diagram of FIG. 2, a case where the voltage value of the DC voltage in1 is 5V is indicated by a solid line, and a case where the voltage value of the DC voltage in1 is 3V is indicated by a one-dot chain line.

  As described above, the level shift circuit 10A according to the first embodiment includes the second circuit unit 12 or the first circuit unit 11 between the first transistors 111 and 121 and the second transistors 112 and 122. The third transistors 113 and 123 controlled by the output are connected. Accordingly, since a through path from the positive power supply vdd to the negative power supply vss is not formed, the through current can be suppressed.

  Moreover, the rising transient of the output pulse signal out can be controlled by the voltage value of the DC voltage in1 input as the first input signal in1. Therefore, the degree of freedom in controlling the transient of the output pulse signal out can be increased by setting the voltage value of the DC voltage in1.

[1-2. Example 2]
FIG. 3 is a circuit diagram illustrating an example of the configuration of the level shift circuit according to the second embodiment. As shown in FIG. 3, the level shift circuit 10B according to the second embodiment is connected in parallel between a first power supply (for example, a positive power supply vdd) and a second power supply (for example, a negative power supply vss). The first and second circuit sections 21 and 22 are also provided.

  The first circuit unit 21 includes first and second transistors 211 and 212 of opposite conductivity types whose gate electrodes are commonly connected to become an input node Nin1, and between the first and second transistors 211 and 212. A third transistor 213 connected thereto; Here, as an example, N-channel transistors are used as the first and third transistors 211 and 213, and P-channel transistors are used as the second transistor 212.

  The second circuit unit 22 has the same circuit configuration as the first circuit unit 21. That is, the second circuit unit 22 is connected between the first and second transistors 221 and 222 that have the gate electrode connected in common and become the input node Nin2, and the first and second transistors 221 and 222. A third transistor 223. Again, N-channel transistors are used as the first and third transistors 221 and 223, and P-channel transistors are used as the second transistor 222.

  The first input signal in1 is input to an input node Nin1 that is a common gate connection node of the first and second transistors 211 and 212 of the first circuit unit 21. The drain electrodes of the second transistor 212 and the third transistor 213 are connected in common, and this common drain connection node is the output node Nout1 of the first circuit unit 21.

  The second input signal in2 is input to an input node Nin2 that is a common gate connection node of the first and second transistors 221 and 222 of the second circuit unit 22. The drain electrodes of the second transistor 221 and the third transistor 223 are connected in common, and this drain common connection node becomes the output node Nout2 of the second circuit unit 22.

  The gate electrode of the third transistor 213 on the first circuit portion 21 side is connected to the output node Nout2 of the second circuit portion 22. The gate electrode of the third transistor 223 on the second circuit section 22 side is connected to the output node Nout1 of the first circuit section 21. The output node Nout2 of the second circuit unit 22 is an output node of the level shift circuit 10B. The output signal out of the level shift circuit 10B is derived from the output node Nout2.

  In the level shift circuit 10B according to the second embodiment having the above-described configuration, as in the case of the level shift circuit 10A according to the first embodiment, a DC voltage in1 whose voltage value can be arbitrarily set is used as the first input signal in1. Entered. On the other hand, a low-active pulse signal (input pulse signal in2) having an amplitude of, for example, 0V-3V is input as the second input signal in2.

  The level shift circuit 10B converts the pulse signal in2 having an amplitude (first amplitude) of vsss-3V into a pulse signal having an amplitude (second amplitude) of vss-vdd using the low level period of the input pulse signal in2 as a level shift period. Level shift (level conversion). The level shift circuit 10B then outputs a level-shifted pulse signal with the amplitude of vss-vdd as the output pulse signal out.

  Also in the level shift circuit 10B according to the second embodiment, as in the case of the level shift circuit 10A according to the first embodiment, a DC voltage is input as the first input signal in1, and output according to the voltage value of the DC voltage in1. Controls the transient of the pulse signal out.

  Here, the principle that the transient of the output signal out can be controlled by the voltage value of the DC voltage in1 (voltage value of the input node Nin1) in the level shift circuit 10B according to the second embodiment will be described with reference to the waveform diagram of FIG. To do. Here, it is assumed that the voltage value of the DC voltage in1 is set to 3V, for example, and the case where the voltage value is set to 5V will be described.

  When 3V is applied to the input node Nin1 on the first circuit section 21 side as the voltage value of the DC voltage in1, the second transistor on the first circuit section 21 side is compared with the case where 5V is applied. The on-resistance of 212 is lowered. As a result, the on-resistance of the third transistor 223 on the second circuit portion 22 side is lowered. Therefore, when the voltage value of the DC voltage in1 is 3V, the transition of the falling edge of the output pulse signal out is earlier than when 5V is input.

  From this, it can be seen that the transient of the fall of the output pulse signal out can be controlled by the voltage value of the DC voltage in1 input as the first input signal in1. That is, the transition of the falling edge of the output pulse signal out is determined according to the voltage value of the input node Nin1 when the input pulse signal in2 transitions from the low level to the high level.

  Incidentally, in the falling waveform of the output pulse signal out in the waveform diagram of FIG. 4, a case where the voltage value of the DC voltage in1 is 3V is indicated by a solid line, and a case where the voltage value of the DC voltage in1 is 5V is indicated by a one-dot chain line. .

  As described above, the level shift circuit 10B according to the second embodiment includes the second circuit unit 22 or the first circuit unit 21 between the first transistors 211 and 221 and the second transistors 212 and 222. The third transistors 213 and 223 controlled by the output are connected. Accordingly, since a through path from the positive power supply vdd to the negative power supply vss is not formed, the through current can be suppressed.

  In addition, the transition of the falling edge of the output pulse signal out can be controlled by the voltage value of the DC voltage in1 input as the first input signal in1. Therefore, the degree of freedom in controlling the transient of the falling edge of the output pulse signal out can be increased by setting the voltage value of the DC voltage in1.

  As described above, the level shift circuits 10A and 10B according to the first and second embodiments receive the input pulse signal in2 having the amplitude of vss-3V inputted to the input node Nin2 of the second circuit unit 12 with respect to the vss-vdd. Level shift to an output pulse signal out having an amplitude of. Then, the transient of the output pulse signal out is controlled by the voltage value of the DC voltage in1 input to the input node Nin1 of the first circuit unit 11.

  More specifically, the level shift circuit 10A according to the first embodiment changes the rising transition of the output pulse signal out according to the voltage value of the input node Nin1 when the input pulse signal in2 transitions from a high level to a low level. I try to control it. Further, the level shift circuit 10B according to the second embodiment controls the transition of the falling edge of the output pulse signal out according to the voltage value of the input node Nin1 when the input pulse signal in2 transitions from the low level to the high level. I have to.

  In the level shift circuits 10A and 10B according to the first and second embodiments, the rising transient is controlled by the voltage value of the input node Nin1 depending on the difference in the circuit configuration (see FIGS. 1 and 3). Whether to control transients is decided.

[1-3. Example 3]
In the level shift circuits 10A and 10B according to the first and second embodiments, a DC voltage is input as the first input signal in1, and the transient of the output pulse signal out is controlled by the voltage value of the DC voltage in1. Yes.

  In contrast, in the level shift circuit according to the third embodiment, the input pulse signal in1 input to the input node Nin1 on the first circuit unit 11 side has the same circuit configuration as the level shift circuit 10A according to the first embodiment. A level shift is performed on it. More specifically, the input pulse signal in1 having the amplitude of vss-3V is level-shifted to the output pulse signal out having the amplitude of vss-vdd.

  A pulse signal in2 having a phase opposite to that of the input pulse signal in1 is input to the input node Nin2 on the second circuit unit 12 side, and an output pulse signal is output according to the amplitude of the pulse signal in2, that is, the voltage value of the input node Nin2. Control the transient of out.

  Here, the principle that the transient of the output signal out can be controlled by the amplitude of the pulse signal in2 (the voltage value of the input node Nin2) in the level shift circuit according to the third embodiment will be described with reference to the waveform diagram of FIG. Here, a description will be given assuming that the amplitude relationship (for example, 0V-5V) of the pulse signal in2 (xin1) is set larger than the amplitude (for example, 0V-3V) of the input pulse signal in1.

  During the operation at the transition timing when the output pulse signal out rises, the pulse signal in2 transitions from the high level (5V) to the low level (0V), and the voltage value of the input node Nin2 becomes 0V. It is not different from the transition from 3V to 0V. Therefore, the rising transient of the output pulse signal out is the same as when the pulse signal in2 transitions from 3V to 0V.

  On the other hand, in the operation at the transition timing when the output pulse signal out falls, the pulse signal in2 transitions from the low level (0V) to the high level (5V), and the voltage value of the input node Nin2 becomes 5V. 1, the on-resistance of the first transistor 121 on the second circuit section 12 side is lower than when the pulse signal in2 transitions from 0V to 3V. Accordingly, since the circuit operation at the time of falling of the output pulse signal out becomes faster, the transient of the falling of the output pulse signal out becomes faster.

  Incidentally, in the falling waveform of the output pulse signal out in the waveform diagram of FIG. 5, the case where the voltage value of the input node Nin2 is 5V is indicated by a solid line, and the case where the voltage value of the input node Nin2 is 3V is indicated by a one-dot chain line. .

  As described above, according to the level shift circuit according to the third embodiment, the falling transient of the output pulse signal out can be controlled by the voltage value of the input node Nin2. Therefore, the degree of freedom in controlling the transient of the falling edge of the output pulse signal out can be increased by setting the amplitude of the pulse signal in2. Further, as in the case of the first embodiment, there is an advantage that the through current can be suppressed.

[1-4. Example 4]
The level shift circuit according to the third embodiment performs level shift on the input pulse signal in1 input to the input node Nin1 of the first circuit unit 11, and transients of the output pulse signal out according to the voltage value of the input node Nin2. To control.

  In contrast, in the level shift circuit according to the fourth embodiment, the input pulse signal in2 input to the input node Nin2 on the second circuit unit 12 side has the same circuit configuration as the level shift circuit 10A according to the first embodiment. A level shift is performed on it. More specifically, the input pulse signal in2 having the amplitude of vss-3V is level-shifted to the output pulse signal out having the amplitude of vss-vdd.

  A pulse signal in1 having a phase opposite to that of the input pulse signal in2 is input to the input node Nin1 on the first circuit unit 11 side, and an output pulse signal is output according to the amplitude of the pulse signal in1, that is, the voltage value of the input node Nin1. Control the transient of out.

  Here, the principle that the transient of the output signal out can be controlled by the amplitude of the pulse signal in1 (the voltage value of the input node Nin1) in the level shift circuit according to the fourth embodiment will be described with reference to the waveform diagram of FIG. Here, the description will be made assuming that the amplitude relationship (for example, 0V-5V) of the pulse signal in1 (xin2) is set larger than the amplitude (for example, 0V-3V) of the input pulse signal in2.

  In the operation at the transition timing when the output pulse signal out rises, the pulse signal in1 transitions from the low level (0V) to the high level (5V), and the voltage value of the input node Nin1 becomes 5V. The on-resistance of the first transistor 111 on the first circuit unit 11 side is lower than when the pulse signal in1 transitions from 0V to 3V. Accordingly, since the circuit operation at the time of rising of the output pulse signal out becomes faster, the rising transient of the output pulse signal out becomes faster.

  Incidentally, in the rising waveform of the output pulse signal out in the waveform diagram of FIG. 6, the solid line indicates the case where the voltage value of the input node Nin1 is 5V, and the dashed line indicates the case where the voltage value of the input node Nin1 is 3V.

  On the other hand, during the operation at the transition timing when the output pulse signal out falls, the pulse signal in1 transits from the high level (5V) to the low level (0V), and the voltage value of the input node Nin1 becomes 0V. This is the same as when the signal in1 transitions from 3V to 0V. Therefore, the transient of the falling edge of the output pulse signal out is the same as that when the pulse signal in1 transitions from 3V to 0V.

  As described above, according to the level shift circuit of the fourth embodiment, the transient of the output pulse signal out can be controlled by the voltage value of the input node Nin1. Accordingly, the degree of freedom in controlling the transient of the output pulse signal out can be increased by setting the amplitude of the pulse signal in1. Further, as in the case of the first embodiment, there is an advantage that the through current can be suppressed.

  As described above, in the level shift circuit according to the third and fourth embodiments, the input pulse signal in1 / in2 having the amplitude of vss-3V input to the input node Nin1 / Nin2 is output to the output pulse signal having the amplitude of vss-vdd. Level shift to out. The transient of the output pulse signal out is controlled by the amplitude of the pulse signal in2 / in1 input to the input node Nin2 / Nin1.

  More specifically, the level shift circuit according to the third embodiment controls the transient of the fall of the output pulse signal out by the voltage value of the input node Nin2 when the input pulse signal in1 transitions from a high level to a low level. I am doing so. In the level shift circuit according to the fourth embodiment, the transient of the rise of the output pulse signal out is controlled by the voltage value of the input node Nin1 when the input pulse signal in2 transitions from the low level to the high level.

  The level shift circuits according to the third and fourth embodiments fall and rise depending on whether the pulse signal having a variable amplitude is input to the second circuit unit 12 or the first circuit unit 11. Which transient is to be controlled is determined.

The level shift circuit according to the first to fourth embodiments is suitable for use as a level shift circuit mounted on a display device in various electronic devices, for example, an electronic device using a flat type display device. It is. In the display device, for example, a first amplitude pulse signal input from outside the display panel is level-shifted to a second amplitude pulse signal necessary for driving the display unit, or a first amplitude pulse signal is displayed on the display panel. It is used for purposes such as level shifting to a pulse signal of the second amplitude.

<2. Display device>
Subsequently, an electronic apparatus using the level shift circuit according to the first to fourth embodiments, for example, an active matrix display device will be described. Here, as an example, an organic EL (electroluminescence) display device will be described as an example of a display device using the level shift circuit according to the first to fourth embodiments. An organic EL display device uses, as a light emitting element of a pixel (pixel circuit), an organic EL element that is a current-driven electro-optical element whose emission luminance changes according to a current value flowing through the device.

[2-1. System configuration]
FIG. 7 is a system configuration diagram illustrating an outline of a configuration of an active matrix organic EL display device using the level shift circuit according to the first to fourth embodiments.

  As shown in FIG. 7, the organic EL display device 30 includes a plurality of pixels 40 including organic EL elements, a pixel array unit 50 in which the pixels 40 are two-dimensionally arranged in a matrix, and the periphery of the pixel array unit 50. It has the structure which has the drive part arrange | positioned in this. The drive unit includes, for example, a write scanning circuit 60, a power supply scanning circuit 70, and a signal output circuit 80, and drives each pixel 40 of the pixel array unit 50.

  Here, when the organic EL display device 30 supports color display, one pixel includes a plurality of sub-pixels (sub-pixels), and this sub-pixel corresponds to the pixel 40. More specifically, in a display device for color display, one pixel includes a sub-pixel that emits red light (R), a sub-pixel that emits green light (G), and a sub-pixel that emits blue light (B). It consists of three sub-pixels of a pixel.

  However, one pixel is not limited to the combination of RGB three primary color subpixels, and one pixel may be configured by adding one or more color subpixels to the three primary color subpixels. Is possible. More specifically, for example, at least one sub-pixel that emits white light (W) is added to improve luminance to form one pixel, or at least one that emits complementary color light to expand the color reproduction range. It is also possible to configure one pixel by adding subpixels.

  The pixel array unit 50 includes scanning lines 51-1 to 51-m and power supply lines 52-1 along the row direction (pixel arrangement direction of pixels in the pixel row) with respect to the arrangement of the pixels 40 in m rows and n columns. To 52-m are wired for each pixel row. Furthermore, signal lines 53-1 to 53-n are wired for each pixel column along the column direction (pixel arrangement direction of the pixel column).

  The scanning lines 51-1 to 51-m are connected to the output ends of the corresponding rows of the writing scanning circuit 60, respectively. The power supply lines 52-1 to 52-m are connected to the output ends of the corresponding rows of the power supply scanning circuit 70, respectively. The signal lines 53-1 to 53-n are connected to the output ends of the corresponding columns of the signal output circuit 80, respectively.

  The pixel array unit 50 is usually formed on a transparent insulating substrate such as a glass substrate. As a result, the organic EL display device 30 has a planar (flat) panel structure. The drive circuit for each pixel 40 of the pixel array unit 50 can be formed using an amorphous silicon TFT or a low-temperature polysilicon TFT. When the low-temperature polysilicon TFT is used, the write scanning circuit 60, the power supply scanning circuit 70, and the signal output circuit 80 can also be mounted on the display panel (substrate) 90 that forms the pixel array unit 50.

  The write scanning circuit 60 is configured by a shift register or the like that sequentially shifts (transfers) the start pulse sp in synchronization with the clock pulse ck. The writing scanning circuit 60 sequentially supplies a writing scanning signal WS (WS1 to WSm) to the scanning lines 51-1 to 51-m when writing video signals to the respective pixels 40 of the pixel array unit 50, thereby providing a pixel array. Each pixel 40 of the unit 50 is scanned in order in a row unit (line-sequential scanning).

  The power supply scanning circuit 70 includes a shift register that sequentially shifts the start pulse sp in synchronization with the clock pulse ck. The power supply scanning circuit 70 synchronizes with the line sequential scanning by the write scanning circuit 60 and switches between a first power supply potential Vccp and a second power supply potential Vini lower than the first power supply potential Vccp. ) To the power supply lines 52-1 to 52-m. The power supply potential DS, Vccp / Vini, controls the light emission / non-light emission of the pixel 40 by switching the potential.

  The signal output circuit 80 selectively outputs a signal voltage Vsig of a video signal (hereinafter sometimes simply referred to as “signal voltage”) according to luminance information supplied from a signal supply source (not shown). . The signal voltage Vsig / reference voltage Vofs output from the signal output circuit 80 is written in units of rows to each pixel 40 of the pixel array unit 50 via the signal lines 53-1 to 53-n. That is, the signal output circuit 80 adopts a line-sequential writing drive configuration in which the signal voltage Vsig is written in units of rows (lines).

(Pixel circuit)
FIG. 8 is a circuit diagram showing a specific circuit configuration of the pixel (pixel circuit) 40.

  As illustrated in FIG. 8, the pixel 40 includes an organic EL element 41 and a drive circuit that drives the organic EL element 41. The organic EL element 41 has a cathode electrode connected to a common power supply line 54 that is wired in common to all the pixels 40 (so-called solid wiring).

  The drive circuit that drives the organic EL element 41 has a configuration including a drive transistor 42, a write transistor 43, and a storage capacitor 44. Here, N-channel TFTs are used as the drive transistor 42 and the write transistor 43. However, the combination of conductivity types of the drive transistor 42 and the write transistor 43 is merely an example, and is not limited to these combinations.

  Note that when an N-channel TFT is used as the driving transistor 42 and the writing transistor 43, an amorphous silicon (a-Si) process can be used. By using the a-Si process, it is possible to reduce the cost of the substrate on which the TFT is formed, and thus to reduce the cost of the organic EL display device 30.

  The drive transistor 42 has one electrode (source / drain electrode) connected to the anode electrode of the organic EL element 41 and the other electrode (drain / source electrode) connected to the power supply line 52 (52-1 to 52-m). It is connected.

  The write transistor 43 has one electrode (source / drain electrode) connected to the signal line 53 (53-1 to 53-n) and the other electrode (drain / source electrode) connected to the gate electrode of the drive transistor 42. ing. The gate electrode of the writing transistor 43 is connected to the scanning line 51 (51-1 to 51-m).

  In the drive transistor 42 and the write transistor 43, one electrode refers to a metal wiring electrically connected to the source / drain region, and the other electrode refers to a metal wiring electrically connected to the drain / source region. Say. Further, depending on the potential relationship between one electrode and the other electrode, if one electrode becomes a source electrode, it becomes a drain electrode, and if the other electrode also becomes a drain electrode, it becomes a source electrode.

  The storage capacitor 44 has one electrode connected to the gate electrode of the drive transistor 42 and the other electrode connected to the other electrode of the drive transistor 42 and the anode electrode of the organic EL element 41.

  The drive circuit of the organic EL element 41 is not limited to a circuit configuration including two transistors, the drive transistor 42 and the write transistor 43, and one capacitive element of the storage capacitor 44. For example, a circuit configuration in which one electrode is connected to the anode electrode of the organic EL element 41 and the other electrode is connected to a fixed potential, so that an auxiliary capacitor that compensates for the insufficient capacity of the organic EL element 41 is provided as necessary. It is also possible to adopt.

  In the pixel 40 configured as described above, the write transistor 43 becomes conductive in response to a high-active write scan signal WS applied to the gate electrode from the write scan circuit 60 through the scan line 51. Thereby, the write transistor 43 samples the signal voltage Vsig or the reference voltage Vofs of the video signal corresponding to the luminance information supplied from the signal output circuit 80 through the signal line 53 and writes the sampled voltage in the pixel 40. The written signal voltage Vsig or reference voltage Vofs is applied to the gate electrode of the driving transistor 42 and held in the holding capacitor 44.

  When the potential DS of the power supply line 52 (52-1 to 52-m) is at the first power supply potential Vccp, the driving transistor 42 has one electrode as a drain electrode and the other electrode as a source electrode in a saturation region. Operate. As a result, the drive transistor 42 is supplied with current from the power supply line 52 and drives the organic EL element 41 to emit light by current drive. More specifically, the drive transistor 42 operates in the saturation region, thereby supplying the organic EL element 41 with a drive current having a current value corresponding to the voltage value of the signal voltage Vsig held in the storage capacitor 44. The organic EL element 41 is caused to emit light by current driving.

  Further, when the power supply potential DS is switched from the first power supply potential Vccp to the second power supply potential Vini, the drive transistor 42 operates as a switching transistor with one electrode serving as a source electrode and the other electrode serving as a drain electrode. As a result, the drive transistor 42 stops supplying the drive current to the organic EL element 41 and puts the organic EL element 41 into a non-light emitting state. That is, the drive transistor 42 also has a function as a transistor that controls light emission / non-light emission of the organic EL element 41.

  By the switching operation of the drive transistor 42, a period during which the organic EL element 41 is in a non-light emitting state (non-light emitting period) is provided, and the ratio (duty) between the light emitting period and the non-light emitting period of the organic EL element 41 is controlled. By this duty control, the afterimage blur caused by the light emission of the pixels over one frame period can be reduced, so that the quality of the moving image can be particularly improved.

  Here, the reference voltage Vofs selectively supplied from the signal output circuit 80 through the signal line 53 corresponds to a potential (for example, a black level of the video signal) that is a reference of the signal voltage Vsig of the video signal corresponding to the luminance information. Potential).

  Of the first and second power supply potentials Vccp and Vini selectively supplied from the power supply scanning circuit 70 through the power supply line 52, the first power supply potential Vccp generates a drive current for driving the organic EL element 41 to emit light. The power supply potential for supplying to The second power supply potential Vini is a power supply potential for applying a reverse bias to the organic EL element 41. The second power supply potential Vini is set to a potential lower than the reference voltage Vofs, for example, a potential lower than Vofs−Vth, preferably a potential sufficiently lower than Vofs−Vth when the threshold voltage of the driving transistor 42 is Vth. Is done.

[2-2. Circuit operation]
Next, the circuit operation of the organic EL display device 30 in which the pixels 40 having the above-described configuration are two-dimensionally arranged in a matrix will be described with reference to the operation waveform diagrams of FIGS. To do.

  In the operation explanatory diagrams of FIGS. 10 and 11, the write transistor 43 is illustrated by a switch symbol for simplification of the drawing. Further, the equivalent capacitance 25 of the organic EL element 41 is also illustrated.

  In the timing waveform diagram of FIG. 9, the change in potential (write scan signal) WS of the scanning lines 51 (51-1 to 51-m) and the change in potential DS of the power supply lines 52 (52-1 to 52-m). , Changes in potentials (Vofs / Vsig) of the signal lines 53 (53-1 to 53-n) are shown. The timing waveform diagram of FIG. 9 further shows changes in the gate potential Vg and the source potential Vs of the drive transistor 42.

[Light emission period of the previous frame]
In the timing waveform diagram of FIG. 9, the light emission period of the organic EL element 41 in the previous frame (field) is before time t11. In the light emission period of the previous frame, the potential DS of the power supply line 52 is at the first power supply potential (hereinafter referred to as “high potential”) Vccp, and the writing transistor 43 is in a non-conductive state.

  At this time, the drive transistor 42 is designed to operate in a saturation region. As a result, as shown in FIG. 10A, the driving current (drain-source current) Ids corresponding to the gate-source voltage Vgs of the driving transistor 42 passes from the power supply line 52 through the driving transistor 42 to the organic EL element. 41. Therefore, the organic EL element 41 emits light with a luminance corresponding to the current value of the drive current Ids.

[Threshold correction preparation period]
At time t11, a new frame (current frame) for line sequential scanning is entered. Then, as shown in FIG. 10B, the second power supply potential (hereinafter, referred to as the potential DS of the power supply line 52 is sufficiently lower than Vofs−Vth with respect to the reference voltage Vofs of the signal line 53 from the high potential Vccp. Switch to Vini) (described as “low potential”).

  Here, the threshold voltage of the organic EL element 41 is Vthel, and the potential of the common power supply line 54 (cathode potential) is Vcath. At this time, if the low potential Vini is Vini <Vthel + Vcath, the source potential Vs of the drive transistor 42 is substantially equal to the low potential Vini, so that the organic EL element 41 is in a reverse bias state and extinguished.

  Next, when the potential WS of the scanning line 51 transits from the low potential side to the high potential side at time t12, the writing transistor 43 is turned on as illustrated in FIG. At this time, since the reference voltage Vofs is supplied from the signal output circuit 80 to the signal line 53, the gate potential Vg of the drive transistor 42 becomes the reference voltage Vofs. Further, the source potential Vs of the driving transistor 42 is at a potential Vini that is sufficiently lower than the reference voltage Vofs.

  At this time, the gate-source voltage Vgs of the driving transistor 42 becomes Vofs-Vini. Here, if Vofs−Vini is not larger than the threshold voltage Vth of the driving transistor 42, threshold correction processing described later cannot be performed, and thus it is necessary to set a potential relationship of Vofs−Vini> Vth.

  As described above, the process of initializing the drive transistor 42 with the gate potential Vg fixed to the reference voltage Vofs and the source potential Vs fixed to the low potential Vini is determined before the threshold correction process described later is performed. (Threshold correction preparation) processing. Therefore, the reference voltage Vofs and the low potential Vini become the initialization potentials of the gate potential Vg and the source potential Vs of the drive transistor 42, respectively.

[Threshold correction period]
Next, at time t13, as shown in FIG. 10D, when the potential DS of the power supply line 52 is switched from the low potential Vini to the high potential Vccp, the threshold value is maintained while the gate potential Vg of the driving transistor 42 is maintained. The correction process is started. That is, the source potential Vs of the drive transistor 42 starts to increase toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor 42 from the gate potential Vg.

  Here, for convenience, processing for changing the source potential Vs toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor 42 from the initialization potential Vofs with reference to the initialization potential Vofs of the gate electrode of the drive transistor 42 is corrected by the threshold value. This is called processing. As the threshold correction process proceeds, the gate-source voltage Vgs of the drive transistor 42 eventually converges to the threshold voltage Vth of the drive transistor 42. A voltage corresponding to the threshold voltage Vth is held in the holding capacitor 44.

  In the period for performing the threshold correction process (threshold correction period), in order to prevent the current from flowing exclusively to the storage capacitor 44 and not to the organic EL element 41, the organic EL element 41 is set to a cut-off state. There is a need to. For this purpose, the potential (cathode potential) Vcath of the common power supply line 54 is set to a potential at which the organic EL element 41 is cut off.

  Next, when the potential WS of the scanning line 51 transitions to the low potential side at time t14, the writing transistor 43 is turned off as illustrated in FIG. At this time, the gate electrode of the driving transistor 42 is electrically disconnected from the signal line 53 to be in a floating state. However, since the gate-source voltage Vgs is equal to the threshold voltage Vth of the drive transistor 42, the drive transistor 42 is in a cutoff state. Therefore, the drain-source current Ids does not flow through the driving transistor 42.

[Signal writing & mobility correction period]
Next, at time t15, as shown in FIG. 11B, the potential of the signal line 53 is switched from the reference voltage Vofs to the signal voltage Vsig of the video signal. Subsequently, at time t <b> 16, the potential WS of the scanning line 51 transitions to the high potential side, so that the writing transistor 43 is turned on and the signal voltage Vsig of the video signal is sampled as illustrated in FIG. 11C. To write in the pixel 40.

  By the writing of the signal voltage Vsig by the writing transistor 43, the gate potential Vg of the driving transistor 42 becomes the signal voltage Vsig. When the driving transistor 42 is driven by the signal voltage Vsig of the video signal, the threshold voltage Vth of the driving transistor 42 is canceled with a voltage corresponding to the threshold voltage Vth held in the holding capacitor 44. Details of the principle of threshold cancellation will be described later.

  At this time, the organic EL element 41 is in a cutoff state (high impedance state). Therefore, the current (drain-source current Ids) flowing from the power supply line 52 to the drive transistor 42 in accordance with the signal voltage Vsig of the video signal flows into the equivalent capacitor 25 of the organic EL element 41, and charging of the equivalent capacitor 25 starts. Is done.

  As the equivalent capacitance 25 of the organic EL element 41 is charged, the source potential Vs of the drive transistor 42 increases with time. At this time, the pixel-to-pixel variation in the threshold voltage Vth of the drive transistor 42 has already been cancelled, and the drain-source current Ids of the drive transistor 42 depends on the mobility μ of the drive transistor 42.

  Here, it is assumed that the ratio of the holding voltage Vgs of the holding capacitor 44 to the signal voltage Vsig of the video signal, that is, the write gain G is 1 (ideal value). Then, the source potential Vs of the drive transistor 42 rises to a potential of Vofs−Vth + ΔV, so that the gate-source voltage Vgs of the drive transistor 42 becomes Vsig−Vofs + Vth−ΔV.

  That is, the increase ΔV of the source potential Vs of the drive transistor 42 is subtracted from the voltage (Vsig−Vofs + Vth) held in the holding capacitor 44, in other words, the charge of the holding capacitor 44 is discharged. And negative feedback was applied. Therefore, the increase ΔV of the source potential Vs becomes a feedback amount of negative feedback.

  Thus, by applying negative feedback to the gate-source voltage Vgs with a feedback amount ΔV corresponding to the drain-source current Ids flowing through the drive transistor 42, the mobility μ of the drain-source current Ids of the drive transistor 42 is obtained. The dependence on can be negated. This canceling process is a mobility correction process for correcting the variation of the mobility μ of the driving transistor 42 for each pixel.

  More specifically, since the drain-source current Ids increases as the signal amplitude Vin (= Vsig−Vofs) of the video signal written to the gate electrode of the driving transistor 42 increases, the absolute value of the feedback amount ΔV of the negative feedback increases. The value also increases. Therefore, mobility correction processing according to the light emission luminance level is performed.

  In addition, when the signal amplitude Vin of the video signal is constant, the absolute value of the feedback amount ΔV of the negative feedback increases as the mobility μ of the driving transistor 42 increases, so that variation in mobility μ for each pixel is removed. Can do. Therefore, it can be said that the feedback amount ΔV of the negative feedback is a correction amount for mobility correction. Details of the principle of mobility correction will be described later.

[Light emission period]
Next, at time t17, the potential WS of the scanning line 51 changes to the low potential side, so that the writing transistor 43 is turned off as illustrated in FIG. As a result, the gate electrode of the driving transistor 42 is electrically disconnected from the signal line 53 and is in a floating state.

  Here, when the gate electrode of the drive transistor 42 is in a floating state, the storage capacitor 44 is connected between the gate and the source of the drive transistor 42, so that the source potential Vs of the drive transistor 42 is linked. The gate potential Vg also varies. Thus, the operation in which the gate potential Vg of the drive transistor 42 varies in conjunction with the variation in the source potential Vs is a bootstrap operation by the storage capacitor 44.

  The gate electrode of the drive transistor 42 is in a floating state, and at the same time, the drain-source current Ids of the drive transistor 42 starts to flow through the organic EL element 41, whereby the anode potential of the organic EL element 41 is set according to the current Ids. To rise.

  When the anode potential of the organic EL element 41 exceeds Vthel + Vcath, a drive current starts to flow through the organic EL element 41, and the organic EL element 41 starts to emit light. The increase in the anode potential of the organic EL element 41 is none other than the increase in the source potential Vs of the drive transistor 42. When the source potential Vs of the drive transistor 42 increases, the gate potential Vg of the drive transistor 42 also increases in conjunction with the bootstrap operation of the storage capacitor 44.

  At this time, assuming that the bootstrap gain is 1 (ideal value), the amount of increase in the gate potential Vg is equal to the amount of increase in the source potential Vs. Therefore, the gate-source voltage Vgs of the drive transistor 42 is kept constant at Vsig−Vofs + Vth−ΔV during the light emission period. At time t18, the potential of the signal line 53 is switched from the signal voltage Vsig of the video signal to the reference voltage Vofs.

  In the series of circuit operations described above, each processing operation of threshold correction preparation, threshold correction, signal voltage Vsig writing (signal writing), and mobility correction is executed in one horizontal scanning period (1H). Further, the signal writing and mobility correction processing operations are executed in parallel during the period from time t16 to t17.

(Threshold cancellation principle)
Here, the principle of threshold cancellation (that is, threshold correction) of the drive transistor 42 will be described. The drive transistor 42 operates as a constant current source because it is designed to operate in the saturation region. As a result, a constant drain-source current (drive current) Ids given by the following equation (1) is supplied from the drive transistor 42 to the organic EL element 41.
Ids = (1/2) · μ (W / L) Cox (Vgs−Vth) ² (1)
Here, W is the channel width of the driving transistor 42, L is the channel length, and Cox is the gate capacitance per unit area.

  FIG. 12 shows the characteristics of the drain-source current Ids versus the gate-source voltage Vgs of the drive transistor 42.

  As shown in this characteristic diagram, if no cancellation process is performed for the variation of the threshold voltage Vth of the drive transistor 42 for each pixel, the drain-source current corresponding to the gate-source voltage Vgs when the threshold voltage Vth is Vth1. Ids becomes Ids1.

  On the other hand, when the threshold voltage Vth is Vth2 (Vth2> Vth1), the drain-source current Ids corresponding to the same gate-source voltage Vgs is Ids2 (Ids2 <Ids). That is, when the threshold voltage Vth of the drive transistor 42 varies, the drain-source current Ids varies even if the gate-source voltage Vgs is constant.

On the other hand, in the pixel (pixel circuit) 40 having the above configuration, as described above, the gate-source voltage Vgs of the driving transistor 42 at the time of light emission is Vsig−Vofs + Vth−ΔV. Therefore, when this is substituted into the equation (1), the drain-source current Ids is expressed by the following equation (2).
Ids = (1/2) · μ (W / L) Cox (Vsig−Vofs−ΔV) ²
(2)

  That is, the term of the threshold voltage Vth of the drive transistor 42 is canceled, and the drain-source current Ids supplied from the drive transistor 42 to the organic EL element 41 does not depend on the threshold voltage Vth of the drive transistor 42. As a result, even if the threshold voltage Vth of the drive transistor 42 varies from pixel to pixel due to variations in the manufacturing process of the drive transistor 42 and changes over time, the drain-source current Ids does not vary, and thus the light emission of the organic EL element 41 occurs. The brightness can be kept constant.

(Principle of mobility correction)
Next, the principle of mobility correction of the drive transistor 42 will be described. FIG. 13 shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the drive transistor 42 and a pixel B having a relatively low mobility μ of the drive transistor 42 are compared. When the driving transistor 42 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

  Consider a case where, for example, the signal amplitude Vin (= Vsig−Vofs) of the same level is written to both the pixels A and B in the gate electrode of the drive transistor 42 in a state where the mobility μ varies between the pixels A and B. In this case, if the mobility μ is not corrected at all, it is between the drain-source current Ids1 ′ flowing through the pixel A having a high mobility μ and the drain-source current Ids2 ′ flowing through the pixel B having a low mobility μ. There will be a big difference. Thus, when a large difference occurs between the pixels in the drain-source current Ids due to the variation in mobility μ from pixel to pixel, the uniformity of the screen is impaired.

  Here, as is clear from the transistor characteristic equation of Equation (1), the drain-source current Ids increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 13, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel B having a low mobility.

  Therefore, by applying negative feedback to the gate-source voltage Vgs with a feedback amount ΔV corresponding to the drain-source current Ids of the driving transistor 42 by the mobility correction processing, the negative feedback increases as the mobility μ increases. become. As a result, variation in mobility μ for each pixel can be suppressed.

  Specifically, when the feedback amount ΔV1 is corrected in the pixel A having a high mobility μ, the drain-source current Ids greatly decreases from Ids1 ′ to Ids1. On the other hand, since the feedback amount ΔV2 of the pixel B having a low mobility μ is small, the drain-source current Ids decreases from Ids2 ′ to Ids2, and does not decrease that much. As a result, since the drain-source current Ids1 of the pixel A and the drain-source current Ids2 of the pixel B are substantially equal, the variation in mobility μ from pixel to pixel is corrected.

  In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current Ids.

  Therefore, by applying negative feedback to the gate-source voltage Vgs with a feedback amount ΔV corresponding to the drain-source current Ids of the driving transistor 42, the current value of the drain-source current Ids of the pixels having different mobility μ. Is made uniform. As a result, variation in mobility μ for each pixel can be corrected. That is, the process of applying negative feedback to the gate-source voltage Vgs of the drive transistor 42 with the feedback amount ΔV corresponding to the current flowing through the drive transistor 42 (drain-source current Ids) is the mobility correction process.

  Here, in the pixel (pixel circuit) 40 shown in FIG. 8, the relationship between the signal voltage Vsig of the video signal and the drain-source current Ids of the drive transistor 42 according to the presence or absence of threshold correction and mobility correction is shown in FIG. I will explain.

  14, (A) does not perform both threshold correction and mobility correction, (B) does not perform mobility correction, and performs only threshold correction, (C) performs threshold correction and mobility correction. Each case is shown. As shown in FIG. 14A, when neither threshold correction nor mobility correction is performed, the drain-source current Ids is caused by variations in the threshold voltage Vth and the mobility μ for each of the pixels A and B. A large difference occurs between the pixels A and B.

  On the other hand, when only threshold correction is performed, as shown in FIG. 14B, although the variation in the drain-source current Ids can be reduced to some extent, it is caused by the variation in the mobility μ between the pixels A and B. The difference between the drain-source current Ids between the pixels A and B to be left remains. Then, by performing both the threshold correction and the mobility correction, as shown in FIG. 14C, the drain between the pixels A and B due to the variation of the threshold voltage Vth and the mobility μ for each of the pixels A and B. -The difference in the current Ids between the sources can be almost eliminated. Therefore, the luminance variation of the organic EL element 41 does not occur at any gradation, and a display image with good image quality can be obtained.

  In addition to the threshold correction and mobility correction functions, the pixel 40 shown in FIG. 8 has the function of bootstrap operation by the storage capacitor 44 described above. Obtainable.

  That is, even if the source potential Vs of the drive transistor 42 changes with time-dependent changes in the IV characteristics of the organic EL element 41, the gate-source potential Vgs of the drive transistor 42 is set by the bootstrap operation by the storage capacitor 44. Can be kept constant. Therefore, the current flowing through the organic EL element 41 does not change and is constant. As a result, since the light emission luminance of the organic EL element 41 is also kept constant, even if the IV characteristic of the organic EL element 41 changes with time, it is possible to realize an image display without luminance deterioration associated therewith.

(About the optimal correction time for mobility correction)
As is clear from the above-described operation explanation, when considering a driving transistor with high mobility and a driving transistor with low mobility, the driving transistor with high mobility is compared to the driving transistor with low mobility in the mobility correction period. As a result, the source potential Vs greatly increases. In addition, since the potential difference Vgs between the gate and the source of the driving transistor becomes smaller as the source potential Vs increases, current hardly flows to the driving transistor.

  Therefore, by adjusting the correction time of the mobility correction and changing the correction amount (feedback amount ΔV in the negative feedback) for the gate input of the drive transistor 42, that is, the signal voltage Vsig of the video signal, the drive transistor having a different mobility μ is obtained. On the other hand, the same current can flow. From this, it is necessary to optimize the correction time for mobility correction in the signal voltage Vsig of the video signal, that is, to set the correction time for mobility correction to an optimal correction time according to the signal voltage Vsig of the video signal.

The optimum correction time t for mobility correction (hereinafter sometimes simply referred to as “correction time t”) is:
t = C / (kμVsig) (3)
It is given by Here, the constant k is k = (1/2) (W / L) Cox. Further, C is a capacity of a node that is discharged when the mobility correction is performed. In the circuit example of FIG. 2, C is an equivalent capacity (capacitance component Cel) of the organic EL element 41 and a combined capacity of the storage capacitor 44.

  The correction time t for mobility correction is determined by the timing at which the write transistor 43 shifts from the conductive state to the non-conductive state. Then, the writing transistor 43 is cut off when the potential difference between the gate potential and the potential of the signal line 53, that is, the gate-source voltage reaches the threshold voltage Vth, that is, shifts from the conductive state to the non-conductive state.

  Here, it is known that the variation in mobility μ for each pixel can be corrected more reliably by setting the correction time t for mobility correction to be inversely proportional to the signal voltage Vsig of the video signal. Therefore, the falling waveform when the write pulse WS applied to the gate electrode of the write transistor 43 transitions from the high level to the low level is a waveform that is inversely proportional to the signal voltage Vsig of the video signal as shown in FIG. It is set to become. When the write transistor 43 is a P channel, a rising waveform is obtained.

  By setting the falling waveform of the write pulse WS to a waveform that is inversely proportional to the signal voltage Vsig of the video signal, when the gate-source voltage of the write transistor 43 reaches the threshold voltage Vth, the write transistor 43 Will be cut off. Therefore, the correction time t for mobility correction can be set to be inversely proportional to the signal voltage Vsig of the video signal.

  This will be described more specifically with reference to the waveform diagram of FIG. When the signal voltage Vsig (white) corresponding to the white level is written, the writing transistor 43 is cut off when the gate-source voltage becomes Vsig (white) + Vth, and therefore the mobility correction correction time t (white) Is set to the shortest. Further, when the signal voltage Vsig (gray) corresponding to the gray level is applied to the write transistor 43, the correction time t (gray) is corrected because the write transistor 43 is cut off when the gate-source voltage becomes Vsig (gray) + Vth. It is set longer than time t (white).

  Not only the falling waveform of the write pulse WS but also the waveform for which the rising waveform of the write pulse WS is proportional to the signal voltage Vsig can be used to set the mobility correction correction time t to the signal voltage of the video signal. It can be set to be inversely proportional to Vsig.

  Thus, by setting the correction time t for mobility correction so as to be inversely proportional to the signal voltage Vsig of the video signal, the correction time t can be set corresponding to the signal voltage Vsig of the video signal. As a result, the dependence of the drain-source current Ids of the driving transistor 42 on the mobility μ over the entire level range (all gradations) of the signal voltage Vsig from the black level to the white level, that is, the mobility μ for each pixel. Variations can be canceled (corrected) more reliably.

(Write scanning circuit)
Next, a specific configuration of the write scanning circuit 60 that generates the write pulse WS having a falling waveform that is inversely proportional to the signal voltage Vsig of the video signal will be described.

  As described above, the write pulse WS (WS 1 to WSm) applied to the gate electrode of the write transistor 43 is output from the write scanning circuit 60. The write scanning circuit 60 includes a shift register 61, a logic circuit 62, a level shift circuit 63, and an output circuit 64, for example, as shown in FIG.

  In the write scanning circuit 60 having the above-described configuration, the level shift circuit 63 outputs a pulse signal of a logic level (first amplitude) output from the logic circuit 62 to a level larger than the logic level necessary for driving the write transistor 43 ( The level is shifted to a pulse signal having a second amplitude. The pulse signal level-shifted by the level shift circuit 63 is supplied to the pixel array unit 50 as an address pulse WS (WS1 to WSm) through an output circuit 64 composed of a plurality of stages of buffers.

  As the level shift circuit 63, the level shift circuit according to any of the first to fourth embodiments described above can be used. Specifically, by using the level shift circuit according to the second embodiment and controlling the transient of the falling of the output pulse signal out by the voltage value of the DC voltage in1, the falling is inversely proportional to the signal voltage Vsig. A waveform write pulse WS can be generated.

  Further, by using the level shift circuit according to the third embodiment and controlling the transient of the falling of the output pulse signal out by the amplitude of the pulse signal in2, the write pulse having a falling waveform that is inversely proportional to the signal voltage Vsig is used. WS can be generated. Then, by setting the voltage value of the DC voltage in1 or the amplitude of the pulse signal in2 to an optimum value, it is possible to obtain a write pulse WS having a falling waveform in which the optimum value can be set as the correction time t for mobility correction.

  On the other hand, as described above, by making the rising waveform of the write pulse WS proportional to the signal voltage Vsig, the correction time t for mobility correction is inversely proportional to the signal voltage Vsig of the video signal. Can be set. Therefore, by using the level shift circuit according to the first embodiment and controlling the rising transient of the output pulse signal out by the voltage value of the DC voltage in1, the write pulse WS having a rising waveform proportional to the signal voltage Vsig is used. Can be generated.

  In addition, by using the level shift circuit according to the fourth embodiment and controlling the rising transient of the output pulse signal out by the amplitude of the pulse signal in1, the write pulse WS having a rising waveform proportional to the signal voltage Vsig is generated. Can be generated. Then, by setting the voltage value of the DC voltage in1 or the amplitude of the pulse signal in1 to an optimum value, it is possible to obtain a write pulse WS having a rising waveform in which the optimum value can be set as the correction time t for mobility correction.

  Incidentally, when the level shift circuit according to the first and second embodiments is used, it is only necessary to supply the DC voltage in1 in common to all the pixel rows. Therefore, when the level shift circuit according to the third and fourth embodiments is used. Compared with the advantage, the wiring layout can be simplified. On the other hand, when the level shift circuits according to the third and fourth embodiments are used, the pulse signals in2 and in1 are in an inactive state in a period other than the level shift period. Part becomes non-operational. Therefore, there is an advantage that power consumption can be reduced as compared with the case where the level shift circuit according to the first and second embodiments is used.

  As described above, in the organic EL display device having the level shift circuit 63, the level shift circuit 63 according to any one of the first to fourth embodiments described above is used as the level shift circuit 63. An effect can be obtained. That is, since the write pulse WS having a falling waveform or a rising waveform that can set an optimum value as the correction time t for mobility correction can be generated, variation in mobility μ for each pixel can be more reliably corrected. .

Here, the case where the level shift circuit according to the present invention is used as a level shift circuit in the writing scanning circuit of the organic EL display device has been described as an example. However, the present invention is not limited to this example. That is, the level shift circuit according to the present invention can be used as the level shift circuit in all display devices having a level shift circuit that needs to control the transient of the level-shifted pulse signal.

<3. Application example>
The display device using the level shift circuit according to the present invention described above displays a video signal input to an electronic device or a video signal generated in the electronic device as an image or a video for display in any field. It can be applied to a device.

  According to the display device using the level shift circuit according to the present invention, the variation in mobility μ for each pixel can be more reliably corrected. Therefore, the display quality of the display device of the electronic device can be improved by mounting the display device using the level shift circuit according to the present invention as the display device of the electronic device in all fields.

  The display device according to the present invention includes a module-shaped one having a sealed configuration. An example of the module shape is a display module formed by attaching a facing portion such as transparent glass to the pixel array portion. The transparent facing portion may be provided with a color filter, a protective film, etc., and further the above-described light shielding film. Note that the display module may be provided with a circuit unit for inputting / outputting a signal to the pixel array unit from the outside, an FPC (flexible printed circuit), and the like.

  Specific examples of electronic devices to which the present invention is applied will be described below. As an example, the present invention can be applied to various electronic devices shown in FIGS. 17 to 21, for example, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, and a display device such as a video camera. .

  FIG. 17 is a perspective view showing an appearance of a television set to which the present invention is applied. The television set according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like. And the television set which concerns on this application example is produced by using the display apparatus by this invention as the video display screen part 101. FIG.

  18A and 18B are perspective views showing the appearance of a digital camera to which the present invention is applied. FIG. 18A is a perspective view seen from the front side, and FIG. 18B is a perspective view seen from the back side. The digital camera according to this application example includes a flash light emitting unit 111, a display unit 112, a menu switch 113, a shutter button 114, and the like. Then, by using the display device according to the present invention as the display unit 112, the digital camera according to this application example is manufactured.

  FIG. 19 is a perspective view showing an external appearance of a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like. Then, by using the display device according to the present invention as the display unit 123, the notebook personal computer according to this application example is manufactured.

  FIG. 20 is a perspective view showing the appearance of a video camera to which the present invention is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. Then, by using the display device according to the present invention as the display unit 134, the video camera according to this application example is manufactured.

  FIG. 21 is an external view showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which (A) is a front view in an open state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view.

A cellular phone according to this application example includes an upper casing 141, a lower casing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub-display 145, a picture light 146, a camera 147, and the like. Then, by using the display device according to the present invention as the display 144 or the sub display 145, the mobile phone according to this application example is manufactured.

  DESCRIPTION OF SYMBOLS 10, 10A, 10B ... Level shift circuit, 11, 21 ... 1st circuit part, 12, 22 ... 2nd circuit part, 30 ... Organic EL display device, 40 ... Pixel, 41 ... Organic EL element, 42 ... Drive Transistors 43... Write transistors 44. Retention capacitors 50. Pixel array units 51 (51-1 to 51-m) Scan lines 52 (52-1 to 52-m) Power supply lines 53 (53 -1 to 53-n) ... signal line, 54 ... common power supply line, 60 ... write scanning circuit, 61 ... shift register, 62 ... logic circuit, 63 ... level shift circuit, 64 ... output circuit, 70 ... power supply scanning Circuit 80 ... Signal output circuit 90 ... Display panel

Claims (8)

First and second transistors having first and second transistors of opposite conductivity type, whose gate electrodes are connected in common and serving as input nodes, and a third transistor connected between the first and second transistors. A circuit unit is connected in parallel between the first power source and the second power source;
The gate electrode of the third transistor of the first circuit portion is at an output node of the second circuit portion, and the gate electrode of the third transistor of the second circuit portion is of the first circuit portion. Connected to each output node,
When the first amplitude pulse signal input to one input node of the first and second circuit units is level-shifted to a second amplitude pulse signal larger than the first amplitude, A level shift circuit for controlling a transient of the pulse signal having the second amplitude according to a voltage value of the other input node of the two circuit units. The level shift circuit according to claim 1, wherein the voltage value of the other input node is determined by a voltage value of a DC voltage input to the other input node. The level shift circuit according to claim 1, wherein the voltage value of the other input node is determined by the amplitude of a pulse signal input to the other input node. 4. The level shift circuit according to claim 2, wherein the voltage value of the other input node is a voltage value when the pulse signal having the second amplitude rises or falls. First and second transistors having first and second transistors of opposite conductivity type, whose gate electrodes are connected in common and serving as input nodes, and a third transistor connected between the first and second transistors. A circuit unit is connected in parallel between the first power source and the second power source;
The gate electrode of the third transistor of the first circuit portion is at an output node of the second circuit portion, and the gate electrode of the third transistor of the second circuit portion is of the first circuit portion. Connected to each output node,
When the first amplitude pulse signal input to one input node of the first and second circuit units is level-shifted to a second amplitude pulse signal larger than the first amplitude, A display device using a level shift circuit that controls a transient of the pulse signal having the second amplitude according to a voltage value of the other input node of the two circuit portions. The display device
An electro-optical element, a writing transistor in which a gate electrode is connected to a scanning line and one electrode is connected to a signal line to which a video signal is supplied, and a gate electrode is connected to the other electrode of the writing transistor to supply power One electrode is connected to the line, the other electrode is connected to the anode electrode of the electro-optic element, and one electrode is connected to the gate electrode of the drive transistor, and the other electrode of the drive transistor is connected to the other electrode. A pixel array unit in which pixels having a storage capacitor to which the other electrode is connected are arranged in a matrix;
A power supply scanning circuit for selectively supplying a first power supply potential and a second power supply potential lower than the first power supply potential to the power supply line;
A writing scanning circuit for writing the video signal by the writing transistor by giving a writing pulse to the writing transistor;
A mobility correction processing function for applying negative feedback to the gate input side of the drive transistor with a correction amount corresponding to the current flowing through the drive transistor,
The write scanning circuit uses the level shift circuit as a level shift circuit that shifts a level of a pulse signal having a first amplitude to a pulse signal having a second amplitude larger than the first amplitude to generate the write pulse. 5. The display device according to 5. First and second transistors having first and second transistors of opposite conductivity type, whose gate electrodes are connected in common and serving as input nodes, and a third transistor connected between the first and second transistors. A circuit unit is connected in parallel between the first power source and the second power source;
The gate electrode of the third transistor of the first circuit portion is at an output node of the second circuit portion, and the gate electrode of the third transistor of the second circuit portion is of the first circuit portion. Connected to each output node,
When the first amplitude pulse signal input to one input node of the first and second circuit units is level-shifted to a second amplitude pulse signal larger than the first amplitude, An electronic apparatus having a display device using a level shift circuit that controls a transient of the pulse signal having the second amplitude according to a voltage value of the other input node of the two circuit portions. The display device
An electro-optical element, a writing transistor in which a gate electrode is connected to a scanning line and one electrode is connected to a signal line to which a video signal is supplied, and a gate electrode is connected to the other electrode of the writing transistor to supply power One electrode is connected to the line, the other electrode is connected to the anode electrode of the electro-optic element, and one electrode is connected to the gate electrode of the drive transistor, and the other electrode of the drive transistor is connected to the other electrode. A pixel array unit in which pixels having a storage capacitor to which the other electrode is connected are arranged in a matrix;
A power supply scanning circuit for selectively supplying a first power supply potential and a second power supply potential lower than the first power supply potential to the power supply line;
A writing scanning circuit for writing the video signal by the writing transistor by giving a writing pulse to the writing transistor;
A mobility correction processing function for applying negative feedback to the gate input side of the drive transistor with a correction amount corresponding to the current flowing through the drive transistor,
The write scanning circuit uses the level shift circuit as a level shift circuit that shifts a level of a pulse signal having a first amplitude to a pulse signal having a second amplitude larger than the first amplitude to generate the write pulse. 7. The electronic device according to 7.

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