JP2008310127A - Display device, driving method of display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress stripe unevenness resulting from dispersion of a gate-source voltage Vgs of a drive transistor resulting from leak by reducing dispersion in detection period of a threshold voltage Vth in a 2Tr+C pixel configuration. <P>SOLUTION: The positive-side power source of a final stage buffer 431 in an output circuit 43 of a write scan circuit 40 is separated from a circuit part of the previous state side, and a source voltage Vdd2 falling in a pulse-like manner (rectangular wave) is supplied as the positive-side power source to fall an output pulse B or scan line potential WS by the fall of the source voltage Vdd2, whereby the fall response speed of the scan line potential SW is hastened to suppress the dispersion of detection period of the threshold voltage Vth of the drive transistor determined by the fall timing of the scan line potential WS. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device, a display device driving method, and an electronic apparatus, and more particularly to a flat (flat panel) display device in which pixels including electro-optical elements are arranged in a matrix (matrix shape), and the display device And an electronic apparatus having the display device.

  In recent years, in the field of display devices that perform image display, flat display devices in which pixels (pixel circuits) including light emitting elements are arranged in a matrix are rapidly spreading. As a flat display device, as a light emitting element of a pixel, a so-called current-driven electro-optical element whose light emission luminance changes according to a current value flowing through the device, for example, a phenomenon that emits light when an electric field is applied to an organic thin film is used. An organic EL display device using an organic EL (Electro Luminescence) element has been developed and commercialized.

  The organic EL display device has the following features. That is, since the organic EL element can be driven with an applied voltage of 10 V or less, it has low power consumption and is a self-luminous element. Therefore, for each pixel including the liquid crystal cell, the liquid crystal cell emits light from the light source (backlight). Compared to a liquid crystal display device that displays an image by controlling the light intensity, the image is highly visible, and the liquid crystal display device does not require an illumination member such as a backlight. Is easy. Furthermore, since the response speed of the organic EL element is as high as about several μsec, an afterimage at the time of displaying a moving image does not occur.

  In the organic EL display device, as in the liquid crystal display device, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although the simple matrix display device has a simple structure, the light-emission period of the electro-optic element decreases with an increase in the number of scanning lines (that is, the number of pixels), thereby realizing a large-sized and high-definition display device. There are problems such as difficult.

  Therefore, in recent years, the current flowing through the electro-optical element is controlled by an active element provided in the same pixel circuit as the electro-optical element, for example, an insulated gate field effect transistor (generally, a TFT (Thin Film Transistor)). Active matrix display devices have been actively developed. An active matrix display device can easily realize a large-sized and high-definition display device because the electro-optic element continues to emit light over a period of one frame (field).

  By the way, it is generally known that the IV characteristic (current-voltage characteristic) of the organic EL element is deteriorated with time (so-called deterioration with time). In a pixel circuit using an N-channel TFT as a transistor for driving an organic EL element with current (hereinafter referred to as “driving transistor”), the organic EL element is connected to the source side of the driving transistor. When the IV characteristic of the organic EL element deteriorates with time, the gate-source voltage Vgs of the driving transistor changes, and as a result, the emission luminance of the organic EL element also changes.

  This will be described more specifically. The source potential of the drive transistor is determined by the operating point of the drive transistor and the organic EL element. When the IV characteristic of the organic EL element deteriorates, the operating point of the driving transistor and the organic EL element fluctuates. Therefore, even if the same voltage is applied to the gate of the driving transistor, the source potential of the driving transistor changes. To do. As a result, since the source-gate voltage Vgs of the drive transistor changes, the value of the current flowing through the drive transistor changes. As a result, since the value of the current flowing through the organic EL element also changes, the light emission luminance of the organic EL element changes.

  In addition, in a pixel circuit using a polysilicon TFT, in addition to the deterioration over time of the IV characteristics of the organic EL element, the threshold voltage Vth of the driving transistor and the mobility of the semiconductor thin film that constitutes the channel of the driving transistor (hereinafter referred to as the following) Μ described as “driving transistor mobility” changes with time, and the threshold voltage Vth and mobility μ vary from pixel to pixel due to variations in the manufacturing process (individual transistor characteristics vary).

  If the threshold voltage Vth and mobility μ of the driving transistor differ from pixel to pixel, the current value flowing through the driving transistor varies from pixel to pixel. Therefore, even if the same voltage is applied to the gate of the driving transistor between the pixels, The light emission luminance of the EL element varies among the pixels, and as a result, the uniformity of the screen is lost.

  Therefore, even if the IV characteristic of the organic EL element deteriorates with time, or the threshold voltage Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element is not affected by those effects. In order to keep constant, the compensation function for the characteristic variation of the organic EL element, the correction for the variation of the threshold voltage Vth of the driving transistor (hereinafter referred to as “threshold correction”), the mobility μ of the driving transistor Each pixel circuit is provided with a correction function for correction of fluctuations (hereinafter referred to as “mobility correction”) (see, for example, Patent Document 1).

JP 2006-133542 A

  In the prior art described in Patent Document 1, each pixel circuit is provided with a compensation function for a characteristic variation of the organic EL element and a correction function for a variation in threshold voltage Vth and mobility μ of the drive transistor, so that Even if the IV characteristics deteriorate over time or the threshold voltage Vth and mobility μ of the driving transistor change over time, the light emission luminance of the organic EL element can be kept constant without being affected by them. On the other hand, however, the number of elements constituting the pixel circuit is large, which hinders the miniaturization of the pixel size and the high definition of the display device.

  On the other hand, in order to reduce the number of elements and wirings constituting the pixel circuit, for example, the power supply potential supplied to the drive transistor of the pixel circuit can be switched between the first potential and a lower second potential. And adopting a method of omitting the transistor for controlling the light emission period / non-light emission period by providing the drive transistor with a function of controlling the light emission period / non-light emission period of the organic EL element by switching the power supply potential. Can be considered.

  By adopting such a method, the minimum number of elements, specifically, a write transistor that samples a video signal and writes it in a pixel, a storage capacitor that holds the video signal written by this write transistor, and this A 2Tr + C pixel circuit can be configured by a driving transistor that drives the electro-optic element based on the video signal held in the holding capacitor, that is, two transistors (Tr) and one or more capacitor elements (C).

  In the organic EL display device having the 2Tr + C pixel circuit, in performing threshold correction of the driving transistor, first, the power supply potential supplied to the driving transistor is switched to the second potential, and then the writing transistor is turned on to start from the signal line. The gate potential and source potential of the driving transistor are initialized by writing the reference potential, and then the threshold voltage Vth of the driving transistor is detected and held in the holding capacitor by switching the power supply potential to the first potential. (The details will be described later).

  After the threshold voltage Vth is detected, the writing transistor is turned off. As a result, the gate electrode of the driving transistor enters a floating state. At this time, since the gate-source voltage Vgs of the drive transistor is equal to the threshold voltage Vth held in the storage capacitor, the drive transistor 22 is in a cut-off state, and the drain-source current Ids does not flow through the drive transistor. .

  However, this is a story in an ideal state, and in actual operation, a minute leak current flows through the drive transistor even when the gate-source voltage Vgs of the drive transistor is equal to or lower than the threshold voltage Vth. Due to this leakage current, the source potential Vs of the driving transistor rises, and accordingly the gate potential Vg also rises (due to a phenomenon similar to a bootstrap operation described later).

  Here, when the detection period of the threshold voltage Vth (determined by the switching timing of the power supply potential supplied to the driving transistor from the second potential to the first potential and the transition timing of the writing transistor from the conductive state to the non-conductive state) varies. The gate-source voltage Vgs of the driving transistor after the detection period varies, and the variation of the gate-source voltage Vgs due to the variation of the source potential Vs and the gate potential Vg due to the subsequent leakage increases. The variation is recognized as stripes at the time of light emission.

  Further, as the resolution of display devices increases and the number of pixels increases, the detection period of the threshold voltage Vth becomes shorter as the period of 1H (H is a horizontal scanning period) becomes shorter. As a result, when a leak current flows through the drive transistor with a variation in the threshold voltage Vth, the variation in the gate-source voltage Vgs of the drive transistor due to the leak becomes more significant, and the stripe unevenness is worsened. Concerned.

  Therefore, the present invention makes it possible to reduce the variation in the detection period of the threshold voltage Vth in the 2Tr + C pixel configuration and suppress the unevenness due to the variation in the gate-source voltage Vgs of the drive transistor due to the leak. It is an object of the present invention to provide a display device, a driving method of the display device, and an electronic apparatus having the display device.

  In order to achieve the above object, the present invention provides an electro-optic element, a writing transistor for writing a video signal, a holding capacitor for holding the video signal written by the writing transistor, and the holding capacitor. A pixel array unit including pixels including drive transistors that drive the electro-optic elements based on a video signal is arranged in a matrix, and is wired for each pixel row of the pixel array unit, and supplies current to the drive transistors. A first scanning circuit for selectively supplying a first potential and a second potential lower than the first potential to the power supply line; and driving the write transistor for each pixel row of the pixel array section. A display device including a second scanning circuit that selects each pixel of a pixel array unit in a row unit has the following configuration. To have.

  That is, during the period when the second potential is selected, the write transistor is turned on, and then the detection period for detecting the threshold voltage of the driving transistor by switching from the second potential to the first potential is started. Thereafter, the write transistor is turned off to end the detection period, and a power supply voltage that changes in a pulse form as a power supply voltage of at least one final stage buffer of the first scanning circuit and the second scanning circuit is set. In other words, at least one of the start timing and the end timing of the detection period is determined by the transition timing of the power supply voltage.

  In the display device having the above structure and the electronic device including the display device, the second potential is selected by the first scanning circuit, whereby the gate potential of the driving transistor becomes the second potential, and the second potential is selected in the selection period of the second potential. By making the writing transistor conductive by the scanning circuit, the reference voltage is written from the signal line by the writing transistor, the gate potential of the driving transistor becomes the reference potential, and the source potential and the gate potential of the driving transistor are initialized. .

  Next, the detection period for detecting the threshold voltage of the driving transistor is started by switching from the second potential to the first potential by the first scanning circuit. That is, the switching timing from the second potential to the first potential is the start timing of the detection period. Thereafter, the writing transistor is turned off by the second scanning circuit, so that the threshold voltage detection period ends. That is, the transition timing from the conductive state to the non-conductive state of the write transistor is the end timing of the detection period.

  Then, a power supply voltage that changes in a pulse shape is used as the power supply voltage of at least one of the first scanning circuit and the second scanning circuit, and at least one of the start timing and the end timing of the detection period at the transition timing of the power supply voltage. To decide. Since the rise / fall of the power supply voltage that transitions in a pulse shape is steep, the power supply of the final stage buffer is shared with the previous stage side, and the detection period starts at the rise / fall timing of the pulse on the previous stage side The response speed of at least one of the start and end of the detection period can be made faster than when determining at least one of the timing and the end timing.

  Here, the detection period for detecting the threshold voltage of the driving transistor is determined by the switching timing from the second potential to the first potential and the transition timing from the conductive state to the non-conductive state of the writing transistor. Since the variation in the detection period is caused by the variation in each stage corresponding to the pixel rows of the first and second scanning circuits or the variation due to the degree of transient rounding, at least one response at the start and end of the detection period Since the speed can be increased, variations in the detection period for each stage can be suppressed.

  According to the present invention, it is possible to suppress the unevenness due to the variation in the detection period by suppressing the variation for each stage of the detection period. Even if the 1H period becomes shorter and the detection period becomes shorter as the display device becomes higher in definition, this can be dealt with.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a system configuration diagram showing an outline of the configuration of an active matrix display device according to an embodiment of the present invention.

  Here, as an example, an active matrix organic EL display device using, as an example, a current-driven electro-optic element whose emission luminance changes according to the value of current flowing through the device, for example, an organic EL element as a light-emitting element of a pixel (pixel circuit) This case will be described as an example.

  As shown in FIG. 1, the organic EL display device 10 according to this embodiment includes a pixel array unit 30 in which pixels (PXLC) 20 are two-dimensionally arranged in a matrix (matrix shape), and the pixel array unit 30. It has a configuration that includes a drive unit that is disposed in the periphery and drives each pixel 20. For example, a writing scanning circuit 40, a power supply scanning circuit 50, and a horizontal driving circuit 60 are provided as driving units for driving the pixels 20.

  The pixel array unit 30 is provided with scanning lines 31-1 to 31-m and power supply lines 32-1 to 32-m for each pixel row with respect to a pixel array of m rows and n columns. The signal lines 33-1 to 33-n are wired.

  The pixel array unit 30 is usually formed on a transparent insulating substrate such as a glass substrate, and has a flat (flat) panel structure. Each pixel 20 of the pixel array unit 30 can be formed using an amorphous silicon TFT (Thin Film Transistor) or a low-temperature polysilicon TFT. When the low-temperature polysilicon TFT is used, the scanning circuit 40, the power supply scanning circuit 50, and the horizontal driving circuit 60 can also be mounted on the display panel (substrate) 70 that forms the pixel array section 30.

  The writing scanning circuit 40 is configured by a shift register or the like that sequentially shifts (transfers) the start pulse sp in synchronization with the clock pulse ck, and the scanning line 31-is used when writing the video signal to each pixel 20 of the pixel array unit 30. The scanning signals WS1 to WSm are sequentially supplied to 1 to 31-m, and the pixels 20 are sequentially scanned (line sequential scanning) in units of rows.

  The power supply scanning circuit 50 includes a shift register that sequentially shifts the start pulse sp in synchronization with the clock pulse ck, and the first potential Vccp and the first potential in synchronization with the line sequential scanning by the writing scanning circuit 40. By supplying the power supply line potentials DS1 to DSm that are switched at the second potential Vini lower than Vccp to the power supply lines 32-1 to 32-m, the drive transistor 22 (see FIG. 2), which will be described later, is turned on / off. Non-conduction (off) control is performed.

  The horizontal driving circuit 60 includes a signal voltage Vsig of a video signal corresponding to luminance information supplied from a signal supply source (not shown) (hereinafter sometimes simply referred to as “signal voltage”) Vsig and a reference signal (reference voltage). ) Is appropriately selected and supplied to the signal lines 33-1 to 33-n, and is written to each pixel 20 of the pixel array unit 30 in units of rows, for example. That is, the horizontal drive circuit 60 is a signal supply unit, and adopts a line-sequential writing drive mode in which the signal voltage Vsig of the video signal is written in units of rows (lines).

  Here, the offset voltage Vofs is a reference voltage (e.g., corresponding to a black level) serving as a reference for the signal voltage Vsig of the video signal. The second potential Vini is set to a potential lower than the offset voltage Vofs, for example, a potential lower than Vofs−Vth, preferably a potential sufficiently lower than Vofs−Vth when the threshold voltage of the driving transistor 22 is Vth. Is done.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating a specific configuration example of the pixel (pixel circuit) 20.

  As shown in FIG. 2, the pixel 20 includes a current-driven electro-optical element, for example, an organic EL element 21, whose light emission luminance changes according to a current value flowing through the device, and the organic EL element 21 includes In addition, the pixel configuration includes a driving transistor 22, a writing transistor 23, and a storage capacitor 24, that is, a 2Tr + C pixel configuration including two transistors (Tr) and one or more capacitive elements (C).

  In the pixel 20 having such a configuration, an N-channel TFT is used as the driving transistor 22 and the writing transistor 23. However, the combination of the conductivity types of the driving transistor 22 and the writing transistor 23 here is only an example, and is not limited to these combinations.

  The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all the pixels 20. The drive transistor 22 has a source electrode connected to the anode electrode of the organic EL element 21 and a drain electrode connected to the power supply line 32 (32-1 to 32-m).

  The writing transistor 23 has a gate electrode connected to the scanning line 31 (31-1 to 31-m), and one electrode (source electrode / drain electrode) connected to the signal line 33 (33-1 to 33-n). The other electrode (drain electrode / source electrode) is connected to the gate electrode of the drive transistor 22.

  The storage capacitor 24 has one end connected to the gate electrode of the drive transistor 22 and the other end connected to the source electrode of the drive transistor 22 (the anode electrode of the organic EL element 21). In addition, in order to compensate for the shortage of the capacity of the organic EL element 21, an auxiliary capacity 25 is connected in parallel to the organic EL element 21 as necessary. That is, the auxiliary capacitor 25 is not an essential component and can be omitted if the capacity of the organic EL element 21 is sufficient.

  In the pixel 20 having the 2Tr + C pixel configuration, the writing transistor 23 is turned on in response to the scanning signal WS applied to the gate electrode from the writing scanning circuit 40 through the scanning line 31, and thus the horizontal driving circuit through the signal line 33. The signal voltage Vsig or the offset voltage Vofs of the video signal corresponding to the luminance information supplied from 60 is sampled and written into the pixel 20.

  The written signal voltage Vsig or offset voltage Vofs is applied to the gate electrode of the drive transistor 22 and held in the holding capacitor 24. When the potential DS of the power supply line 32 (32-1 to 32-m) is at the first potential Vccp, the driving transistor 22 is supplied with current from the power supply line 32 and is held in the storage capacitor 24. A drive current having a current value corresponding to the voltage value of the signal voltage Vsig is supplied to the organic EL element 21, and the organic EL element 21 is caused to emit light by current driving.

(Pixel structure)
FIG. 3 is a cross-sectional view illustrating an example of the cross-sectional structure of the pixel 20. As shown in FIG. 3, in the pixel 20, an insulating film 202, an insulating planarizing film 203, and a window insulating film 204 are sequentially formed on a glass substrate 201 on which pixel circuits such as a driving transistor 22 and a writing transistor 23 are formed. The organic EL element 21 is provided in the recess 204A of the window insulating film 204.

  The organic EL element 21 includes an anode electrode 205 made of metal or the like formed on the bottom of the recess 204A of the window insulating film 204, and an organic layer (electron transport layer, light emitting layer, hole transport) formed on the anode electrode 205. Layer / hole injection layer) 206 and a cathode electrode 207 made of a transparent conductive film or the like formed on the organic layer 206 in common for all pixels.

  In the organic EL element 21, the organic layer 206 is formed by sequentially depositing a hole transport layer / hole injection layer 2061, a light emitting layer 2062, an electron transport layer 2063 and an electron injection layer (not shown) on the anode electrode 205. It is formed. Then, current flows from the driving transistor 22 to the organic layer 206 through the anode electrode 205 under current driving by the driving transistor 22 in FIG. 2, so that electrons and holes are recombined in the light emitting layer 2062 in the organic layer 206. It is designed to emit light.

  As shown in FIG. 3, after the organic EL element 21 is formed on a glass substrate 201 on which a pixel circuit is formed via the insulating film 202, the insulating flattening film 203, and the window insulating film 204, in units of pixels, The sealing substrate 209 is bonded by the adhesive 210 via the passivation film 208, and the organic EL element 21 is sealed by the sealing substrate 209, whereby the display panel 70 is formed.

(Basic circuit operation of organic EL display device)
Next, the basic circuit operation of the organic EL display device 10 in which the pixels 20 having a 2Tr + C pixel configuration are two-dimensionally arranged in a matrix will be described with reference to the timing waveform diagrams of FIGS. This will be described with reference to the drawings.

  In the operation explanatory diagrams of FIGS. 5 and 6, the write transistor 23 is illustrated by a switch symbol for simplification of the drawing. In addition, the organic EL element 21 has a parasitic capacitance, and the parasitic capacitance and the auxiliary capacitance 25 are illustrated as a combined capacitance Csub.

  In the timing chart of FIG. 4, with a common time axis, the change in potential (scanning signal) WS of the scanning line 31 (31-1 to 31-m) at 1H (H is the horizontal scanning time), the power supply line 32 ( 32-1 to 32 -m), and changes in the gate potential Vg and the source potential Vs of the driving transistor 22. Further, the waveform of the potential (scanning signal) WS of the scanning line 31 is indicated by a one-dot chain line, and the potential DS of the power supply line 32 is indicated by a dotted line so that the two can be identified.

<Light emission period>
In the timing waveform diagram of FIG. 4, the organic EL element 21 is in a light emitting state (light emission period) before time t1. In this light emission period, the potential DS of the power supply line 32 is at the high potential Vccp (first potential), and the writing transistor 23 is in a non-conduction state. At this time, since the driving transistor 22 is set to operate in the saturation region, the gate-source voltage of the driving transistor 22 is supplied from the power supply line 32 through the driving transistor 22 as shown in FIG. A drive current (drain-source current) Ids corresponding to Vgs is supplied to the organic EL element 21. Therefore, the organic EL element 21 emits light with a luminance corresponding to the current value of the drive current Ids.

<Threshold correction preparation period>
At time t1, a new field of line sequential scanning is entered, and as shown in FIG. 5B, the potential DS of the power supply line 32 is changed from the first potential (hereinafter referred to as “high potential”) Vccp. The second potential (hereinafter referred to as “low potential”) Vini that is sufficiently lower than the offset voltage Vofs−Vth of the signal line 33 is switched to.

  Here, when the threshold voltage of the organic EL element 21 is Vel and the potential of the common power supply line 34 is Vcath, if the low potential Vini is Vini <Vel + Vcath, the source potential Vs of the drive transistor 22 is substantially equal to the low potential Vini. Therefore, the organic EL element 21 is extinguished in a reverse bias state.

  Next, when the potential WS of the scanning line 31 transits from the low potential side to the high potential side at time t2, as shown in FIG. 5C, the writing transistor 23 becomes conductive. At this time, since the offset voltage Vofs is supplied from the horizontal drive circuit 60 to the signal line 33, the gate potential Vg of the drive transistor 22 becomes the offset voltage Vofs. Further, the source potential Vs of the drive transistor 22 is at a potential Vini that is sufficiently lower than the offset voltage Vofs.

  At this time, the gate-source voltage Vgs of the drive transistor 22 is Vofs-Vini. Here, if Vofs−Vini is not larger than the threshold voltage Vth of the drive transistor 22, a threshold correction operation described later cannot be performed. Therefore, it is necessary to set a potential relationship of Vofs−Vini> Vth.

  In this way, the operation of fixing and fixing the gate potential Vg of the drive transistor 22 to the offset voltage Vofs and the source potential Vs to the low potential Vini is an operation for preparing for threshold correction.

<Threshold correction period>
Next, at time t3, as shown in FIG. 5D, when the potential DS of the power supply line 32 is switched from the low potential Vini to the high potential Vccp, the source potential Vs of the drive transistor 22 starts to rise. Eventually, the gate-source voltage Vgs of the drive transistor 22 converges to the threshold voltage Vth of the drive transistor 22, and a voltage corresponding to the threshold voltage Vth is held in the storage capacitor 24.

  Here, for convenience, a period in which the threshold voltage Vth is detected and a voltage corresponding to the threshold voltage Vth is held in the storage capacitor 24 is referred to as a threshold correction period. In the threshold correction period, the common power supply line 34 is set so that the organic EL element 21 is cut off in order to prevent the current from flowing exclusively to the storage capacitor 24 side and to the organic EL element 21 side. The potential Vcath is set in advance.

  Next, at time t4, the potential WS of the scanning line 31 shifts to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. At this time, the gate electrode of the driving transistor 22 is in a floating state, but the driving transistor 22 is in a cut-off state because the gate-source voltage Vgs is equal to the threshold voltage Vth of the driving transistor 22. Therefore, the drain-source current Ids does not flow through the driving transistor 22.

<Writing period / mobility correction period>
Next, at time t5, as shown in FIG. 6B, the potential of the signal line 33 is switched from the offset voltage Vofs to the signal voltage Vsig of the video signal. Subsequently, at time t6, the potential WS of the scanning line 31 transitions to the high potential side, so that the writing transistor 23 becomes conductive as shown in FIG. 6C, and the signal voltage Vsig of the video signal is sampled. To write in the pixel 20.

  By writing the signal voltage Vsig by the writing transistor 23, the gate potential Vg of the driving transistor 22 becomes the signal voltage Vsig. When the driving transistor 22 is driven by the signal voltage Vsig of the video signal, the threshold voltage correction is performed by canceling the threshold voltage Vth of the driving transistor 22 with a voltage corresponding to the threshold voltage Vth held in the holding capacitor 24. Done. Details of the principle of threshold correction will be described later.

  At this time, since the organic EL element 21 is initially in a cut-off state (high impedance state), a current (drain-source current Ids) that flows from the power supply line 32 to the drive transistor 22 according to the signal voltage Vsig of the video signal. Flows into the composite capacitor Csub connected in parallel to the organic EL element 21, and charging of the composite capacitor Csub is started.

  Due to the charging of the composite capacitor Csub, the source potential Vs of the drive transistor 22 rises with time. At this time, the variation of the threshold voltage Vth of the drive transistor 22 from pixel to pixel has already been corrected, and the drain-source current Ids of the drive transistor 22 depends on the mobility μ of the drive transistor 22.

  Eventually, when the source potential Vs of the drive transistor 22 rises to the potential of Vofs−Vth + ΔV, the gate-source voltage Vgs of the drive transistor 22 becomes Vsig−Vofs + Vth−ΔV. That is, the increase ΔV of the source potential Vs is subtracted from the voltage (Vsig−Vofs + Vth) held in the holding capacitor 24, in other words, acts to discharge the charged charge of the holding capacitor 24, and negative feedback Has been applied. Therefore, the increase ΔV of the source potential Vs becomes a feedback amount of negative feedback.

  As described above, the drain-source current Ids flowing through the drive transistor 22 is negatively fed back to the gate input of the drive transistor 22, that is, the gate-source voltage Vgs, so that the drain-source current Ids of the drive transistor 22 is reduced. Mobility correction is performed to cancel the dependence on the mobility μ, that is, to correct the variation of the mobility μ for each pixel.

  More specifically, since the drain-source current Ids increases as the signal voltage Vsig of the video signal increases, the absolute value of the feedback amount (correction amount) ΔV of negative feedback also increases. Therefore, the mobility correction according to the light emission luminance level is performed.

  Further, when the signal voltage Vsig of the video signal is constant, the absolute value of the feedback amount ΔV of the negative feedback increases as the mobility μ of the driving transistor 22 increases, so that variation in the mobility μ for each pixel is removed. Can do. Details of the principle of mobility correction will be described later.

<Light emission period>
Next, when the potential WS of the scanning line 31 transitions to the low potential side at time t7, the writing transistor 23 is turned off as illustrated in FIG. 6D. As a result, the gate electrode of the drive transistor 22 is disconnected from the signal line 33 and is in a floating state.

  Here, when the gate electrode of the driving transistor 22 is in a floating state, if the storage capacitor 24 is connected between the gate and the source of the driving transistor 22 and the source potential Vs of the driving transistor 22 fluctuates, The gate potential Vg of the drive transistor 22 also varies in conjunction with (follows) the variation in the potential Vs. This is a bootstrap operation by the storage capacitor 24.

  At the same time, the drain-source current Ids of the drive transistor 22 starts to flow into the organic EL element 21, so that the anode potential of the organic EL element 21 becomes the drain potential of the drive transistor 22. -Increases according to the source-to-source current Ids.

  The increase in the anode potential of the organic EL element 21 is nothing but the increase in the source potential Vs of the drive transistor 22. When the source potential Vs of the drive transistor 22 rises, the gate potential Vg of the drive transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24.

  At this time, assuming that the bootstrap gain is 100% (ideal value), the amount of increase in the gate potential Vg is equal to the amount of increase in the source potential Vs. Therefore, the gate-source voltage Vgs of the drive transistor 22 is kept constant at Vsig−Vofs + Vth−ΔV during the light emission period. At time t8, the potential of the signal line 33 is switched from the signal voltage Vsig of the video signal to the offset voltage Vofs.

(Principle of threshold correction)
Here, the principle of threshold correction of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. As a result, a constant drain-source current (drive current) Ids given by the following equation (1) is supplied from the drive transistor 22 to the organic EL element 21.
Ids = (1/2) · μ (W / L) Cox (Vgs−Vth) ² (1)
Here, W is the channel width of the drive transistor 22, L is the channel length, and Cox is the gate capacitance per unit area.

  FIG. 7 shows characteristics of the drain-source current Ids of the drive transistor 22 versus the gate-source voltage Vgs.

  As shown in this characteristic diagram, when correction for variation in the threshold voltage Vth of the driving transistor 22 for each pixel is not performed, when the threshold voltage Vth is Vth1, the drain-source current Ids corresponding to the gate-source voltage Vgs. Becomes Ids1.

  On the other hand, when the threshold voltage Vth is Vth2 (Vth2> Vth1), the drain-source current Ids corresponding to the same gate-source voltage Vgs is Ids2 (Ids2 <Ids). That is, when the threshold voltage Vth of the driving transistor 22 varies, the drain-source current Ids varies even if the gate-source voltage Vgs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above configuration, as described above, the gate-source voltage Vgs of the drive transistor 22 during light emission is Vsig−Vofs + Vth−ΔV. Then, the drain-source current Ids is
Ids = (1/2) · μ (W / L) Cox (Vsig−Vofs−ΔV) ²
(2)
It is represented by

  That is, the term of the threshold voltage Vth of the drive transistor 22 is canceled, and the drain-source current Ids supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage Vth of the drive transistor 22. As a result, the drain-source current Ids does not vary even if the threshold voltage Vth of the drive transistor 22 varies from pixel to pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time. The brightness can be kept constant.

(Principle of mobility correction)
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 8 shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the driving transistor 22 and a pixel B having a relatively low mobility μ of the driving transistor 22 are compared. When the driving transistor 22 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

  For example, when the signal voltage Vsig of the video signal of the same level is written in both the pixels A and B in the state where the mobility μ is varied between the pixel A and the pixel B, the movement is not performed. There is a large difference between the drain-source current Ids1 'flowing through the pixel A having a high degree μ and the drain-source current Ids2' flowing through the pixel B having a low mobility μ. Thus, if a large difference occurs between the pixels in the drain-source current Ids due to the variation in mobility μ from pixel to pixel, the uniformity of the screen is impaired.

  Here, as is clear from the transistor characteristic equation of Equation (1), the drain-source current Ids increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 8, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel V having a low mobility.

  Therefore, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the signal voltage Vsig side of the video signal by the mobility correction operation, the larger the mobility μ, the more negative feedback is applied. It is possible to suppress the variation for each pixel of degree μ.

  Specifically, when the feedback amount ΔV1 is corrected in the pixel A having a high mobility μ, the drain-source current Ids greatly decreases from Ids1 ′ to Ids1. On the other hand, since the feedback amount ΔV2 of the pixel B having a low mobility μ is small, the drain-source current Ids decreases from Ids2 ′ to Ids2, and does not decrease that much. As a result, since the drain-source current Ids1 of the pixel A and the drain-source current Ids2 of the pixel B are substantially equal, the variation in mobility μ from pixel to pixel is corrected.

  In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current Ids.

  Therefore, by negatively feeding back the drain-source current Ids of the driving transistor 22 to the signal voltage Vsig side of the video signal, the current value of the drain-source current Ids of the pixels having different mobility μ is made uniform. As a result, variation in mobility μ for each pixel can be corrected.

  Here, in the pixel (pixel circuit) 20 shown in FIG. 2, the relationship between the signal potential (sampling potential) Vsig of the video signal and the drain-source current Ids of the drive transistor 22 depending on the presence or absence of threshold correction and mobility correction. This will be described with reference to FIG.

  In FIG. 9, (A) does not perform both threshold correction and mobility correction, (B) does not perform mobility correction, and performs only threshold correction, (C) performs threshold correction and mobility correction. Each case is shown. As shown in FIG. 9A, when neither threshold correction nor mobility correction is performed, the drain-source current Ids is caused by variations in the threshold voltage Vth and the mobility μ for each of the pixels A and B. A large difference occurs between the pixels A and B.

  On the other hand, when only the threshold correction is performed, as shown in FIG. 9B, although the variation in the drain-source current Ids can be reduced to some extent by the threshold correction, the pixels A and B having the mobility μ A difference in the drain-source current Ids between the pixels A and B due to the variation of each pixel remains.

  Then, by performing both the threshold correction and the mobility correction, as shown in FIG. 9C, the drain between the pixels A and B due to the variation of the threshold voltage Vth and the mobility μ for each of the pixels A and B. -Since the difference between the source currents Ids can be almost eliminated, the luminance variation of the organic EL element 21 does not occur at any gradation, and a display image with good image quality can be obtained.

  Further, the pixel 20 shown in FIG. 2 has the above-described bootstrap function in addition to the threshold correction function and the mobility correction function, so that the following operational effects can be obtained.

  That is, even if the IV characteristic of the organic EL element 21 changes with time, and the source potential Vs of the drive transistor 22 changes accordingly, the bootstrap operation by the storage capacitor 24 causes the gate-source connection of the drive transistor 22. Since the potential Vgs is kept constant, the current flowing through the organic EL element 21 does not change. Therefore, since the light emission luminance of the organic EL element 21 is also kept constant, even if the IV characteristic of the organic EL element 21 changes with time, it is possible to realize an image display that does not cause luminance deterioration associated therewith.

(Problems associated with variations in leakage during the floating period)
By the way, in the organic EL display device 10 having the 2Tr + C pixel circuit, the threshold correction period, that is, the threshold voltage Vth of the driving transistor 22 is detected and held in the holding capacitor 24 as is apparent from the above description of the circuit operation. After the period ends, the writing transistor 23 is turned off. As a result, the gate electrode of the drive transistor 22 enters a floating state.

  At this time, since the gate-source voltage Vgs of the driving transistor 22 is equal to the threshold voltage Vth held in the holding capacitor 24, the driving transistor 22 is in a cut-off state, and the drain-source current Ids is supplied to the driving transistor 22. Does not flow. However, as mentioned earlier, this is an ideal situation.

  In actual operation, even if the gate-source voltage Vgs of the drive transistor 22 is equal to or lower than the threshold voltage Vth, a minute leak current flows through the drive transistor 22. As described above, during the floating period of the gate electrode of the drive transistor 22, a leak current flows through the drive transistor 22, and as shown in FIG. 10, the source potential Vs of the drive transistor 22 rises due to a phenomenon similar to the bootstrap operation. As the source potential Vs increases, the gate potential Vg also increases.

  Here, as is apparent from the above description of the circuit operation, the threshold correction period, which is the detection period of the threshold voltage Vth, is the switching timing (from the low potential Vini to the high potential Vccp of the power supply potential DS supplied to the drive transistor 22 ( Time t3) and timing (time t4) at which the writing transistor 23 is turned off.

  When the threshold correction period (t3-t4) varies, the gate-source voltage Vgs of the driving transistor 22 after the threshold correction period varies, and due to variations in the source potential Vs and the gate potential Vg due to subsequent leakage. Since the variation of the gate-source voltage Vgs becomes large, this variation is recognized as a stripe unevenness at the time of light emission.

  Further, as the resolution of display devices increases and the number of pixels increases, the threshold correction period becomes shorter as the 1H period becomes shorter. As a result, when a leak current flows through the drive transistor 22 with the variation in the threshold voltage Vth, the variation in the gate-source voltage Vgs of the drive transistor 22 due to the leak becomes more significant. As a result, there is a concern that the uneven stripes are further deteriorated and the image quality is lowered.

(Characteristics of this embodiment)
Therefore, in the present embodiment, the final stage buffer (details thereof) of at least one of the write scanning circuit 40 that outputs the scanning line potential (scanning signal) WS and the power supply scanning circuit 50 that outputs the power supply line potential DS. Is a power supply voltage that changes (falls / rises) in a pulse form as a power supply voltage to be described later, and at least the start timing and end timing of the threshold correction period (threshold voltage Vth detection period) at the transition timing of the power supply voltage It is characterized by deciding one side.

[Example]
Hereinafter, a specific example for determining at least one of the start timing and the end timing of the threshold correction period based on the transition timing of the power supply voltage will be described.

Example 1
FIG. 11 is a block diagram illustrating a configuration example of the write scanning circuit 40 according to the first embodiment. As shown in FIG. 11, the write scanning circuit 40 includes a shift register 41, a logic circuit 42, and an output circuit 43 including a plurality of stages of buffers for each pixel row, and drives each pixel 20 of the pixel array unit 30. It is mounted on the display panel 70 as a driving unit.

  A timing signal and a power supply voltage are supplied to the writing scanning circuit 40 from, for example, a flexible cable 90 from a control board 80 provided outside the display panel 70. Specifically, a timing generation circuit 81, a Vdd1 power supply circuit 82, a Vdd2 power supply circuit 83, and the like are provided on the control board 80.

  The timing generation circuit 81 generates a clock pulse CK serving as a reference for the operation of the shift register 41 and a start pulse ST for instructing the start of the shift operation of the shift register 41 and supplies the generated start pulse ST to the shift register 41. An enable pulse EN that determines the pulse width is generated and supplied to the logic circuit 42.

  The Vdd1 power supply circuit 82 generates a DC power supply voltage Vdd1. The power supply voltage Vdd1 is supplied as a positive power supply voltage to the buffers except the shift register 41, the logic circuit 42, and the final stage buffer 431 of the output circuit 43 via the flexible cable 90.

  Although not shown here, a Vss power supply circuit that generates a DC power supply voltage Vss is also provided on the control board 80, and the power supply voltage Vss is shifted from the Vss power supply circuit via the flexible cable 90. The buffers of the register 41, the logic circuit 42, and the output circuit 43 are supplied as their negative power supply voltages.

  The Vdd2 power supply circuit 83 generates a power supply voltage Vdd2 that falls in a pulse form in synchronization with the enable pulse EN, for example. The power supply voltage Vdd2 is preferably set to have a voltage value higher than that of the power supply voltage Vdd1, and is supplied to the last stage buffer 431 of the output circuit 43 as a positive power supply voltage in units of rows. This embodiment is characterized in that the falling of the power supply voltage Vdd2 is pulsed and supplied to the buffer 431 in the final stage.

<Circuit configuration of output circuit>
FIG. 12 is a circuit diagram showing an example of the configuration of the output circuit 43 in a certain pixel row. Here, an output circuit having a two-stage configuration including the last-stage buffer 431 and the preceding-stage buffer 432 is shown as an example, but the present invention is not limited to the two-stage configuration.

  The final stage buffer 431 has a CMOS inverter configuration including a P-channel MOS transistor P11 and an N-channel MOS transistor N11 in which gate electrodes and drain electrodes are connected in common. A power supply voltage Vdd2 falling in a pulse shape is applied to the source electrode of the MOS transistor P11, and a DC power supply voltage Vss is applied to the source electrode of the MOS transistor N11.

  The buffer 432 in the previous stage has a CMOS inverter configuration including a P-channel MOS transistor P12 and an N-channel MOS transistor N12 in which gate electrodes and drain electrodes are connected in common. A DC power supply voltage Vdd1 is applied to the source electrode of the MOS transistor P12, and a DC power supply voltage Vss is applied to the source electrode of the MOS transistor N12.

<Circuit operation of output circuit>
Next, the circuit operation of the output circuit 43 configured as described above will be described with reference to the timing waveform diagram of FIG.

  In the output circuit 43, the shift pulse output from the shift register 41 is input to the preceding buffer 432 via the logic circuit 42 as the input pulse A that rises at time t11 and falls at time t13. The input pulse A passes through the circuit portions of the shift register 41 and the logic circuit 42, causing rounding of the rising and falling waveforms, rising at a slow response speed, and falling at a slow response speed.

  The input pulse A is inverted in polarity by the preceding buffer 432 and further inverted in polarity by the final buffer 431 to become an output pulse B. At this time, the power supply voltage Vdd2 different from the power supply voltage Vdd1 of the previous stage is supplied to the final stage buffer 431 from the Vdd2 power supply circuit 83 provided on the control board 80 via the flexible gable 90. Applied.

  The power supply voltage Vdd2 has a pulse-like falling characteristic and falls sharply at time t12. Since the power supply voltage Vdd2 does not pass through any circuit portion on the display panel 70, no delay occurs and the falling waveform is steep. Therefore, like the input pulse A, the shift register 41 and the logic circuit The falling waveform does not become rounded by passing through the 42 circuit portions.

  Since the power supply voltage Vdd2 having a steep falling waveform is used as the power supply voltage on the positive side of the final stage buffer 431, the falling speed of the output pulse B is determined by the falling speed of the power supply voltage Vdd2. The falling waveform is steep. Since the rising edge of the output pulse B is determined by the rising edge of the input pulse A, the rising waveform is gentle. The output pulse B is applied as a scanning line potential (scanning signal) WS to the gate electrode of the writing transistor 23 in each pixel 20 of the corresponding pixel row.

  As described above, the positive power supply of the final stage buffer 431 of the output circuit 43 in the write scanning circuit 40 is separated from the circuit part of the previous stage, and the power supply voltage is pulsed (rectangular wave) in synchronization with the enable pulse EN, for example. Since the output voltage B, that is, the scanning line potential WS is lowered at the fall of the power supply voltage Vdd2 by using the power supply voltage Vdd2 that falls on the power supply voltage Vdd2, the power supply voltage Vdd2 falls sharply. The response speed of the fall of the scanning line potential WS can be made faster than when the scanning line potential WS is lowered at the falling edge of the input pulse A.

  As described above, the threshold correction period is defined by the rising timing of the power supply line potential DS from the low potential Vini to the high potential Vccp and the falling timing of the scanning line potential (scanning signal) WS. The variation in the threshold correction period is caused by the variation in each stage corresponding to the pixel rows of the writing scanning circuit 40 and the power supply scanning circuit 50 and the variation due to the degree of transient rounding.

  Therefore, at least by increasing the response speed of the fall of the scanning line potential WS, it is possible to suppress the variation of the write scanning circuit 40 for each stage of the threshold correction period by the increase in the response speed. Variation in the gate-source voltage Vgs of the drive transistor 22 due to the above can be suppressed.

  As a result, unevenness due to variations in the threshold correction period can be suppressed, so that the display image can be improved in image quality, and the 1H period becomes shorter as the display device becomes higher in definition. Even if the period is shortened, this can be dealt with, that is, unevenness due to variations in the threshold correction period can be suppressed.

  Incidentally, when the configuration in which the DC power supply voltage Vdd1 is supplied to the positive power supply of the final stage buffer 431 without separating the positive power supply of the final stage buffer 431 from the circuit section on the previous stage side, the output pulse B rises. The falling speed is governed by the size of the N-channel MOS transistor N11. However, since the write scanning circuit 40 is arranged in a narrow space, there is a limit in increasing the size of the N-channel MOS transistor N11, and thus there is a limit in increasing the falling speed τ of the output pulse B. For example, τ = about 200 ns.

  On the other hand, as the power supply voltage Vdd2 applied to the positive power supply of the final stage buffer 431, the falling speed τ can be set to 100 ns or less. The falling speed of the output pulse B is not limited by the size of the N-channel MOS transistor N11, but becomes the falling speed of the pulsed power supply voltage Vdd2, so that the falling speed of the output pulse B is also 100 ns. The speed can be increased to the following.

(Example 2)
FIG. 14 is a block diagram illustrating a configuration example of the power supply scanning circuit 50 according to the first embodiment. In the drawing, the same parts as those in FIG. 11 are denoted by the same reference numerals. As shown in FIG. 14, the power supply scanning circuit 50 includes a shift register 51, a logic circuit 52, and an output circuit 53 including a plurality of stages of buffers for each pixel row, and each pixel 20 of the pixel array unit 30 is arranged. It is mounted on the display panel 70 as a drive unit for driving.

  A timing signal and a power supply voltage are supplied to the power supply scanning circuit 50 from, for example, a flexible cable 90 from a control board 80 provided outside the display panel 70. Specifically, on the control board 80, in addition to the timing generation circuit 81 and the Vdd1 power supply circuit 82 described above, a Vccp power supply circuit 84, a Vini power supply circuit 85, and the like are provided.

  The timing generation circuit 81 generates a clock pulse CK serving as a reference for the operation of the shift register 51 and a start pulse ST for instructing the start of the shift operation of the shift register 51, supplies the generated clock pulse CK to the shift register 51, and supplies the power supply line potential. An enable pulse EN that determines the pulse width of DS is generated and supplied to the logic circuit 52.

  The Vdd1 power supply circuit 82 generates a DC power supply voltage Vdd1. This power supply voltage Vdd1 is supplied as a power supply voltage on the positive side to the buffers other than the buffer 531 at the final stage of the shift register 51, the logic circuit 52, and the output circuit 53 via the flexible cable 90.

  Although not shown here, a Vss power supply circuit that generates a DC power supply voltage Vss is also provided on the control board 80, and the power supply voltage Vss is shifted from the Vss power supply circuit via the flexible cable 90. The negative side power supply voltages are supplied to the buffers except the final stage buffer 531 of the register 51, the logic circuit 52, and the output circuit 53.

  The Vccp power supply circuit 84 generates a power supply voltage (first potential) Vccp that rises in a pulse form in synchronization with the enable pulse EN, for example. The power supply voltage Vccp is set to have a voltage value higher than that of the power supply voltage Vdd1, and is supplied to the final stage buffer 531 of the output circuit 53 as a positive power supply voltage in units of rows. This embodiment is characterized in that the rising of the power supply voltage Vccp is pulsed and supplied to the buffer 531 at the final stage.

  The Vini power supply circuit 85 generates a power supply voltage (second potential) Vini set to a potential lower than the offset voltage Vofs, for example, a potential lower than Vofs−Vth, preferably sufficiently lower than Vofs−Vth, The negative power supply voltage is supplied to the buffer 531 at the final stage of the output circuit 53 in common for each row.

<Circuit configuration of output circuit>
FIG. 15 is a circuit diagram showing an example of the configuration of the output circuit 53 of a certain pixel row. Here, an output circuit having a two-stage configuration including the last-stage buffer 531 and the preceding-stage buffer 532 is shown as an example, but the present invention is not limited to the two-stage configuration.

  The final stage buffer 531 has a CMOS inverter configuration including a P channel MOS transistor P21 and an N channel MOS transistor N211 in which gate electrodes and drain electrodes are connected in common. A power supply voltage Vccp that rises in a pulse shape is applied to the source electrode of the MOS transistor P21, and a DC power supply voltage Vini is applied to the source electrode of the MOS transistor N11.

  The buffer 532 in the previous stage has a CMOS inverter configuration including a P-channel MOS transistor P22 and an N-channel MOS transistor N22 in which gate electrodes and drain electrodes are connected in common. A DC power supply voltage Vdd1 is applied to the source electrode of the MOS transistor P22, and a DC power supply voltage Vss is applied to the source electrode of the MOS transistor N22.

<Circuit operation of output circuit>
Next, the circuit operation of the output circuit 53 configured as described above will be described with reference to the timing waveform diagram of FIG.

  In the output circuit 53, the shift pulse output from the shift register 51 is input to the preceding buffer 532 via the logic circuit 52 as the input pulse C that falls at time t21 and rises at time t23. When the input pulse C passes through the circuit portions of the shift register 51 and the logic circuit 52, the falling and rising waveforms are rounded, fall at a slow response speed, and rise at a slow response speed.

  The input pulse C is inverted in polarity by the preceding buffer 532 and further inverted in polarity by the final buffer 531 to become an output pulse D. At this time, the final stage buffer 531 has a power supply voltage Vccp as its positive power supply voltage and a power supply voltage Vini as its negative power supply voltage, and a Vccp power supply circuit 84 and a Vini power supply circuit 85 provided on the control board 80. To the flexible gable 90.

  Here, the power supply voltage Vccp has a pulse-like rising characteristic and rises sharply at time t22. Since the power supply voltage Vccp does not pass through any circuit portion on the display panel 70, there is no delay and the rising waveform is steep. Therefore, like the input pulse C, the shift register 51 and the logic circuit 52 The rising waveform does not become rounded by passing through the circuit portion.

  Since the power supply voltage Vccp having a steep rising waveform is used as the power supply voltage on the positive side of the final stage buffer 531, the rising speed of the output pulse D is determined by the rising speed of the power supply voltage Vccp. It becomes steep. Note that the low potential of the output pulse D is the power supply voltage Vini. This output pulse D is applied as the power supply line potential DS to the drain electrode of the drive transistor 22 in each pixel 20 of the corresponding pixel row.

  As described above, the positive power supply of the final stage buffer 531 of the output circuit 53 in the power supply scanning circuit 50 is separated from the circuit part of the previous stage, and the power supply voltage is pulsed (rectangular wave) in synchronization with the enable pulse EN, for example. Using the power supply voltage Vccp that rises at (), the output pulse D, that is, the power supply line potential DS is raised from the low potential Vini to the high potential Vccp at the rise of the power supply voltage Vccp, so that the rise of the power supply voltage Vccp is steep. Therefore, the response speed of the rising of the power supply line potential DS can be made faster than the case where the positive power supply is made common to the preceding stage and the power supply line potential DS is raised at the rising edge of the input pulse C.

  As described above, the threshold correction period is defined by the rising timing of the power supply line potential DS from the low potential Vini to the high potential Vccp and the falling timing of the scanning line potential (scanning signal) WS. By increasing the response speed of the rise of the power supply line potential DS, it is possible to suppress variations among the stages of the power supply scanning circuit 50 during the threshold correction period by the increase in the response speed. Variations in the gate-source voltage Vgs of the drive transistor 22 can be suppressed.

  As a result, unevenness due to variations in the threshold correction period can be suppressed, so that the display image can be improved in image quality, and the 1H period becomes shorter as the display device becomes higher in definition. Even if the period is shortened, this can be dealt with, that is, unevenness due to variations in the threshold correction period can be suppressed.

  In each of the embodiments described above, the case where positive logic output pulses B and D that are active at the “H” level are generated as the scanning line potential WS and the power supply line potential DS has been described as an example. The present invention can be similarly applied to the case of generating negative logic output pulses BX and DX that become active at the “level”. In this case, the negative power supply of the final stage buffers 431 and 531 of the output circuits 43 and 53 is separated from other circuit portions, and the power supply voltage Vss2 rising in a pulse shape and the power supply voltage Vini falling in a pulse shape are used as the power supply voltage. By using it, the waveforms of the rising edge of the negative logic output pulse BX and the falling edge of the output pulse DX can be made steep, and variations in the threshold correction period determined by these transition timings can be suppressed.

  In the first embodiment, the present invention is applied to the write scanning circuit 40 to increase the response speed of the fall of the scanning line potential WS. In the second embodiment, the present invention is applied to the power supply scanning circuit 50. Although the case where the response speed of the rising of the power supply line potential DS is increased has been described as an example, the present invention is applied to both the write scanning circuit 40 and the power supply scanning circuit 50 to decrease the scanning line potential WS. Of course, the response speed of the rising of the power supply line potential DS may be increased.

  In this way, threshold response correction is achieved by increasing the response speeds of the fall of the scanning line potential WS and the rise of the power supply line potential DS and determining the start timing and end timing of the threshold correction period at these transition timings. Since variation in the period can be more reliably suppressed, unevenness due to the variation can be suppressed, and thus higher quality of the display image can be achieved.

[Modification]
The above embodiment has been described on the assumption that the threshold correction, signal writing, and mobility correction operations are executed within the 1H period. However, in order to sufficiently secure the threshold correction period, as shown in FIG. Applying the present invention to an organic EL display device that adopts a so-called division threshold correction configuration in which the threshold correction period is divided and set over a plurality of Hs, the fall of the scanning line potential WS that determines the first threshold correction period, and power supply The same effect can be obtained even if the response speed of at least one of the rises of the line potential DS is increased.

  In the above embodiment, the case where the present invention is applied to an organic EL display device using an organic EL element as the electro-optical element of the pixel circuit 20 has been described as an example. However, the present invention is not limited to this application example. In addition, the present invention can be applied to all display devices using current-driven electro-optic elements (light-emitting elements) whose light emission luminance changes according to the value of current flowing through the device.

[Application example]
As an example, the display device according to the present invention described above is applied to various electronic devices shown in FIGS. 18 to 22, for example, electronic devices such as digital cameras, notebook personal computers, mobile terminal devices such as mobile phones, and video cameras. The input video signal or the video signal generated in the electronic device can be applied to a display device of an electronic device in any field that displays an image or a video.

  As described above, by using the display device according to the present invention as a display device for electronic devices in all fields, the display device according to the present invention can be applied to the threshold voltage Vth of the driving transistor and the movement as is apparent from the description of the above-described embodiment. Since it is possible to surely correct the variation for each pixel of the degree μ, there is an advantage that high-quality image display can be performed in various electronic devices.

  Note that the display device according to the present invention includes a module-shaped one having a sealed configuration. For example, a display module formed by being affixed to an opposing portion such as transparent glass on the pixel array portion 30 is applicable. The transparent facing portion may be provided with a color filter, a protective film, and the like, and further, the above-described light shielding film. Note that the display module may be provided with a circuit unit for inputting / outputting a signal and the like from the outside to the pixel array unit, an FPC (flexible printed circuit), and the like.

  Specific examples of electronic devices to which the present invention is applied will be described below.

  FIG. 18 is a perspective view showing the appearance of a television to which the present invention is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to the present invention as the video display screen unit 101.

  19A and 19B are perspective views showing an external appearance of a digital camera to which the present invention is applied. FIG. 19A is a perspective view seen from the front side, and FIG. 19B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present invention as the display unit 112.

  FIG. 20 is a perspective view showing an external appearance of a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like, and the display device according to the present invention is used as the display unit 123. It is produced by this.

  FIG. 21 is a perspective view showing the appearance of a video camera to which the present invention is applied. The video camera according to this application example includes a main body part 131, a lens 132 for photographing an object on the side facing forward, a start / stop switch 133 at the time of photographing, a display part 134, etc., and the display part 134 according to the present invention. It is manufactured by using a display device.

  22A and 22B are views showing the appearance of a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which FIG. 22A is a front view in an opened state, FIG. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper casing 141, a lower casing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. 144 and the sub-display 145 are manufactured by using the display device according to the present invention.

1 is a system configuration diagram illustrating an outline of a configuration of an organic EL display device according to an embodiment of the present invention. It is a circuit diagram which shows the specific structural example of a pixel (pixel circuit). It is sectional drawing which shows an example of the cross-sectional structure of a pixel. FIG. 6 is a timing waveform diagram for explaining a basic circuit operation of an organic EL display device in which pixels having a 2Tr + C pixel configuration are two-dimensionally arranged. FIG. 10 is an explanatory diagram (part 1) of a basic circuit operation of a pixel circuit having a 2Tr + C pixel configuration; FIG. 10 is an explanatory diagram (part 2) of a basic circuit operation of a pixel circuit having a 2Tr + C pixel configuration. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the threshold voltage Vth of a drive transistor. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the mobility (mu) of a drive transistor. FIG. 10 is a characteristic diagram for explaining the relationship between the signal voltage Vsig of the video signal and the drain-source current Ids of the drive transistor depending on whether threshold correction and mobility correction are performed. FIG. 10 is a timing waveform diagram for explaining a problem associated with a variation in leak amount during a floating period in actual operation. FIG. 3 is a block diagram illustrating a configuration example of a write scanning circuit according to the first embodiment. It is a circuit diagram which shows an example of a structure of the output circuit in a writing scanning circuit. FIG. 6 is a timing waveform diagram for explaining the circuit operation of the output circuit in the writing scanning circuit. FIG. 6 is a block diagram illustrating a configuration example of a power supply scanning circuit according to a second embodiment. It is a circuit diagram which shows an example of a structure of the output circuit in a power supply scanning circuit. FIG. 6 is a timing waveform diagram for explaining the circuit operation of the output circuit in the power supply scanning circuit. It is a timing waveform diagram in the case of division threshold correction. It is a perspective view which shows the external appearance of the television with which this invention is applied. It is a perspective view which shows the external appearance of the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view illustrating an appearance of a notebook personal computer to which the present invention is applied. It is a perspective view which shows the external appearance of the video camera to which this invention is applied. It is a figure which shows the external appearance of the mobile telephone to which this invention is applied, (A) is the front view in the open state, (B) is the side view, (C) is the front view in the closed state, (D ) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Organic EL display device, 20 ... Pixel (pixel circuit), 21 ... Organic EL element, 22 ... Drive transistor, 23 ... Write transistor, 24 ... Retention capacity, 25 ... Auxiliary capacity, 30 ... Pixel array part, 31 (31 -1 to 31-m) ... scanning lines, 32 (32 to 1 to 32-m) ... power supply lines, 33 (33-1 to 33-n) ... signal lines, 34 ... common power supply lines, 40 ... write Scanning circuit 50 ... Power supply scanning circuit 60 ... Horizontal drive circuit 70 ... Display panel 80 ... Control board 90 ... Flexible cable

Claims (6)

An electro-optical element; a writing transistor for writing a video signal; a holding capacitor for holding the video signal written by the writing transistor; and driving the electro-optical element based on the video signal held in the holding capacitor. A pixel array unit in which pixels including drive transistors are arranged in a matrix;
A first potential and a second potential lower than the first potential are selectively supplied to a power supply line that is wired for each pixel row of the pixel array portion and supplies a current to the driving transistor. A first scanning circuit having a switching timing from two potentials to the first potential as a start timing of a detection period for detecting a threshold voltage of the driving transistor;
By driving the write transistor for each pixel row of the pixel array unit, the write transistor is made conductive during a period in which the second potential is selected while selecting each pixel of the pixel array unit in a row unit. And a second scanning circuit that causes the write transistor to transition to a non-conducting state after switching from the second potential to the first potential, and uses the transition timing as the end timing of the detection period,
At least one of the first scanning circuit and the second scanning circuit uses a power supply voltage that changes in a pulse shape as the power supply voltage of the final stage buffer, and the start timing and end timing of the detection period at the transition timing of the power supply voltage. A display device characterized by determining at least one of them. The first scanning circuit has a final stage buffer in which a power source is separated from a circuit portion on the previous stage side, and a power supply voltage that makes a pulse transition from the second potential to the first potential as a power supply voltage of the final stage buffer The display device according to claim 1, wherein the start timing of the detection period is determined by the transition timing of the power supply voltage. The second scanning circuit includes a final stage buffer in which a power source is separated from a circuit portion on the previous stage side, and the power supply voltage of the final stage buffer is changed from a potential that makes the write transistor conductive to a potential that makes the write transistor nonconductive. 2. The display device according to claim 1, wherein the end timing of the detection period is determined based on a transition timing of the power supply voltage using a power supply voltage that transitions in a pulse shape. The first scanning circuit has a final stage buffer in which a power source is separated from a circuit portion on the previous stage side, and a power supply voltage that makes a pulse transition from the second potential to the first potential as a power supply voltage of the final stage buffer Is used to determine the start timing of the detection period at the transition timing of the power supply voltage,
The second scanning circuit includes a final stage buffer in which a power source is separated from a circuit portion on the previous stage side, and the power supply voltage of the final stage buffer is changed from a potential that makes the write transistor conductive to a potential that makes the write transistor nonconductive. 2. The display device according to claim 1, wherein the end timing of the detection period is determined based on a transition timing of the power supply voltage using a power supply voltage that transitions in a pulse shape. An electro-optical element; a writing transistor for writing a video signal; a holding capacitor for holding the video signal written by the writing transistor; and driving the electro-optical element based on the video signal held in the holding capacitor. A pixel array unit in which pixels including drive transistors are arranged in a matrix;
A first scanning circuit that is arranged for each pixel row of the pixel array section and selectively supplies a first potential and a second potential lower than the first potential to a power supply line that supplies a current to the driving transistor. When,
A driving method of a display device comprising: a second scanning circuit that selects each pixel of the pixel array unit in units of rows by driving the write transistor for each pixel row of the pixel array unit,
The writing transistor is turned on during the period in which the second potential is selected, and then a detection period is started in which the threshold voltage of the driving transistor is detected by switching from the second potential to the first potential. The write transistor is turned off to end the detection period,
A power supply voltage that changes in a pulse shape is used as a power supply voltage of at least one final stage buffer of the first scanning circuit and the second scanning circuit, and at least a start timing and an end timing of the detection period at the transition timing of the power supply voltage. A method for driving a display device, characterized in that one is determined. An electro-optical element; a writing transistor for writing a video signal; a holding capacitor for holding the video signal written by the writing transistor; and driving the electro-optical element based on the video signal held in the holding capacitor. A pixel array unit in which pixels including drive transistors are arranged in a matrix;
A first potential and a second potential lower than the first potential are selectively supplied to a power supply line that is wired for each pixel row of the pixel array portion and supplies a current to the driving transistor. A first scanning circuit having a switching timing from two potentials to the first potential as a start timing of a detection period for detecting a threshold voltage of the driving transistor;
By driving the write transistor for each pixel row of the pixel array unit, each pixel of the pixel array unit is selected in units of rows, and the write transistor that is in a conductive state during the selection period of the second potential is selected in the first row. A second scanning circuit that transitions to a non-conduction state after switching from two potentials to the first potential, and uses the transition timing as the end timing of the detection period;
At least one of the first scanning circuit and the second scanning circuit uses a power supply voltage that changes in a pulse shape as the power supply voltage of the final stage buffer, and the start timing and end timing of the detection period at the transition timing of the power supply voltage. An electronic device comprising: a display device that determines at least one of them.

Images