JP2009145531A - Display, driving method for display, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set a correction time for executing mobility correction to the optimum correction time in response to a signal voltage of an image signal, and to surely carry out desired mobility correction processing. <P>SOLUTION: A capacitive element 87 is added to an electric power source supply line 86 for supplying an electric power source potential Vddws generated in an electric power source supply part 83, from the electric power source supply part 83 to the final stage of buffer 432 in an output circuit 43, as the positive side electric power source potential thereof, and the electric power source potential Vddws after capacity-coupled and a potential WSL of a scanning line 31-i are restrained from getting low caused by connecting the electric power source supply line 86 to the scanning line 31-i via a Pch transistor of the buffer 432, when the electric power source supply line 86 is under a floating state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device, a driving method of the display device, and an electronic apparatus, and more particularly, a flat-type (flat panel type) display device in which pixels including electro-optical elements are two-dimensionally arranged in a matrix (matrix shape), and the display The present invention relates to a device driving method and an electronic apparatus having the display device.

  In recent years, in the field of display devices that perform image display, flat display devices in which pixels (pixel circuits) including light emitting elements are arranged in a matrix are rapidly spreading. As a flat display device, as a light emitting element of a pixel, a so-called current-driven electro-optical element whose light emission luminance changes according to a current value flowing through the device, for example, a phenomenon of emitting light when an electric field is applied to an organic thin film is used. An organic EL display device using an organic EL (Electro Luminescence) element has been developed and commercialized.

  The organic EL display device has the following features. That is, since the organic EL element can be driven with an applied voltage of 10 V or less, the power consumption is low. Since the organic EL element is a self-luminous element, image visibility is higher than that of a liquid crystal display device that displays an image by controlling the light intensity from a light source (backlight) with a liquid crystal for each pixel. In addition, since an illumination member such as a backlight is not required, it is easy to reduce the weight and thickness. Furthermore, since the response speed of the organic EL element is as high as about several μsec, an afterimage at the time of displaying a moving image does not occur.

  As in the liquid crystal display device, the organic EL display device can adopt a simple (passive) matrix method and an active matrix method as its driving method. However, although the simple matrix display device has a simple structure, the light-emission period of the electro-optic element decreases with an increase in the number of scanning lines (that is, the number of pixels), thereby realizing a large-sized and high-definition display device. There are problems such as difficult.

  Therefore, in recent years, an active element in which an electric current flowing through an electro-optic element is controlled by an active element provided in the same pixel as the electro-optic element, for example, an insulated gate field effect transistor (generally, a TFT (Thin Film Transistor)). Matrix display devices have been actively developed. An active matrix display device can easily realize a large-sized and high-definition display device because the electro-optic element continues to emit light over a period of one frame (one field).

  By the way, it is generally known that the IV characteristic (current-voltage characteristic) of the organic EL element is deteriorated with time (so-called deterioration with time). In a pixel circuit using an N-channel TFT as a transistor for driving an organic EL element with current (hereinafter referred to as “driving transistor”), the organic EL element is connected to the source electrode side of the driving transistor. In addition, when the IV characteristic of the organic EL element deteriorates with time, the gate-source voltage Vgs of the driving transistor changes, and as a result, the emission luminance of the organic EL element also changes.

  This will be described more specifically. The source potential of the drive transistor is determined by the operating points of the drive transistor and the organic EL element. When the IV characteristic of the organic EL element deteriorates, the operating point of the driving transistor and the organic EL element fluctuates. Therefore, even if the same voltage is applied to the gate electrode of the driving transistor, the source potential of the driving transistor is Change. As a result, since the source-gate voltage Vgs of the drive transistor changes, the value of the current flowing through the drive transistor changes. As a result, since the value of the current flowing through the organic EL element also changes, the light emission luminance of the organic EL element changes.

  In addition, in a pixel circuit using a polysilicon TFT, in addition to the deterioration over time of the IV characteristics of the organic EL element, the threshold voltage Vth of the driving transistor and the mobility of the semiconductor thin film that constitutes the channel of the driving transistor (hereinafter referred to as the following) The μ changes over time, and the transistor characteristics of the threshold voltage Vth and the mobility μ vary from pixel to pixel due to variations in manufacturing processes (transistor characteristics of each pixel vary). There is).

  If the threshold voltage Vth and mobility μ of the driving transistor differ from pixel to pixel, the current value flowing through the driving transistor varies from pixel to pixel, so even if the same voltage is applied between the pixels to the gate electrode of the driving transistor, The light emission luminance of the organic EL element varies among pixels, and as a result, the uniformity of the screen is impaired.

  Therefore, even if the IV characteristic of the organic EL element deteriorates with time, or the threshold voltage Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element is not affected by those effects. In order to keep constant, the compensation function for the characteristic variation of the organic EL element, the correction for the variation of the threshold voltage Vth of the driving transistor (hereinafter referred to as “threshold correction”), the mobility μ of the driving transistor Each pixel circuit is provided with a correction function for correction of fluctuations (hereinafter referred to as “mobility correction”) (see, for example, Patent Document 1).

  As described above, each of the pixel circuits has the compensation function for the characteristic variation of the organic EL element and the correction function for the threshold voltage Vth and the mobility μ of the driving transistor, so that the IV characteristic of the organic EL element is improved. Even if the threshold voltage Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element can be kept constant without being affected by the deterioration. The display quality of the display device can be improved.

JP 2006-133542 A

  Among the various correction functions described above, the correction time for performing the mobility correction is determined by the write pulse that is a scanning signal applied to the gate electrode of the writing transistor for writing the video signal in synchronization with the vertical scanning. In order to reliably realize a desired mobility correction process corresponding to the signal level of the video signal (hereinafter sometimes referred to as “signal voltage”), the correction time for performing the mobility correction is set to It is necessary to set an optimal correction time according to the signal voltage (details will be described later).

  Therefore, the present invention sets a correction time for performing mobility correction to an optimal correction time according to the signal voltage of the video signal, and allows the desired mobility correction processing to be reliably executed, and the display device An object of the present invention is to provide a driving method and an electronic device using the display device.

In order to achieve the above object, the present invention provides:
An electro-optic element;
A writing transistor in which a gate electrode is connected to the scanning line and one electrode is connected to a signal line to which a video signal is supplied;
A driving transistor in which a gate electrode is connected to the other electrode of the writing transistor, one electrode is connected to a power supply line, and the other electrode is connected to an anode electrode of the electro-optic element;
A pixel array unit in which pixels having a storage capacitor in which one electrode is connected to the gate electrode of the driving transistor and the other electrode is connected to the other electrode of the driving transistor; and
A power supply scanning circuit for selectively supplying a first power supply potential and a second power supply potential lower than the first power supply potential to the power supply line;
A write scanning circuit having a final stage buffer in which a circuit part on the front stage side and a power supply line are separated, and writing the video signal by the write transistor by giving a write pulse output from the final stage buffer to the write transistor And
In a display device that executes mobility correction processing that applies negative feedback to the gate input side of the driving transistor with a correction amount corresponding to the current flowing through the driving transistor, in parallel with the video signal writing processing by the writing transistor,
The write scanning circuit comprising:
A power supply unit that supplies a power supply potential that changes in a waveform determined by a predetermined time constant to the final stage buffer when the write pulse is transitioned from an active state to an inactive state;
The power supply unit includes a capacitor added to a power supply line that supplies the power supply potential to the final stage buffer.

  In the display device having the above-described configuration and the electronic apparatus having the display device, when the write pulse is changed from the active state to the inactive state, the power supply unit changes in a waveform determined by a predetermined time constant with respect to the final stage buffer. By supplying the power supply potential, the write pulse transitions from the active state to the inactive state with a waveform determined by the time constant. Here, by setting the waveform determined by the time constant to a waveform corresponding to the signal level of the video signal, the optimum correction time for mobility correction can be set to correspond to the signal level of the video signal. As a result, the mobility correction processing can be reliably executed over the entire level range (all gradations) of the video signal from the black level to the white level, that is, the variation of the mobility of the driving transistor from pixel to pixel can be reliably corrected. Can do.

  In the write scan circuit, a capacitor is added to the power supply line that supplies the power supply potential from the power supply unit to the final stage buffer, whereby the power supply line is connected to the scan line via the final stage buffer. A decrease in power supply potential caused by capacitive coupling can be suppressed to a smaller value than when no capacitive element is added to the power supply line. Specifically, when the capacitance value of the capacitive element is sufficiently larger than the parasitic capacitance of the power supply line or the scanning line, the parasitic capacitance of the scanning line can be ignored. The power supply potential can be set substantially equal to the original power supply potential. As a result, even if there is a difference in the parasitic capacitance of the scanning line in each video line (pixel row), there is no difference in the potential of the scanning line (the peak value of the write pulse), and therefore there is a variation in brightness in each display pattern. Therefore, the effect of improving the display quality (image quality) associated with the mobility correction process can be sufficiently obtained.

  According to the present invention, since the optimal correction time for mobility correction can be set so as to correspond to the signal level of the video signal, variation in mobility for each pixel can be corrected more reliably. Also, even if there is a difference in the parasitic capacitance of the scanning line in each video line, there is no difference in the potential of the scanning line, and the display quality improvement effect associated with the mobility correction process can be sufficiently obtained. A display image with high image quality can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[System configuration]
FIG. 1 is a system configuration diagram showing an outline of the configuration of an active matrix display device to which the present invention is applied.

  Here, as an example, a current-driven electro-optic element whose emission luminance changes in accordance with the value of current flowing through the device, for example, an organic EL element (organic electroluminescence element) is used as a light emitting element of a pixel (pixel circuit). The case of a matrix type organic EL display device will be described as an example.

  As shown in FIG. 1, the organic EL display device 10 includes a plurality of pixels (PXLC) 20 including light emitting elements, a pixel array unit 30 in which the pixels 20 are two-dimensionally arranged in a matrix, and the pixel array unit 30. And a driving unit that drives each pixel 20. For example, a writing scanning circuit 40, a power supply scanning circuit 50, and a signal output circuit 60 are provided as driving units for driving the pixels 20.

  Here, when the organic EL display device 10 is a display device for color display, one pixel is composed of a plurality of sub-pixels (sub-pixels), and this sub-pixel corresponds to the pixel 20. More specifically, in a display device for color display, one pixel includes a sub-pixel that emits red light (R), a sub-pixel that emits green light (G), and a sub-pixel that emits blue light (B). It consists of three sub-pixels of a pixel.

  However, one pixel is not limited to the combination of RGB three primary color subpixels, and one pixel may be configured by adding one or more color subpixels to the three primary color subpixels. Is possible. More specifically, for example, at least one sub-pixel that emits white light (W) is added to improve luminance to form one pixel, or at least one that emits complementary color light to expand the color reproduction range. It is also possible to configure one pixel by adding subpixels.

  The pixel array unit 30 supplies power to the scanning lines 31-1 to 31-m along the first direction (left-right direction / horizontal direction in FIG. 1) with respect to the arrangement of the pixels 20 in m rows and n columns. Lines 32-1 to 32-m are wired for each pixel row, and signal lines 33-1 to 33-33 are arranged along a second direction (vertical direction / vertical direction in FIG. 1) orthogonal to the first direction. n is wired for each pixel column.

  The scanning lines 31-1 to 31 -m are connected to the output ends of the corresponding rows of the writing scanning circuit 40, respectively. The power supply lines 32-1 to 32-m are connected to the output terminals of the corresponding rows of the power supply scanning circuit 50, respectively. The signal lines 33-1 to 33-n are connected to the output ends of the corresponding columns of the signal output circuit 60, respectively.

  The pixel array unit 30 is usually formed on a transparent insulating substrate such as a glass substrate. Thereby, the organic EL display device 10 has a flat panel structure. The drive circuit for each pixel 20 in the pixel array section 30 can be formed using an amorphous silicon TFT or a low-temperature polysilicon TFT. When the low-temperature polysilicon TFT is used, the write scanning circuit 40, the power supply scanning circuit 50, and the signal output circuit 60 can also be mounted on the display panel (substrate) 70 that forms the pixel array unit 30.

  The write scanning circuit 40 is configured by a shift register or the like that sequentially shifts (transfers) the start pulse sp in synchronization with the clock pulse ck, and the scanning line 31-is used for writing the video signal to each pixel 20 of the pixel array unit 30. By sequentially supplying write pulses (scanning signals) WS1 to WSm to 1-31 to m, each pixel 20 of the pixel array unit 30 is sequentially scanned (line sequential scanning) in units of rows. The specific configuration will be described later.

  The power supply scanning circuit 50 includes a shift register that sequentially shifts the start pulse sp in synchronization with the clock pulse ck, and the first power supply potential Vccp and the first power supply potential Vccp in synchronization with the line sequential scanning by the writing scanning circuit 40. The power supply line potentials DS1 to DSm that are switched at the second power supply potential Vini lower than the power supply potential Vccp are supplied to the power supply lines 32-1 to 32-m, thereby controlling the light emission / non-light emission of the pixel 20. A drive current is supplied to the organic EL element which is a light emitting element.

  The signal output circuit 60 has either a signal voltage (hereinafter also simply referred to as “signal voltage”) Vsig or a reference potential Vofs of a video signal corresponding to luminance information supplied from a signal supply source (not shown). Either one is selected as appropriate, and writing is performed, for example, in units of rows to each pixel 20 of the pixel array unit 30 via the signal lines 33-1 to 33-n. That is, the signal output circuit 60 adopts a line-sequential writing drive mode in which the signal voltage Vsig of the video signal is written in units of rows.

  Here, the reference potential Vofs is a reference potential (for example, a potential corresponding to the black level) of the signal voltage Vsig of the video signal corresponding to the luminance information. The second power supply potential Vini is lower than the reference potential Vofs, for example, a potential lower than Vofs−Vth, preferably a potential sufficiently lower than Vofs−Vth when the threshold voltage of the driving transistor 22 is Vth. Is set.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating a specific configuration example of the pixel (pixel circuit) 20.

  As shown in FIG. 2, the pixel 20 includes a current-driven electro-optical element whose emission luminance changes according to a current value flowing through the device, for example, an organic EL element 21, and a drive circuit that drives the organic EL element 21. It is constituted by. The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all the pixels 20 (so-called solid wiring).

  The drive circuit that drives the organic EL element 21 includes a drive transistor 22, a write transistor 23, and a storage capacitor 24. Here, N-channel TFTs are used as the drive transistor 22 and the write transistor 23. However, the combination of conductivity types of the drive transistor 22 and the write transistor 23 is merely an example, and is not limited to these combinations.

  Note that when an N-channel TFT is used as the driving transistor 22 and the writing transistor 23, an amorphous silicon (a-Si) process can be used. By using the a-Si process, it is possible to reduce the cost of the substrate on which the TFT is formed, and thus to reduce the cost of the organic EL display device 10. Further, when the drive transistor 22 and the write transistor 23 have the same conductivity type, both the transistors 22 and 23 can be formed by the same process, which can contribute to cost reduction.

  The drive transistor 22 has one electrode (source / drain electrode) connected to the anode electrode of the organic EL element 21 and the other electrode (drain / source electrode) connected to the power supply line 32 (32-1 to 32-m). It is connected.

  The write transistor 23 has a gate electrode connected to the scanning line 31 (31-1 to 31-m), one electrode (source / drain electrode) connected to the signal line 33 (33-1 to 33-n), The other electrode (drain / source electrode) is connected to the gate electrode of the drive transistor 22.

  In the drive transistor 22 and the write transistor 23, one electrode refers to a metal wiring electrically connected to the source / drain region, and the other electrode refers to a metal wiring electrically connected to the drain / source region. Say. Further, depending on the potential relationship between one electrode and the other electrode, if one electrode becomes a source electrode, it becomes a drain electrode, and if the other electrode also becomes a drain electrode, it becomes a source electrode.

  The storage capacitor 24 has one electrode connected to the gate electrode of the drive transistor 22 and the other electrode connected to the other electrode of the drive transistor 22 and the anode electrode of the organic EL element 21.

  The drive circuit of the organic EL element 21 is not limited to a circuit configuration including two transistors, the drive transistor 22 and the write transistor 23, and one capacitor of the storage capacitor 24. The other electrode is connected to the anode electrode of the organic EL element 21 at a fixed potential, so that the capacity shortage of the organic EL element 21 is compensated for, and the auxiliary capacity for increasing the video signal write gain to the holding capacity 24 It is also possible to adopt a circuit configuration provided as necessary.

  In the pixel 20 having the above-described configuration, the writing transistor 23 is turned on in response to the high-level scanning signal WS applied to the gate electrode from the writing scanning circuit 40 through the scanning line 31, thereby outputting a signal through the signal line 33. The signal voltage Vsig or the reference potential Vofs of the video signal corresponding to the luminance information supplied from the circuit 60 is sampled and written into the pixel 20. The written signal voltage Vsig or reference potential Vofs is applied to the gate electrode of the driving transistor 22 and held in the holding capacitor 24.

  When the potential DS of the power supply line 32 (32-1 to 32-m) is at the first power supply potential Vccp, the drive transistor 22 has one electrode as a drain electrode and the other electrode as a source electrode in a saturation region. It operates and receives current from the power supply line 32 to drive the organic EL element 21 to emit light by current driving. More specifically, the drive transistor 22 operates in the saturation region to supply a drive current having a current value corresponding to the voltage value of the signal voltage Vsig held in the holding capacitor 24 to the organic EL element 21. The organic EL element 21 is caused to emit light by current driving.

  Further, when the potential DS of the power supply line 32 (32-1 to 32-m) is switched from the first power supply potential Vccp to the second power supply potential Vini, the drive transistor 22 has one electrode as a source electrode and the other electrode as By operating as a switching transistor as a drain electrode, supply of drive current to the organic EL element 21 is stopped, and the organic EL element 21 is brought into a non-light emitting state. That is, the drive transistor 22 also has a function as a transistor that controls light emission / non-light emission of the organic EL element 21.

  By the switching operation of the drive transistor 22, a period during which the organic EL element 21 is in a non-light emitting state (non-light emitting period) is provided, and duty control is performed to control the ratio (duty) between the light emitting period and the non-light emitting period of the organic EL element 21. By doing so, it is possible to reduce the afterimage blur caused by the pixels emitting light over one frame period. As a result, the picture quality of the moving image can be particularly improved.

(Pixel structure)
FIG. 3 is a cross-sectional view illustrating an example of the cross-sectional structure of the pixel 20. As shown in FIG. 3, in the pixel 20, an insulating film 202, an insulating planarizing film 203, and a window insulating film 204 are formed in that order on a glass substrate 201 on which a driving circuit including a driving transistor 22 and the like is formed. The organic EL element 21 is provided in the recess 204A of the insulating film 204. Here, only the drive transistor 22 is shown in the components of the drive circuit, and the other components are omitted.

  The organic EL element 21 includes an anode electrode 205 made of metal or the like formed on the bottom of the recess 204A of the window insulating film 204, and an organic layer (electron transport layer, light emitting layer, hole transport) formed on the anode electrode 205. Layer / hole injection layer) 206 and a cathode electrode 207 made of a transparent conductive film or the like formed on the organic layer 206 in common for all pixels.

  In the organic EL element 21, the organic layer 206 is formed by sequentially depositing a hole transport layer / hole injection layer 2061, a light emitting layer 2062, an electron transport layer 2063 and an electron injection layer (not shown) on the anode electrode 205. It is formed. Then, current flows from the driving transistor 22 to the organic layer 206 through the anode electrode 205 under current driving by the driving transistor 22 in FIG. 2, so that electrons and holes are recombined in the light emitting layer 2062 in the organic layer 206. It is designed to emit light.

  The driving transistor 22 includes a gate electrode 221, a source / drain region 223 provided on one side of the semiconductor layer 222, a drain / source region 224 provided on the other side of the semiconductor layer 222, and a gate electrode of the semiconductor layer 222. 221 and a portion of the channel formation region 225 facing the portion 221. The source / drain region 223 is electrically connected to the anode electrode 205 of the organic EL element 21 through a contact hole.

  Then, as shown in FIG. 3, the organic EL element 21 is formed on the glass substrate 201 on which the drive circuit including the drive transistor 22 is formed, with the insulating film 202, the insulating planarizing film 203, and the window insulating film 204 interposed therebetween. After the formation, the sealing substrate 209 is bonded by the adhesive 210 through the passivation film 208, and the organic EL element 21 is sealed by the sealing substrate 209, whereby the display panel 70 is formed. .

(Basic circuit operation of organic EL display device)
Next, the basic circuit operation of the organic EL display device 10 according to the present embodiment will be described with reference to the operation explanatory diagrams of FIGS. 5 and 6 based on the timing waveform diagram of FIG.

  In the operation explanatory diagrams of FIGS. 5 and 6, the write transistor 23 is illustrated by a switch symbol for simplification of the drawing. Further, since the organic EL element 21 has a capacitive component Cel, the capacitive component Cel is also illustrated.

  The timing waveform diagram of FIG. 4 shows changes in the potential (scanning signal) WS of the scanning lines 31 (31-1 to 31-m), changes in the potential DS of the power supply lines 32 (32-1 to 32-m), Changes in the gate potential Vg and the source potential Vs of the drive transistor 22 are shown.

<Light emission period of previous frame>
In the timing waveform diagram of FIG. 4, the light emission period of the organic EL element 21 in the previous frame is before time t1. In this light emission period, the potential DS of the power supply line 32 is at the first power supply potential (hereinafter referred to as “high potential”) Vccp, and the writing transistor 23 is in a non-conductive state.

  At this time, since the driving transistor 22 is set to operate in the saturation region, a driving current (drain-source) corresponding to the gate-source voltage Vgs of the driving transistor 22 as shown in FIG. Current Ids is supplied from the power supply line 32 to the organic EL element 21 through the drive transistor 22. Therefore, the organic EL element 21 emits light with a luminance corresponding to the current value of the drive current Ids.

<Threshold correction preparation period>
At time t1, a new frame (current frame) for line sequential scanning is entered. As shown in FIG. 5B, the second power supply potential (hereinafter, referred to as the potential DS of the power supply line 32 is sufficiently lower than Vofs−Vth with respect to the reference potential Vofs of the signal line 33 from the high potential Vccp. Switch to Vini) (described as “low potential”).

  Here, when the threshold voltage of the organic EL element 21 is Vel and the potential of the common power supply line 34 is Vcath, if the low potential Vini is Vini <Vel + Vcath, the source potential Vs of the drive transistor 22 is substantially equal to the low potential Vini. Therefore, the organic EL element 21 is extinguished in a reverse bias state.

  Next, when the potential WS of the scanning line 31 transits from the low potential side to the high potential side at time t2, as shown in FIG. 5C, the writing transistor 23 becomes conductive. At this time, since the reference potential Vofs is supplied from the signal output circuit 60 to the signal line 33, the gate potential Vg of the drive transistor 22 becomes the reference potential Vofs. Further, the source potential Vs of the driving transistor 22 is at a potential Vini that is sufficiently lower than the reference potential Vofs.

  At this time, the gate-source voltage Vgs of the drive transistor 22 is Vofs-Vini. Here, if Vofs−Vini is not larger than the threshold voltage Vth of the drive transistor 22, threshold correction processing described later cannot be performed, and therefore it is necessary to set a potential relationship of Vofs−Vini> Vth.

  As described above, the process of fixing (initializing) the gate potential Vg of the drive transistor 22 to the reference potential Vofs and the source potential Vs to the low potential Vini is a preparation before performing a threshold correction process described later. (Threshold correction preparation) processing. Therefore, the reference potential Vofs and the low potential Vini become the initialization potentials of the gate potential Vg and the source potential Vs of the drive transistor 22, respectively.

<Threshold correction period>
Next, at time t3, as shown in FIG. 5D, when the potential DS of the power supply line 32 is switched from the low potential Vini to the high potential Vccp, the gate potential Vg of the drive transistor 22 is maintained. The source potential Vs of the drive transistor 22 starts to increase toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor 22 from the gate potential Vg. Eventually, the gate-source voltage Vgs of the drive transistor 22 converges to the threshold voltage Vth of the drive transistor 22, and a voltage corresponding to the threshold voltage Vth is held in the storage capacitor 24.

  Here, for convenience, with the gate potential Vg of the drive transistor 22 maintained, the initialization potential (reference potential) Vofs of the gate electrode of the drive transistor 22 is used as a reference and the threshold voltage Vth of the drive transistor 22 from the initialization potential Vofs. The source potential Vs of the drive transistor 22 is changed, specifically increased, toward the potential obtained by subtracting the voltage, and the gate-source voltage Vgs of the drive transistor 22 finally converged is detected as the threshold voltage Vth of the drive transistor 22. A period during which a process corresponding to holding the voltage corresponding to the threshold voltage Vth is held in the holding capacitor 24 is called a threshold correction period.

  In the threshold correction period, the common power supply line 34 is set so that the organic EL element 21 is cut off in order to prevent the current from flowing exclusively to the storage capacitor 24 side and to the organic EL element 21 side. The potential Vcath is set in advance.

  Next, at time t4, the potential WS of the scanning line 31 transitions to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. At this time, the gate electrode of the drive transistor 22 is electrically disconnected from the signal line 33 to be in a floating state. However, since the gate-source voltage Vgs is equal to the threshold voltage Vth of the drive transistor 22, the drive transistor 22 Is in a cut-off state. Therefore, the drain-source current Ids does not flow through the driving transistor 22.

<Signal writing & mobility correction period>
Next, at time t5, as shown in FIG. 6B, the potential of the signal line 33 is switched from the reference potential Vofs to the signal voltage Vsig of the video signal. Subsequently, at time t6, the potential WS of the scanning line 31 transitions to the high potential side, so that the writing transistor 23 becomes conductive as shown in FIG. 6C, and the signal voltage Vsig of the video signal is sampled. To write in the pixel 20.

  By writing the signal voltage Vsig by the writing transistor 23, the gate potential Vg of the driving transistor 22 becomes the signal voltage Vsig. When the driving transistor 22 is driven by the signal voltage Vsig of the video signal, the threshold voltage correction is performed by canceling the threshold voltage Vth of the driving transistor 22 with a voltage corresponding to the threshold voltage Vth held in the holding capacitor 24. Done. The principle of threshold correction will be described later.

  At this time, since the organic EL element 21 is initially in a cut-off state (high impedance state), a current (drain-source current Ids) that flows from the power supply line 32 to the drive transistor 22 according to the signal voltage Vsig of the video signal. Flows into the capacitance component Cel of the organic EL element 21, and charging of the capacitance component Cel is started.

  Due to the charging of the capacitive component Cel, the source potential Vs of the driving transistor 22 rises with time. At this time, the variation in the threshold voltage Vth of the drive transistor 22 has already been corrected, and the drain-source current Ids of the drive transistor 22 depends on the mobility μ of the drive transistor 22.

  Here, assuming that the write gain (ratio of the holding voltage Vgs of the holding capacitor 24 to the signal voltage Vsig of the video signal) is 1 (ideal value), the source potential Vs of the driving transistor 22 rises to a potential of Vofs−Vth + ΔV. Thus, the gate-source voltage Vgs of the drive transistor 22 becomes Vsig−Vofs + Vth−ΔV.

  That is, the increase ΔV of the source potential Vs of the drive transistor 22 is subtracted from the voltage (Vsig−Vofs + Vth) held in the holding capacitor 24, in other words, the charge of the holding capacitor 24 is discharged. And negative feedback was applied. Therefore, the increase ΔV of the source potential Vs becomes a feedback amount of negative feedback.

  As described above, the drain-source current Ids flowing through the drive transistor 22 is negatively fed back to the gate input of the drive transistor 22, that is, the gate-source voltage Vgs, so that the drain-source current Ids of the drive transistor 22 is reduced. Mobility correction is performed to cancel the dependence on the mobility μ, that is, to correct the variation of the mobility μ for each pixel.

  More specifically, since the drain-source current Ids increases as the signal voltage Vsig of the video signal increases, the absolute value of the feedback amount (correction amount) ΔV of negative feedback also increases. Therefore, the mobility correction according to the light emission luminance level is performed.

  Further, when the signal voltage Vsig of the video signal is constant, the absolute value of the feedback amount ΔV of the negative feedback increases as the mobility μ of the driving transistor 22 increases, so that variation in the mobility μ for each pixel is removed. Can do. Therefore, it can be said that the feedback amount ΔV of the negative feedback is a correction amount for mobility correction. Details of the principle of mobility correction will be described later.

<Light emission period>
Next, at time t7, the potential WS of the scanning line 31 shifts to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. 6D. As a result, the gate electrode of the driving transistor 22 is electrically disconnected from the signal line 33 and is in a floating state.

  Here, when the gate electrode of the driving transistor 22 is in a floating state, if the storage capacitor 24 is connected between the gate and the source of the driving transistor 22 and the source potential Vs of the driving transistor 22 fluctuates, The gate potential Vg of the drive transistor 22 also varies in conjunction with (follows) the variation in the potential Vs. Thus, the operation in which the gate potential Vg of the drive transistor 22 varies in conjunction with the variation in the source potential Vs is a bootstrap operation by the storage capacitor 24.

  At the same time, the drain-source current Ids of the drive transistor 22 starts to flow into the organic EL element 21, so that the anode potential of the organic EL element 21 becomes the drain potential of the drive transistor 22. -Increases according to the source-to-source current Ids.

  When the anode potential of the organic EL element 21 exceeds Vel + Vcath, a driving current (light emission current) starts to flow through the organic EL element 21, and thus the organic EL element 21 starts to emit light. The increase in the anode potential of the organic EL element 21 is nothing but the increase in the source potential Vs of the drive transistor 22. When the source potential Vs of the drive transistor 22 rises, the gate potential Vg of the drive transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24.

  At this time, assuming that the bootstrap gain is 1 (ideal value), the amount of increase in the gate potential Vg is equal to the amount of increase in the source potential Vs. Therefore, the gate-source voltage Vgs of the drive transistor 22 is kept constant at Vsig−Vofs + Vth−ΔV during the light emission period. At time t8, the potential of the signal line 33 is switched from the signal voltage Vsig of the video signal to the reference potential Vofs.

(Principle of threshold correction)
Here, the principle of threshold correction of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. As a result, a constant drain-source current (drive current) Ids given by the following equation (1) is supplied from the drive transistor 22 to the organic EL element 21.
Ids = (1/2) · μ (W / L) Cox (Vgs−Vth) ² (1)
Here, W is the channel width of the drive transistor 22, L is the channel length, and Cox is the gate capacitance per unit area.

  FIG. 7 shows characteristics of the drain-source current Ids of the drive transistor 22 versus the gate-source voltage Vgs.

  As shown in this characteristic diagram, when correction for variation in the threshold voltage Vth of the driving transistor 22 for each pixel is not performed, when the threshold voltage Vth is Vth1, the drain-source current Ids corresponding to the gate-source voltage Vgs. Becomes Ids1.

  On the other hand, when the threshold voltage Vth is Vth2 (Vth2> Vth1), the drain-source current Ids corresponding to the same gate-source voltage Vgs is Ids2 (Ids2 <Ids). That is, when the threshold voltage Vth of the drive transistor 22 varies, the drain-source current Ids varies even if the gate-source voltage Vgs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above configuration, as described above, the gate-source voltage Vgs of the drive transistor 22 during light emission is Vsig−Vofs + Vth−ΔV. Then, the drain-source current Ids is
Ids = (1/2) · μ (W / L) Cox (Vsig−Vofs−ΔV) ²
(2)
It is represented by

  That is, the term of the threshold voltage Vth of the drive transistor 22 is canceled, and the drain-source current Ids supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage Vth of the drive transistor 22. As a result, even if the threshold voltage Vth of the drive transistor 22 varies from pixel to pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time, the drain-source current Ids does not vary. The brightness does not change.

(Principle of mobility correction)
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 8 shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the driving transistor 22 and a pixel B having a relatively low mobility μ of the driving transistor 22 are compared. When the driving transistor 22 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

  For example, when the signal voltage Vsig of the video signal of the same level is written in both the pixels A and B in the state where the mobility μ is varied between the pixel A and the pixel B, the movement is not performed. There is a large difference between the drain-source current Ids1 'flowing through the pixel A having a high degree μ and the drain-source current Ids2' flowing through the pixel B having a low mobility μ. Thus, when a large difference occurs between the pixels in the drain-source current Ids due to the variation in mobility μ from pixel to pixel, the uniformity of the screen is impaired.

  Here, as is clear from the transistor characteristic equation of Equation (1), the drain-source current Ids increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 8, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel B having a low mobility.

  Therefore, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the signal voltage Vsig side of the video signal by mobility correction processing, the larger the mobility μ, the larger the negative feedback is applied. It is possible to suppress the variation for each pixel of degree μ.

  Specifically, when the feedback amount ΔV1 is corrected in the pixel A having a high mobility μ, the drain-source current Ids greatly decreases from Ids1 ′ to Ids1. On the other hand, since the feedback amount ΔV2 of the pixel B having a low mobility μ is small, the drain-source current Ids decreases from Ids2 ′ to Ids2, and does not decrease that much. As a result, since the drain-source current Ids1 of the pixel A and the drain-source current Ids2 of the pixel B are substantially equal, the variation in the mobility μ is corrected.

  In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current Ids.

  Therefore, the drain-source current of the pixels having different mobility μ is obtained by negatively feeding back the drain-source current Ids of the drive transistor 22 to the gate electrode side of the drive transistor 22 to which the signal voltage Vsig of the video signal is applied. The current value of Ids is made uniform. As a result, variation in mobility μ for each pixel can be corrected. That is, the process for negatively feeding back the current flowing through the drive transistor 22 (drain-source current Ids) to the gate electrode side of the drive transistor 22 is the mobility correction process.

  Here, in the pixel (pixel circuit) 20 shown in FIG. 2, the relationship between the signal potential (sampling potential) Vsig of the video signal and the drain-source current Ids of the drive transistor 22 depending on the presence or absence of threshold correction and mobility correction. This will be described with reference to FIG.

  In FIG. 9, (A) does not perform both threshold correction and mobility correction, (B) does not perform mobility correction, and performs only threshold correction, (C) performs threshold correction and mobility correction. Each case is shown. As shown in FIG. 9A, when neither threshold correction nor mobility correction is performed, the drain-source current Ids is caused by variations in the threshold voltage Vth and the mobility μ for each of the pixels A and B. A large difference occurs between the pixels A and B.

  On the other hand, when only the threshold correction is performed, as shown in FIG. 9B, although the variation in the drain-source current Ids can be reduced to some extent by the threshold correction, the pixels A and B having the mobility μ A difference in the drain-source current Ids between the pixels A and B due to the variation of each pixel remains.

  Then, by performing both the threshold correction and the mobility correction, as shown in FIG. 9C, the drain between the pixels A and B due to the variation of the threshold voltage Vth and the mobility μ for each of the pixels A and B. -Since the difference between the source currents Ids can be almost eliminated, the luminance variation of the organic EL element 21 does not occur at any gradation, and a display image with good image quality can be obtained.

  Further, the pixel 20 shown in FIG. 2 has the function of bootstrap operation by the holding capacitor 24 described above in addition to the correction functions of threshold correction and mobility correction. Obtainable.

  That is, even if the IV characteristic of the organic EL element 21 changes with time, and the source potential Vs of the drive transistor 22 changes accordingly, the bootstrap operation by the storage capacitor 24 causes the gate-source connection of the drive transistor 22. Since the potential Vgs can be maintained constant, the current flowing through the organic EL element 21 does not change and is constant. Therefore, since the light emission luminance of the organic EL element 21 is also kept constant, even if the IV characteristic of the organic EL element 21 changes with time, it is possible to realize an image display that does not cause luminance deterioration associated therewith.

(About the optimal correction time for mobility correction)
As is clear from the above-described operation explanation, when considering a driving transistor with high mobility and a driving transistor with low mobility, the driving transistor with high mobility is compared to the driving transistor with low mobility in the mobility correction period. As a result, the source potential Vs greatly increases. In addition, since the potential difference Vgs between the gate and the source of the driving transistor becomes smaller as the source potential Vs increases, current hardly flows to the driving transistor.

  Therefore, the correction time for performing the mobility correction process (hereinafter simply referred to as “mobility correction correction time”) is adjusted, and the correction amount (= drain) for the gate input of the drive transistor 22, that is, the signal voltage Vsig of the video signal. -By changing the feedback amount ΔV) in the negative feedback of the source-to-source current Ids, the same current can be supplied to the drive transistors having different mobility μ. Therefore, it is necessary to optimize the correction time for mobility correction in the signal voltage Vsig of each video signal, that is, to set the correction time for mobility correction to an optimal correction time according to the signal voltage Vsig of the video signal. .

The optimum correction time t for mobility correction (hereinafter sometimes simply referred to as “correction time t”) is:
t = C / (kμVsig) (3)
It is given by Here, the constant k is k = (1/2) (W / L) Cox. Further, C is a capacity of a node that is discharged when the mobility correction is performed. In the circuit example of FIG. 2, C is an equivalent capacity (capacitance component Cel) of the organic EL element 21 and a combined capacity of the storage capacitor 24.

  The optimum correction time t for mobility correction is determined by the timing at which the write transistor 23 shifts from the conductive state to the non-conductive state. Then, the writing transistor 23 is cut off when the potential difference between the gate potential and the potential of the signal line 33, that is, the gate-source voltage reaches the threshold voltage Vth, that is, shifts from the conductive state to the non-conductive state.

  By the way, the applicant makes the correction time t for mobility correction inversely proportional to the signal voltage Vsig of the video signal, that is, the correction time t becomes shorter as the signal voltage Vsig is higher, and the correction time is lower as the signal voltage Vsig is lower. By setting t to be longer, it is possible to more reliably cancel the dependence of the drain-source current Ids of the driving transistor 22 on the mobility μ, that is, more reliably the variation of the mobility μ from pixel to pixel. It is confirmed that it can be corrected.

  Therefore, the falling waveform when the write pulse WS applied to the gate electrode of the write transistor 23 transitions from the high level to the low level (the rising waveform when the write transistor 23 is a P channel) is shown in FIG. As described above, the waveform is set to be inversely proportional to the signal voltage Vsig of the video signal.

  By setting the falling waveform of the write pulse WS to a waveform that is inversely proportional to the signal voltage Vsig of the video signal, when the gate-source voltage of the write transistor 23 reaches the threshold voltage Vth, the write transistor 23 Therefore, the optimum correction time t for mobility correction can be set to be inversely proportional to the signal voltage Vsig of the video signal.

  Specifically, as is apparent from the waveform diagram of FIG. 10, when the signal voltage Vsig (white) corresponding to the white level of the write transistor 23, the gate-source voltage becomes Vsig (white) + Vth. By the way, in order to cut off, the correction time t (white) for mobility correction is set to be the shortest, and when the signal voltage Vsig (gray) corresponding to the gray level, the gate-source voltage becomes Vsig (gray) + Vth. In order to cut off at this point, the correction time t (gray) is set longer than the correction time t (white).

  Thus, by setting the optimal correction time t for mobility correction so as to be inversely proportional to the signal voltage Vsig of the video signal, the optimal correction time t can be set corresponding to the signal voltage Vsig of the video signal. The dependence of the drain-source current Ids of the driving transistor 22 on the mobility μ can be more reliably canceled over the entire level range (all gradations) of the signal voltage Vsig from the level to the white level, that is, the mobility μ. The variation for each pixel can be corrected more reliably.

(Write scanning circuit)
Next, a specific configuration of the write scanning circuit 40 that generates the write pulse WS having a falling waveform that is inversely proportional to the signal voltage Vsig of the video signal will be described.

  As described above, the write pulse WS (WS 1 to WSm) is output from the write scanning circuit 40. As shown in FIG. 11, the write scanning circuit 40 includes a shift register 41 including a logic circuit, a level circuit 42, and an output circuit 43. The write scanning circuit 40 is a display panel as a drive unit that drives each pixel 20 of the pixel array unit 30. 70 is implemented.

  In the write scanning circuit 40, the level conversion circuit 42 is not an essential component and is provided when level conversion is required for the output signal of the shift register. The output circuit 43 includes a plurality of stages of buffers for each pixel row, for example, two stages of buffers 431 and 432, and the positive-side power supply line between the final-stage buffer 432 and the preceding-stage circuit portion is separated. .

  Various timing signals and power supply potentials are supplied to the writing scanning circuit 40 from, for example, a flexible cable 90 from a control board 80 provided outside the display panel 70. Specifically, a timing generation (TG) unit 81, a power supply unit 82, a power supply unit 83, and the like are provided on the control board 80.

  The timing generation unit 81 generates a clock pulse CK serving as a reference for the operation of the shift register 41 and a start pulse ST for instructing the start of the shift operation of the shift register 41, and supplies the generated clock pulse CK to the shift register 41. The shift register 41 uses the positive power supply potential VDD and the negative power supply potential VSS as operating power supply potentials.

  The power supply unit 82 generates a positive power supply potential WSHigh that is different from the power supply potential VDD, for example, higher than the power supply potential VDD, and a negative power supply potential WSLow that is equal to or lower than the power supply potential VSS. The power supply potential WSHigh on the positive side is supplied as a power supply potential on the positive side to the buffers other than the level conversion circuit 42 and the final stage buffer 432 of the output circuit 43 via the flexible cable 90 by the power supply line 84. . The negative power supply potential WSLow is supplied as a negative power supply potential to the output circuit 43 including the level conversion circuit 42 and the final stage buffer 432 via the flexible cable 90 via the power supply line 85.

  The power supply unit 83 generates a write pulse WS having a falling waveform that is inversely proportional to the signal voltage Vsig of the video signal, and supplies a positive power supply potential WSHigh and a negative power supply provided from the power supply unit 82. Based on the potential WSLow, the power supply potential Vddws on the positive side that falls with a desired falling waveform (falling waveform of the write pulse WS) is generated. The power supply potential Vddws is supplied as a positive power supply potential to the final buffer 432 of the output circuit 43 through the flexible cable 90 via the power supply line 86.

  In this example, the power supply unit 83 is provided on the control board 80 side. However, the present invention is not limited to this, and the power supply unit 83 is provided on the same display pulse 70 side as the write scanning circuit 40. Is also possible.

  FIG. 12 shows an example of the configuration of the circuit portion 40 (i) corresponding to the i-th pixel row of the write scanning circuit 40 and a specific circuit configuration of the power supply unit 83. The circuit portions corresponding to the other pixel rows have the same configuration.

  In FIG. 12, the i-th shift stage (hereinafter referred to as “shift stage 41”), which is a unit circuit of the shift register, is cascade-connected by the number of stages corresponding to the number of rows of the pixel array unit 30, and the negative side The power supply potential VSS and the positive power supply potential VDD are set as the operation power supply potential, and a scanning signal having a pulse waveform with an amplitude of VSS-VDD is sequentially output in synchronization with the vertical scanning.

  The level conversion circuit 42 has a negative power supply potential WSLow equal to or lower than the negative power supply potential VSS of the shift stage 41 and a positive power supply potential WSHigh higher than the positive power supply potential VDD of the shift stage 41. And the level of the scan pulse having the VSS-VDD amplitude output from the shift stage 41 to the scan pulse SCP having the WSLow-WSHigh amplitude.

  The output circuit 43 includes, for example, two-stage buffers 431 and 432, and the positive-side power supply line between the final-stage buffer 432 and the circuit portion on the preceding stage is separated. The first-stage buffer 431 includes a CMOS inverter connected between the negative power supply potential WSLow and the positive power supply potential WSHigh, which are the same as those of the level conversion circuit 42, and a scanning pulse output from the level conversion circuit 42. Invert the polarity of the SCP.

  In the final-stage buffer 432, for example, the positive-side power supply line is separated from the positive-side power supply line of the first-stage buffer 431, and a dedicated power supply potential is supplied from the power supply unit 83 as the positive-side power supply potential Vddws. The In this example, the negative power line is common to the negative power line of the buffer 431.

  This last stage buffer 432 is configured by the same CMOS inverter as the first stage buffer 431, and further inverts the polarity of the inverted scanning pulse output from the buffer 431 and outputs it as the write pulse WS (i) of the i-th row. To do.

  In the power supply unit 83, for example, one electrode (source / drain electrode) is connected to the switch element 833 connected between the first input terminal 851 and the output terminal 852, and the second input terminal 834, and the output terminal 832 and a MOS transistor 835 having the other electrode (drain / source electrode) connected thereto.

  A positive power supply potential WSHigh is input from the power supply unit 82 to the first input terminal 831, and a negative power supply potential WSLow is input from the power supply unit 82 to the second input terminal 834. The switch element 833 is controlled to be turned on (closed) / off (opened) by a first control pulse CP1 input via the first control terminal 836. In the MOS transistor 835, conduction / non-conduction is controlled by a second control pulse CP2 applied to the gate electrode via the second control terminal 837. The first and second control pulses CP1 and CP2 are generated at a predetermined control timing in the timing generator 81.

  Next, the circuit operation of the circuit portion 40 (i) corresponding to the i-th pixel row and the power supply unit 83 in the write scanning circuit 40 having the above configuration will be described with reference to the timing waveform diagram of FIG.

  In the timing waveform diagram of FIG. 13, the scan pulse SCP input to the first stage buffer 431, the first control pulse CP1 and the second control pulse CP2 input to the power supply unit 83, and the output from the last stage buffer 432 are shown. The timing relationship with the write pulse WS (i) is shown.

  The scan pulse SCP becomes active (high level) in the period from time t11 to t12 and in the period from time t14 to t16. The period from time t11 to t12 corresponds to the period from time t2 to t4 in FIG. 4 and is a period for initializing the gate potential Vg and gate potential Vs of the driving transistor 22 and performing threshold correction processing. The period from time t14 to t16 corresponds to the period from time t6 to t7 in FIG. 4 and is a period for performing video signal writing and mobility correction processing.

  The first control pulse CP1 is normally in a high level state. At this time, since the switch element 833 is in the ON state, the power supply unit 83 supplies the power supply potential WSHigh to the final stage buffer 432 as the positive power supply potential Vddws via the power supply line 86. As a result, the write pulse WS (i) of the power supply potential WSHigh is output in the period from time t11 to t12.

  Here, when the write pulse WS (i) is lowered, the power supply line 86 needs to be electrically floated before the write pulse WS (i) is lowered. Therefore, the first control pulse CP1 is made inactive at time t13 within the period in which the scan pulse SCP is in the inactive state (low level). The first control pulse CP1 becomes inactive and the switch element 833 is turned off (opened), so that the power supply line 86 enters a floating state.

  At this time, even if the switch element 833 is turned off, the power supply potential WSHigh is held in the power supply line 86 by the parasitic capacitance C_VddL or the like. Thereafter, the scanning pulse SCP becomes active at time t14, so that the writing pulse WS (i) again becomes the power supply potential WSHigh. Then, at time t15, the second control pulse CP2 transitions from the low level to the high level, so that the MOS transistor 835 is turned on in the power supply unit 83.

  Then, the positive-side power supply potential Vddws of the buffer 432 in the final stage is directed toward the negative-side power supply potential WSLow with a falling waveform determined by the time constant between the on-resistance Ron of the MOS transistor 835 and the parasitic capacitance C_VddL of the power supply line 86. And descend. As a result, the write pulse WS (i) falls with a falling waveform determined by the time constant. At time t16 when the scan pulse SCP becomes inactive, the write pulse WS (i) becomes the negative power supply potential WSLow and disappears.

  In the above description of the circuit operation, the power supply line 86 holds the power supply potential WSHigh when the switch element 833 is turned off and the power supply line 86 is in a floating state. Then, the potential of the power supply line 86 is lower than the power supply potential WSHigh for the reason described below.

  When the scan pulse SCP becomes active at time t14 and the Pch transistor of the final stage buffer 432 is turned on in response to this, the power supply line 86 is in a floating state, and therefore the power supply line 86 is buffered. Capacitive coupling occurs by being electrically connected to the scanning line 31-i via the 432 Pch transistor.

  Then, due to the charge distribution between the parasitic capacitance C_VddL of the power supply line 86 and the parasitic capacitance C_WSL of the scanning line 31-i, as shown in FIG. 14, the potential held in the power supply line 86, that is, the buffer 432 at the final stage. The power supply potential Vddws of the power supply decreases.

  In the timing waveform diagram of FIG. 14, times t13, t14, and t15 correspond to times t13, t14, and t15 of FIG. 13, respectively, and at time t13, the first control pulse CP1 transitions from a high level to a low level. At time t14, the scanning pulse SCP changes from low level to high level, and at time t15, the second control pulse SP2 changes from low level to high level.

Here, the power supply potential Vddws after the capacitive coupling and the potential WSL of the scanning line 31-i are values given by the following equation (4).
Vddws = WSL
= (WSHigh × C_VddL + WSLow × C_WSL)
/ (C_VddL + C_WSL) (4)

  Further, as an example, when a case where a black window display image shown in FIG. 15 is output is considered, a scanning line 31-w for a region displaying only white, and a scanning line 31-b for a region displaying black. In the meantime, a difference occurs in the parasitic capacitance C_WSL of the scanning line 31. The reason is as follows.

  The black display image has a low signal voltage Vsig, and the white display image has a high signal voltage Vsig. When the write pulse WS is raised from the negative power supply potential WSLow to the positive power supply potential WSHigh, a black display image pixel with a small signal voltage Vsig is compared with a white display image pixel with a high signal voltage Vsig. Thus, the write transistor 23 becomes conductive at an early stage during the rise of the write pulse WS. Accordingly, in the writing transistor 23 of the pixel of the black display image, a channel is formed between the source region and the drain region since the signal voltage Vsig is small.

  In a transistor, when a channel is formed between a source region and a drain region, parasitic capacitance formed between the channel and the gate electrode increases. Therefore, the parasitic capacitance interposed between the channel of the write transistor 23 and the gate electrode changes depending on the value of the signal voltage Vsig. More specifically, a black display image pixel having a small signal voltage Vsig is turned on earlier than a white display image pixel having a large signal voltage Vsig. A parasitic capacitance is formed quickly.

  As a result, there is a difference in the parasitic capacitance C_WSL of the scanning line 31 between the scanning line 31-w in the region displaying only white and the scanning line 31-b in the region displaying black, so that after the capacitive coupling Is different between the scan line 31-w and the scan line 31-b in the power supply potential Vddws and the potential WSL of the scan line 31-i (the peak value of the write pulse WS). Further, if the timing at which the parasitic capacitance is formed between the channel and the gate electrode of the write transistor 23 is early, the rising waveform of the write pulse WS after that becomes dull, and the writing of the signal voltage Vsig is delayed accordingly.

  Then, a difference occurs between the scanning line 31-w and the scanning line 31-b in the rising speed of the gate potential Vg of the driving transistor 22 in the signal writing & mobility correction period of FIG. Specifically, the rising speed of the gate potential Vg of the drive transistor 22 is slower in the scanning line 31-b in the region displaying black than in the scanning line 31-w in the region displaying only white. As a result, even if the signal voltage Vsig having the same value is written, there is a difference in the written voltage between the area displaying only white and the area displaying black. It will occur.

  More specifically, even if the same white level is written as the signal voltage Vsig in an area displaying only white and an area displaying white on both the left and right sides of the black window, a difference occurs in the written white level. For this reason, a luminance difference occurs even in the same white display. In the display image of FIG. 15, this luminance difference is visually recognized as horizontal crosstalk that occurs on both the left and right sides of the black window (shaded portions in FIG. 15).

  In particular, as in the case of the organic EL display device 10 according to the present embodiment, in the organic EL display device having a pixel configuration including two transistors of the drive transistor 22 and the write transistor 23, the writing process and the mobility of the signal voltage Vsig. Since the correction processing is performed in parallel, the rising speed of the gate potential Vg of the driving transistor 22 is moved due to a difference between the scanning line 31-w and the scanning line 31-b. A difference also occurs in the degree correction processing.

  Specifically, the parasitic capacitance is formed between the channel and the gate electrode of the writing transistor 23 in the scanning line 31-b in the region displaying black, than in the scanning line 31-w in the region displaying only white. As the timing of the write pulse WS rises and the rising waveform of the write pulse WS is smoothed, the correction time t for mobility correction is shortened, that is, the current flowing through the drive transistor 22 (drain-source current Ids) is negatively fed back to the gate electrode side. Since the time required for the reduction is shortened, the luminance increases (becomes brighter) even if the same white level is written. As a result, the effect of improving the display quality (image quality) associated with the mobility correction process cannot be obtained sufficiently.

  From the viewpoint described above, in this embodiment, as shown in FIG. 12, the power supply potential Vddws generated by the power supply unit 83 is transferred from the power supply unit 83 to the buffer 432 at the final stage of the output circuit 43. A configuration is adopted in which a capacitive element 87 is added to a power supply line 86 supplied as a power supply potential.

  Here, when the capacitance value of the capacitor 87 is C_Vddα, when the power supply line 86 is in a floating state, the power supply line 86 is connected to the scanning line 31-i via the Pch transistor of the buffer 432, and the capacitance The power supply potential Vddws and the potential WSL of the scanning line 31-i after capacitive coupling caused by charge sharing between the element 87 (C_Vddα) and the parasitic capacitance C_VddL of the power supply line 86 and the parasitic capacitance C_WSL of the scanning line 31-i are: The value is given by the following equation (5).

Vddws = WSL
= {WSHigh × (C_VddL + C_Vddα) + WSLow × C_WSL}
/ (C_VddL + C_Vddα + C_WSL)
...... (5)

  As apparent from the above equation (5), when the capacitive element 87 is added to the power supply line 86, the power supply line 86 is connected to the scanning line 31-i via the Pch transistor of the buffer 432. The decrease in the power supply potential Vddws caused by the capacitive coupling can be made smaller than when the capacitive element 87 is not added to the power supply line 86. As the capacitance value C_Vddα of the capacitor 87 is larger, the decrease in the power supply potential Vddws can be suppressed.

  More specifically, when the capacitance value C_Vddα of the capacitive element 87 is sufficiently larger than the parasitic capacitance C_VddL of the power supply line 86 and the parasitic capacitance C_WSL of the scanning line 31-i, it is apparent from the above equation (5). In addition, since the parasitic capacitance C_WSL of the scanning line 31-i can be ignored, the power supply potential Vddws after the capacitive coupling (the potential WSL of the scanning line 31-i) can be set almost equal to the original power supply potential SWHigh.

  As a result, taking as an example the case where a black window display image shown in FIG. 15 is output, the scanning line 31-w for the region displaying only white, and the scanning line 31-b for the region displaying black. Even if there is a difference in the parasitic capacitance C_WSL of the scanning line 31 for the reason described above, there is no difference in the potential WSL of the scanning line 31, that is, the peak value of the write pulse WS. There is no difference in luminance between the white display area and the black display area. As a result, luminance variation does not occur in each display pattern, and the display quality (image quality) improvement effect associated with the mobility correction processing can be sufficiently obtained, so that a display image with good image quality can be obtained. .

  In the write scanning circuit 40 having the above configuration, the circuit configuration of the power supply unit 83 is an example, and the power supply unit 83 is not limited to this circuit configuration, and is inversely proportional to the signal voltage Vsig of the video signal. In order to generate the write pulse WS having such a falling waveform, the power supply potential WSHigh falling at the falling waveform can be supplied as the positive power supply potential Vddws to the buffer 432 at the final stage. Does not matter.

  Specifically, as another circuit configuration of the power supply unit 83, instead of the MOS transistor 835, a configuration in which a resistance element and a switch element are connected in series, or a plurality of MOS transistors having different on-resistances are connected in parallel. Connect and connect multiple MOS transistors in parallel to each other to obtain a desired falling waveform, or connect multiple series connection circuits of multiple resistance elements and multiple switching elements with different resistance values in parallel. A configuration in which a desired falling waveform is obtained by appropriately turning on a plurality of switch elements is conceivable.

  Next, a specific embodiment in which the capacitive element 87 is added to the power supply line 86 will be described.

Example 1
FIG. 16 is a circuit diagram showing a configuration example of the power supply unit 83 according to the first embodiment in which the capacitive element 87 is added to the power supply line 86. In FIG. Show.

  In the first embodiment, as shown in FIG. 11, for example, when the power supply unit 83 is provided on the control board 80, the power supply unit 83 is provided with a capacitor terminal 838 electrically connected to the power supply line 86. The capacitor element 87 is connected between the capacitor terminal 838 and a reference potential node, for example, the ground.

  In this way, by attaching the capacitive element 87 to the power supply unit 83, the capacitance value C_Vddα of the capacitive element 87 can be freely selected, and the capacitance value C_Vddα of the power supply line 86 can be selected. By selecting a value sufficiently larger than the parasitic capacitance C_VddL and the parasitic capacitance C_WSL of the scanning line 31-i, the power supply potential Vddws after the capacitive coupling (the potential WSL of the scanning line 31-i) is minimized. Ideally, it can be set to the power supply potential SWHigh.

  Here, although the capacitive element 87 is externally attached to the power supply unit 83, a configuration in which the capacitive element 87 is provided inside the power supply unit 83 may be employed.

(Example 2)
FIG. 17 is a plan pattern diagram illustrating a configuration of a main part of the write scanning circuit 40 according to the second embodiment in which the capacitive element 87 is added to the power supply line 86.

  In FIG. 17, the power supply potential Vddws generated by the power supply unit 83 is supplied as the positive power supply potential to the final stage buffer 432 (see FIG. 11) of each scanning stage in the formation region of the write scanning circuit 40. Therefore, the power supply line 86 is formed along the arrangement direction of the scanning lines 31-1 to 31 -m (the scanning direction of the writing scanning circuit 40) by the metal wiring 87 made of aluminum (Al) or the like.

  A metal wiring 88 made of an insulating layer (not shown) molybdenum (Mo) or the like is formed facing the metal wiring 87 of the power supply line 86, so that the metal wiring 87 is interposed between the metal wiring 87 and the metal wiring 88. A capacitive component can be formed, and the capacitive component becomes a capacitive element 87 added to the power supply line 86. At this time, the capacitance value C_Vddα of the capacitive element 87 is determined by the facing area S between the metal wiring 87 and the metal wiring 88 and the distance d between both the wirings 87 and 88. Therefore, the capacitance value C_Vddα of the capacitive element 87 can be freely set by increasing the opposing area S by increasing the thickness of the metal wiring 87 of the power supply line 86 or by decreasing the distance d between the wirings 87 and 88. can do.

  In this way, the capacitance component formed between the metal wiring 87 of the power supply line 86 and the metal wiring 88 facing the metal wiring 87 is used as the capacitive element 87 added to the source supply line 86, so that the capacitance can be obtained. Since the element 87 can be built in the display panel 70 in advance, it is not necessary to externally attach the capacitive element 87 to the power supply unit 83 on the control board 80.

  It is also possible to adopt a structure in which the metal wiring 87 of the power supply line 86 is sandwiched between two electrically connected metal wirings 88A and 88B. By adopting this structure, the facing area S between the metal wiring 87 of the power supply line 86 and the metal wirings 88A and 88B can be doubled as compared with the case where one metal wiring 88 is provided. The capacitance value C_Vddα can be set larger.

[Modification]
In the above embodiment, the case where the present invention is applied to an organic EL display device using an organic EL element as the electro-optical element of the pixel 20 has been described as an example. However, the present invention is not limited to this application example, and the device The present invention can be applied to all display devices using current-driven electro-optic elements in which the light emission luminance changes according to the value of the current flowing through the.

[Application example]
As an example, the display device according to the present invention described above is applied to various electronic devices shown in FIGS. 18 to 22, for example, electronic devices such as digital cameras, notebook personal computers, mobile terminal devices such as mobile phones, and video cameras. The input video signal or the video signal generated in the electronic device can be applied to a display device of an electronic device in any field that displays an image or a video.

  As described above, by using the display device according to the present invention as a display device for electronic devices in all fields, the display device according to the present invention causes luminance variations in each display pattern, as is apparent from the description of the above-described embodiment. In addition, since the display quality improvement effect associated with the mobility correction process can be sufficiently obtained, it is possible to display images with good image quality in various electronic devices.

  Note that the display device according to the present invention includes a module-shaped one having a sealed configuration. For example, a display module formed by being affixed to an opposing portion such as transparent glass on the pixel array portion 30 is applicable. The transparent facing portion may be provided with a color filter, a protective film, and the like, and further the above-described light shielding film. Note that the display module may be provided with a circuit unit for inputting / outputting signals from the outside to the pixel array unit, an FPC (flexible printed circuit), and the like.

  Specific examples of electronic devices to which the present invention is applied will be described below.

  FIG. 18 is a perspective view showing a television to which the present invention is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to the present invention as the video display screen unit 101.

  19A and 19B are perspective views showing a digital camera to which the present invention is applied. FIG. 19A is a perspective view seen from the front side, and FIG. 19B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present invention as the display unit 112.

  FIG. 20 is a perspective view showing a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like, and the display device according to the present invention is used as the display unit 123. It is produced by this.

  FIG. 21 is a perspective view showing a video camera to which the present invention is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using a display device.

  FIG. 22 is a perspective view showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which (A) is a front view in an opened state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. Alternatively, the sub-display 145 is manufactured by using the display device according to the present invention.

1 is a system configuration diagram illustrating an outline of a configuration of an organic EL display device according to an embodiment of the present invention. It is a circuit diagram which shows the specific structural example of a pixel (pixel circuit). It is sectional drawing which shows an example of the cross-sectional structure of a pixel. It is a timing waveform diagram with which it uses for description of the basic circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 1) of circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 2) of the circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the threshold voltage Vth of a drive transistor. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the mobility (mu) of a drive transistor. FIG. 6 is a characteristic diagram for explaining the relationship between the signal voltage Vsig of the video signal and the drain-source current Ids of the drive transistor depending on whether or not threshold correction and mobility correction are performed. It is a wave form diagram which shows the relationship between the falling waveform of the write pulse WS, and the optimal correction time t of mobility correction. It is a block diagram which shows an example of a structure of a writing scanning circuit. FIG. 3 is a circuit diagram illustrating an example of a configuration of a circuit portion corresponding to an i-th pixel row in a writing scanning circuit and a specific circuit configuration of a power supply unit. FIG. 5 is a timing waveform diagram for explaining circuit operations of a circuit portion corresponding to an i-th pixel row of a writing scanning circuit and a power supply unit. FIG. 10 is a timing waveform diagram showing how the power supply potential Vddws and the potential WSL of the scanning line 31-i decrease due to capacitive coupling between the floating power supply line and the scanning line. It is a figure which shows the mode of the horizontal crosstalk generate | occur | produced when the signal write voltage of each line changes. It is a circuit diagram which shows the structural example of the power supply part which concerns on Example 1 which adds a capacitive element to a power supply line. FIG. 10 is a plan pattern diagram illustrating a configuration of a main part of a write scanning circuit according to a second embodiment in which a capacitor is added to a power supply line. It is a perspective view which shows the external appearance of the television set to which this invention is applied. It is a perspective view which shows the external appearance of the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view illustrating an appearance of a notebook personal computer to which the present invention is applied. It is a perspective view which shows the external appearance of the video camera to which this invention is applied. BRIEF DESCRIPTION OF THE DRAWINGS It is an external view which shows the mobile telephone to which this invention is applied, (A) is the front view in the open state, (B) is the side view, (C) is the front view in the closed state, (D) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Organic EL display device, 20 ... Pixel (pixel circuit), 21 ... Organic EL element, 22 ... Drive transistor, 23 ... Write transistor, 24 ... Retention capacity, 30 ... Pixel array part, 31 (31-1 to 31-31) m) ... scanning line, 32 (32-1 to 32-m) ... power supply line, 33 (33-1 to 33-n) ... signal line, 34 ... common power supply line, 40 ... write scanning circuit, 41 ... Shift register, 42 ... level conversion circuit, 43 ... output circuit, 50 ... power supply scanning circuit, 60 ... signal output circuit, 70 ... display panel, 80 ... control board, 81 ... timing generator, 82 ... power supply, 83 ... Power supply unit, 90 ... Flexible cable

Claims (6)

An electro-optic element;
A writing transistor in which a gate electrode is connected to the scanning line and one electrode is connected to a signal line to which a video signal is supplied;
A driving transistor in which a gate electrode is connected to the other electrode of the writing transistor, one electrode is connected to a power supply line, and the other electrode is connected to an anode electrode of the electro-optic element;
A pixel array unit in which pixels having a storage capacitor in which one electrode is connected to the gate electrode of the driving transistor and the other electrode is connected to the other electrode of the driving transistor; and
A power supply scanning circuit for selectively supplying a first power supply potential and a second power supply potential lower than the first power supply potential to the power supply line;
A write scanning circuit having a final stage buffer in which a circuit part on the front stage side and a power supply line are separated, and writing the video signal by the write transistor by giving a write pulse output from the final stage buffer to the write transistor And
In the display device, a mobility correction process for applying negative feedback to the gate input side of the drive transistor with a correction amount corresponding to a current flowing through the drive transistor is performed in parallel with the video signal write process by the write transistor. And
The write scanning circuit includes:
A power supply unit that supplies a power supply potential that changes in a waveform determined by a predetermined time constant to the final stage buffer when the write pulse is transitioned from an active state to an inactive state;
A display device comprising: a capacitor added to a power supply line that supplies the power supply potential from the power supply unit to the final stage buffer. The display device according to claim 1, wherein a capacitance value of the capacitive element is larger than each capacitance value of a parasitic capacitance of the scanning line and a parasitic capacitance of the power supply line. The power supply unit has a terminal electrically connected to the power supply line;
The display device according to claim 1, wherein the capacitive element is connected between the terminal and a reference potential node. The capacitive element is a capacitive component formed between a first metal wiring serving as the power supply line and a second metal wiring formed to face the first metal wiring. The display device according to claim 1. An electro-optic element;
A writing transistor in which a gate electrode is connected to the scanning line and one electrode is connected to a signal line to which a video signal is supplied;
A driving transistor in which a gate electrode is connected to the other electrode of the writing transistor, one electrode is connected to a power supply line, and the other electrode is connected to an anode electrode of the electro-optic element;
A pixel array unit in which pixels having a storage capacitor in which one electrode is connected to the gate electrode of the driving transistor and the other electrode is connected to the other electrode of the driving transistor; and
A power supply scanning circuit for selectively supplying a first power supply potential and a second power supply potential lower than the first power supply potential to the power supply line;
It has a final stage buffer in which the circuit part on the previous stage side and the power supply line are separated, and the video signal is written by the write transistor by giving a write pulse output from the final stage buffer to the write transistor, and A write scanning circuit having a power supply unit that supplies a power supply potential that changes in a waveform determined by a predetermined time constant to the final stage buffer when the write pulse is transitioned from an active state to an inactive state; Circuit
A power supply unit that supplies a power supply potential that changes in a waveform determined by a predetermined time constant to the final stage buffer when the write pulse is transitioned from an active state to an inactive state;
A capacitive element added to a power supply line that supplies the power supply potential from the power supply unit to the final stage buffer;
Driving a display device that performs mobility correction processing for applying negative feedback to the gate input side of the driving transistor with a correction amount corresponding to the current flowing through the driving transistor in parallel with the video signal writing processing by the writing transistor A method,
Before starting the video signal writing process, the power supply line is in an electrically floating state,
Next, the writing pulse is shifted from the inactive state to the active state to start the writing process of the video signal,
Thereafter, the mobility correction processing is executed with a correction time determined by a waveform when the write pulse is shifted from an active state to an inactive state. An electro-optic element;
A writing transistor in which a gate electrode is connected to the scanning line and one electrode is connected to a signal line to which a video signal is supplied;
A driving transistor in which a gate electrode is connected to the other electrode of the writing transistor, one electrode is connected to a power supply line, and the other electrode is connected to an anode electrode of the electro-optic element;
A pixel array unit in which pixels having a storage capacitor in which one electrode is connected to the gate electrode of the driving transistor and the other electrode is connected to the other electrode of the driving transistor; and
A power supply scanning circuit for selectively supplying a first power supply potential and a second power supply potential lower than the first power supply potential to the power supply line;
It has a final stage buffer in which the circuit part on the previous stage side and the power supply line are separated, and the video signal is written by the write transistor by giving a write pulse output from the final stage buffer to the write transistor. A write scanning circuit having a power supply unit that supplies a power supply potential that changes in a waveform determined by a predetermined time constant to the final stage buffer when transitioning the write pulse from the active state to the inactive state;
A display device that executes mobility correction processing for applying negative feedback to the gate input side of the driving transistor with a correction amount corresponding to the current flowing through the driving transistor in parallel with the video signal writing processing by the writing transistor. Electronic equipment,
The write scanning circuit includes:
A power supply unit that supplies a power supply potential that changes in a waveform determined by a predetermined time constant to the final stage buffer when the write pulse is transitioned from an active state to an inactive state;
An electronic device, comprising: a capacitor added to a power supply line that supplies the power supply potential from the power supply unit to the final stage buffer.

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