JP2010015433A - Control/supervisory signal transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control/supervisory signal transmission system which superimposes clock signals superimposed with power supplies with supervisory signals and control signals using a mediation station with which faults of restricting a change in the number of inputs or outputs are eliminated, and which has the mediation station having the degree of freedom of coping with an input part and an output part inside, and is easily used. <P>SOLUTION: In the mediation station connected to a plurality of slave stations by common data signal lines and sends out the supervisory data transmitted through the slave stations from an actuator as the control data to previously correlated another actuator, the supervisory data are overwritten and stored in a storage region of the mediation station after sending out of the other surveillance data already stored in the storage region as the control data when extracted from the control signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a control / monitoring signal transmission system, which is a simple control / monitoring signal transmission system having a configuration in which an intermediary station is provided in place of a PLC (programmable logic controller), a computer, and a master station. With this configuration, a parallel control signal from the control unit is converted into a serial signal and transmitted, and the device is controlled by converting the serial signal into a parallel signal on the side of the operating device at a remote position. This is a so-called wiring-saving system concept in which wiring between devices can be omitted. In the case of regular control where the output with respect to the input is constant while omitting such wiring, simpler control can simplify the design and the equipment. The present invention relates to a control / monitor signal transmission system that superimposes a power signal on a transmission signal and superimposes a monitor signal and a control signal on a clock signal in regular control with a constant output for such an input.

  Conventionally, even control that performs simple input / output has always been performed by the judgment of the central control system. As the central control system, there are a host computer, a PLC (programmable logic controller), a master station with reduced wiring, and the like. These central control systems and controlled devices such as lamps and solenoid valves, or wire-saving output units (control units that reduce the number of wires by converting communication control signals from parallel signals to serial signals and combining them, for example, from a minimum of one terminal (A suitable unit with 32 terminals can be selected and used), and communication control is performed, and monitoring signals are transmitted from a number of remote sensor units (switches, phototransistors, and other on / off states). The control / monitoring signal transmission system is widely used in the technical field of automatic control.

On the other hand, in these technical fields of automatic control, a method for performing communication control more easily has been proposed. For example, in Patent Document 1, an intermediary station is provided without a control unit in place of a master station. A communication control system is described in which simple communication control without a control unit can be performed by transmitting a signal of an input unit to an output unit.
JP 2005-080256 A

  However, the communication control system using the mediation station has a drawback that changes in the number of inputs and outputs are restricted by the circuit of the mediation station. Also, the regularity of signal transmission from the input unit to the output unit has a drawback that it is restricted by the circuit of the mediation station. However, if this restriction is removed, the control / monitor signal transmission system can be further expanded in applicability, shortening the design time and ensuring mass productivity, easy to handle, and easy to change the system. It was. Then, it was found that by improving the structure of the intermediary station with the degree of freedom of correspondence between the input unit and the output unit, it is possible to make a system that is cheaper to handle than conventional methods and has an improved degree of freedom.

  Therefore, the present invention has a drawback in that a change in the number of inputs and outputs is restricted by a circuit in a control / monitor signal transmission system using an intermediary station that superimposes a monitor signal and a control signal on a clock signal on which a power source is superimposed. Therefore, an object of the present invention is to provide a control / monitoring signal transmission system that is easy to use and has an intermediary station having a structure having a degree of freedom of correspondence between an input unit and an output unit.

A control / monitoring signal transmission system according to the present invention is connected to a plurality of actuators each including an actuator unit and a sensor unit that monitors the actuator unit by a common data signal line provided corresponding to the plurality of actuators. And a mediation station connected to the data signal line. The operating device in the present invention corresponds to a controlled device in a conventional control / monitor signal transmission system. Further, the actuator unit of the present invention does not have to perform movement such as expansion and contraction and bending as long as it performs an operation intended by the user. For example, in addition to a solenoid, a relay, a solenoid valve, a lamp, etc. Is also included.
The plurality of actuators are divided into one or a plurality of groups including at least two, and those belonging to the same group are in a correspondence relationship.
The intermediary station extracts the monitoring data from the monitoring signal transmitted from the sensor unit via the slave station, and another operation corresponding to the operating device including the sensor unit that has transmitted the monitoring data. It is sent as control data to the device.
When the monitoring data is extracted, another monitoring data already stored in the storage area of the mediation station is sent out as the control data, and then overwritten in the storage area.

  The intermediary station may have a buffer area, and the monitoring data may be transferred from the buffer area to the storage area after being stored in the buffer area.

  The overwriting storage may be executed for each minimum unit of the monitoring data. Alternatively, the overwriting storage may be executed for each block in which a predetermined number of minimum units of the monitoring data are collected.

  The monitoring data signal may have an output period in which data is output from the mediation station to the actuator, and an input period in which data is input from the actuator to the mediation station.

  The control data is sent following a start signal indicating the start of transmission, and the slave station starts from the start signal based on the start signal and a clock signal constituting the control data, and sequentially by the clock signal. The address counter may be updated to synchronize transmission.

  The present invention enables simplification of simple control of immediate input / output by improving the function of the mediation station. That is, according to the present invention, in the control / monitor signal transmission system, a storage area is provided in the mediation station. The mediation station extracts the monitoring data from the monitoring signal sent to the common data signal line, stores the monitoring data in the storage area of the mediation station, and sends the stored monitoring data as control data. Therefore, it is possible to improve the structure having a degree of freedom in associating the input unit and the output unit, and it is easier to handle than the conventional method, and a system with an improved degree of freedom has been achieved. The monitoring data in the storage area is overwritten with new monitoring data whenever it is sent out as control data. The overwriting storage is performed every minimum unit of monitoring data (every clock). It may be executed for each block in which a predetermined number of minimum units of monitoring data are collected, for example, for each cycle of control data. Further, a buffer area may be provided in the mediation station, and the monitoring data may be transferred from the buffer area to the storage area after being stored in the buffer area. By defining the exchange of data in the storage area and setting the timing for overwriting or transferring the input data to the storage area, the change in the number of inputs and outputs can The shortcomings restricted by the circuit were solved, and a system that was easier to use was created. Furthermore, the regularity of the signal transmission from the input unit to the output unit has also been solved with the drawback of being restricted by the circuit of the mediation station. In this way, an easy-to-handle control / monitor signal transmission system having a wide range of applicability, ensuring design time reduction and mass productivity was obtained. And it was possible to reduce the system cost by simplifying the transmission system, reduce the design cost, simplify the wiring, and simplify the assembly work.

  The overwriting storage and transfer timing of the monitoring data can be set more effectively by optimizing the data transmission / reception method. Specifically, the monitoring data signal has an output period in which data is output from the mediation station to the actuator, and an input period in which data is input from the actuator to the mediation station. With the above bidirectional communication, it becomes possible to handle a larger number of devices by increasing the communication speed. That is, the number of inputs and outputs can be increased, and the degree of freedom of correspondence can be increased.

  Furthermore, the control data is sent out following the start signal indicating the start of transmission, and the slave station starts from the start signal based on the start signal and the clock signal constituting the control data, and the address counter sequentially by the clock signal. If it is assumed that transmission synchronization is performed by updating the I / O, it is possible to easily cope with increase / decrease in input / output only by changing the address. Therefore, the degree of freedom in handling input and output can be further increased.

  Also in the present invention, by providing an intermediary station instead of the control unit and the master station, it is simple, small-scale, easy to maintain and inexpensive, and remote control is performed without using the control unit or the master station. As a result, it is possible to obtain the effect of the conventional control / monitoring signal transmission system in which a high-speed transmission control can be realized without causing a control delay due to a scanning time inside the control unit or the master station.

  Examples of the embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a basic configuration diagram of an entire control / monitor signal transmission system according to an embodiment of the present invention, FIG. 2 is a functional block diagram of an intermediary station, and FIG. 3 is a schematic diagram of a transmission signal form in a storage area.

  As shown in FIG. 1, this control / monitor signal transmission system is connected to a single mediation station 1 through a DP signal line 8 and a DN signal line 9 which are data lines common to the mediation station 1. A plurality of slave stations 4 and a plurality of actuating devices 5 connected to each of the plurality of slave stations 4 are provided.

  The actuating devices 5 are divided into one or a plurality of sets including at least two, and those belonging to the same set are in a correspondence relationship. For example, if five operating devices are installed at each of points A and B, if one operating device at point A and one operating device at point B are taken as one set, it can be divided into five groups. In addition, a pair of each pair is in a correspondence relationship. For each group, if an address described later, for example, 0 to 5 is given, the addresses of the operating devices in the correspondence relationship are the same. In addition to the points A and B, for example, when five operating devices are installed at the C point, the operating devices installed at the respective points A, B, and C can be obtained by combining three units. Is the corresponding relationship.

  In addition, the operating device 5 includes an actuator unit 6 and a sensor unit 7 that monitors the actuator unit 6. The actuator unit 6 is composed of various components constituting the operating device 5, such as a solenoid, a relay, a solenoid valve, a lamp, and the like. The sensor unit 7 is selected according to the corresponding actuator unit 6 and includes, for example, a phototransistor, a push button switch, and the like, and inputs an on / off state (binary signal). However, the signal input from the sensor unit 7 is not limited, and a binary or higher signal may be input.

  A control signal is transmitted to the actuator unit 6 via the slave station 4 via the DP signal line 8 and the DN signal line 9 to the plurality of actuators 5. A monitoring signal (sensor signal) from the sensor unit 7 is transmitted through the slave station 4 via the DP signal line 8 and the DN signal line 9. The monitoring signal and the control signal transmitted on the DP signal line 8 and the DN signal line 9 are serial signals. As will be described later, between the DP signal line 8 and the DN signal line 9, the supply of the power supply voltage Vx, the supply of the clock signal CK, and the (virtually) bidirectional transmission of the monitoring signal and the control signal are performed. Used.

  The plurality of slave stations 4 are provided corresponding to the plurality of actuating devices 5, are connected to the DP signal line 8 and the DN signal line 9 at arbitrary positions, and are connected to the corresponding actuating devices 5. Each of the plurality of slave stations 4 includes a slave station output unit 2 and a slave station input unit 3, and the slave station output unit 2 and the slave station input unit 3 correspond to the actuator unit 6 and the sensor unit 7, respectively. The monitoring signal and the control signal input to and output from the slave station input unit 3 and the slave station output unit 2 are multi-bit parallel signals. The slave station output unit 2 performs serial / parallel conversion on the control signal, and the slave station input unit 3 performs parallel / serial conversion on the monitoring signal.

  The mediation station 1 is connected to a plurality of slave stations 4 via a DP signal line 8 and a DN signal line 9. This intermediary station 1 does not take in a control signal from a control unit or send a monitoring signal to the control unit unlike a master station in a known control / monitoring signal transmission system. 5 is merely transmitted as a control signal to another actuating device 5 (actuator unit 6 thereof) associated in advance with a monitoring signal transmitted from (sensor unit 7). It has a different configuration (see FIG. 2). Therefore, the monitoring signal from the sensor unit 7 taken into the slave station input unit 3 at the point B is determined in advance via the DP signal line 8 and the DN signal line 9 as in the data signal flow indicated by the broken line. Is output to the actuator unit 6 of the actuator 5 via the slave station output unit 2 at the point A. On the other hand, the monitoring signal captured from the sensor unit 7 to the slave station input unit 3 of the slave station 4 at the predetermined point A is passed through the DP signal line 8 and the DN signal line 9 to be a predetermined point B. Is output to the actuator unit 6 of the actuator 5 via the slave station output unit 2. Therefore, in this control / monitor signal transmission system, it is possible to build a control system without requiring a host computer or PLC (programmable logic controller).

  The control / monitor signal transmission system does not include a power line P (24V power line and 0V power line) and a local power supply for supplying the power supply voltage Vx to each of the plurality of slave stations 4. As will be described later, power is supplied to the plurality of slave stations 4 by a power signal superimposed on the clock signal. The power capacity of the power signal is such that each of the plurality of slave stations 4 can sufficiently operate.

  The intermediary station 1 includes a transfer circuit 10, an intermediary station output unit 15, an intermediary station input unit 18, an oscillator (OSC) 11, and a timing generation unit 13. The timing generation unit 13 generates a predetermined timing signal synchronized with the clock CK having a predetermined period t0 based on the oscillation output output from the oscillator 11.

  The mediation station input unit 18 includes monitoring signal detection means 19 and monitoring data extraction means 20. The monitoring signal detection means 20 takes in a serial pulse voltage signal transmitted over the DP signal line 8 and the DN signal line 9, and detects and outputs a monitoring data signal superimposed thereon. The monitor signal detection means 19 outputs this detection output to the transfer circuit 10 in synchronization with the clock CK from the timing generation means 13 (waveform shaping). As the transfer circuit 10, an MCU (microcomputer control unit) is suitable, and in most practical forms, an MCU is considered to be adopted. Therefore, the transfer circuit is hereinafter referred to as MCU.

  The mediation station output unit 15 includes control data signal generation means 14 and a line driver 23. The line driver 23 is connected to a power supply means 21 for generating a predetermined level of the power supply voltage Vx. The control data signal generation unit 14 superimposes each data value of the serial data string input from the data monitoring data extraction unit 20 to the MCU 10 on the clock CK. The output of the control data signal generating means 14 is output on the DP signal line 8 and the DN signal line 9 as a serial signal including a power supply voltage via a line driver 23 which is an output circuit. As will be described later, the clock CK including the power supply voltage is level-converted and output to the terminals 16 and 17 and supplied to the DP signal line 8 and the DN signal line 9. That is, it is output as a relative potential difference between the two.

  The MCU 10 includes a storage area 12. As shown in FIG. 3, the storage area 12 is composed of an input data area (IN-DATA, corresponding to the buffer area of the present invention) and an output data area (OUT-DATA). The monitored data is stored in IN-DATA. Note that the input data area may be a separate device from the storage area 12. The data stored here is written (overwritten) in OUT-DATA every clock or every cycle of transmission data (each block). Note that after the writing to the OUT-DATA is completed, the IN-DATA data is rewritten with new input data. The data written to OUT-DATA is output to the slave station 4 via the mediation station output unit 15 via the DP signal line 8 and the DN signal line 9. Therefore, in this control / monitor signal transmission system, the input signal (monitor signal) from the sensor unit 7 and the output signal (control signal) to the actuator unit 6 are made to correspond one-to-one.

  For example, four addresses 0 to 3 of the actuating device 5 at the point A are allocated, and a 4-bit monitoring signal “0011” is supported from the sensor unit 7 (actually, the corresponding slave station input unit 3). A case where the data is output to the slave station input unit 3 of the slave station 4 to be performed will be described. In this case, first, the slave station input unit 3 superimposes the monitoring signal “0011” on the positions of the addresses 0 to 3 of the clock CK, and as shown by dotted lines in FIG. Output above. Then, the mediation station input unit 18 of the mediation station 1 extracts the monitoring signal “0011” and inputs it to the MCU 10 as the control signal “0011”. In the MCU 10, the control signal “0011” is stored in IN-DATA addresses 0 to 3 in the storage area 12. Then, it is rewritten to OUT-DATA addresses 0 to 3 and input to the mediation station output unit 15. The mediation station output unit 15 outputs the signal on the DP signal line 8 and the DN signal line 9 by superimposing them at the same addresses 0 to 3 as the address from which the control signal “0011” is extracted. Then, at the point B remote from the point A, the slave station output unit 2 corresponding to the actuator unit 6 to which the addresses 0 to 3 are assigned is superimposed on the positions of the addresses 0 to 3 as indicated by dotted lines in FIG. The control signal “0011” is extracted and output to the corresponding actuator unit 6. As a result, signal input / output is performed between the slave station 4 at the point A and the point B where the address of the slave station input unit 3 and the address of the slave station output unit 2 match.

  After this, for example, the monitoring signal, for example, “0101” from the sensor unit 7 provided with a different address of the B point (not limited to this, but may be the C point), for example, the addresses 4 to 7, corresponds to the child. When the signal is output to the station output unit 2, the slave station input unit 3 superimposes the monitoring signal on the positions of the addresses 4 to 7 of the clock CK, and as shown by the dotted line in FIG. Output on line 9. In the mediation station 1, the mediation station input unit 18 extracts the monitoring signal and inputs it to the MCU 10 as a control signal. In the MCU 10, the control signal “0101” is stored in IN-DATA addresses 4 to 7 in the storage area 12. Then, it is rewritten to OUT-DATA addresses 4 to 7 and input to the mediation station output unit 15. The mediation station output unit 15 superimposes the control signals on the positions of the addresses 4 to 7 and outputs them on the DP signal line 8 and the DN signal line 9. The slave station output unit 2 at the point A to which the addresses 4 to 7 are assigned extracts the control signal superimposed at the position of the addresses 4 to 7 as in the case of the addresses 0 to 3 above. Output to the actuator unit 6.

  In this way, one cycle of control / monitor signal transmission (for example, a predetermined address 0 to 31 or a start signal ST to an end signal END) is executed. Furthermore, signal transmission is repeated in units of this one cycle.

  However, the correspondence between the input signal and the output signal is not limited to the above-described one-to-one, and the correspondence can be variously changed. For example, when an input signal from the slave station input unit 3 at the point A is given as an output signal to the slave station output unit 2 at the point B, as described above, the input signal from the slave station input unit 3 at the point B is A In addition to being provided as an output signal to the slave station output unit 2 at the point, an input signal from the slave station input unit 3 at the B point may be provided as an output signal to the slave station output unit 2 at the C point. Further, an input signal from the slave station input unit 3 at the point A may be given as an output signal to the slave station output unit 2 at the points B and C.

  In the transmission of this control / monitor signal transmission system, a signal from the slave station input unit 3 having a certain address is transmitted to the slave station output unit 2 having the same address within the same cycle of the clock CK. That is, the address of the monitoring signal (input address) and the address of the control signal (output address) in the transmission cycle are the same (hence, referred to as an input / output address). Thus, the output signal can be transmitted (supplied) to the corresponding slave station 4 (with the same address) only by giving the input signal to the slave station 4. A specific circuit configuration for realizing such a transmission method is shown below.

  4 is a functional block diagram of the slave station output section, slave station input section and actuator, FIG. 5 is a functional block wiring diagram of the slave station input section, FIG. 6 is a block wiring diagram of the slave station output section, and FIG. 8 is a time chart of the control / monitor signal transmission system, FIG. 9 is a time chart of the slave station input unit, FIG. 10 is a time chart of the slave station output unit, and FIG. FIG.

  First, the slave station input unit 3 will be described. As shown in FIGS. 4 and 5, the slave station input unit 3 includes a power supply voltage generation means (CV) 300, a line receiver 301, a control data signal extraction means 302, a slave station address setting means 303, an address extraction means 304, and an input. A data unit 305, a monitoring data signal generation unit 306, and a line driver 307 are provided.

  The power supply voltage generation means 300 electrically drives a circuit constituting the slave station input unit 3 and electrically drives the sensor unit 7 of the corresponding operating device 5, that is, an output Vcg ( 19V) and an output Vcp (24V) from a DP signal line 8 and a DN signal line 9 are DC (direct current) -DC converters. By smoothing and stabilizing the voltages of the DP signal line 8 and the DN signal line 9 by a known means, a stabilized output Vcg (19V) is obtained, and an output Vcp (24V) is formed by the diode D0 and the capacitor C0. Note that the period of the pulse width modulated clock on the DP signal line 8 and the DN signal line 9 is set so that the output Vcp can be sufficiently maintained at 24V. The slave station input unit 3 operates between the output Vcg (19V) and the output Vcp.

  The line receiver 301 includes divided resistors R1 and R2 having the same resistance value and a buffer circuit B. The potential difference Vs between the DP signal line 8 and the DN signal line 9 is detected, and a signal obtained by dividing the potential difference by two by the dividing resistors R1 and R2 is output from the buffer circuit B. That is, when the potential difference between the DP signal line 8 and the DN signal line 9 is 24V, the diode D0 is turned on by the potential of 24V of the DP signal line 8, the capacitor C0 is charged to the potential difference, and the output Vcp = 24V is 24V of the DP signal line 8 is applied to one end of the resistor R1 and one end of the resistor R2. Therefore, there is no potential difference between both ends of the resistors R1 and R2. On the other hand, when the potential difference changes to 19V, the diode D0 is turned off, and the potential of Vcp based on the potential of the DN signal line 9 is maintained at 24V by the capacitor C0, but the DP signal line is connected to one end of the resistor R2. 8 19V is given. Therefore, a potential difference of 5 V is given between both ends of the resistors R1 and R2, and a value obtained by dividing this by two is input to the buffer circuit B. Note that this is due to the overall potential shift, and the relationship between the output Vcp (24 V), which is the reference potential, and the output Vcg (19 V) does not change.

  Thus, in the circuit of the slave station input unit 3, the capacitor C0 is inserted in parallel between the DP signal line 8 and the DN signal line 9, and further, the DP signal line 8 side terminal of the capacitor C0 and the DP signal line. 8 is equivalent to the insertion of a diode D0. Therefore, during the period in which the potential difference between the DP signal line 8 and the DN signal line 9 is the power supply potential Vx = 24 V, a charging current flows from the DP signal line 8 to the DN signal line 9 via the diode D0, and the capacitor C0 While charging, the circuits of the slave station 4 and the actuator 5 are driven. On the other hand, during the period in which the potential difference (Vx−Vs) is 19V, the diode D0 is turned off and the current for charging the capacitor C0 does not flow (cut off) from the DN signal line 9 to the DN signal line 9. Therefore, during the period when (Vx−Vs) is 19V, the capacitor C0 is discharged to drive the circuits of the slave station 4 and the actuator 5 and, as will be described later, when the monitoring data signal is “1”, for example, Superimpose the current signal. That is, the current Iis that is “1” of the monitoring data signal is output to the DN signal line 9.

  Considering a control signal (serial pulse voltage signal) on which the clock CK is superimposed, the buffer circuit B outputs a high level signal when the potential difference is 24 V, and outputs a low level signal otherwise. This is the output do. That is, the data value of the demodulated control signal. This may be considered to include a phase modulated clock CK. This output do is input to a preset addition counter (hereinafter referred to as preset addition counter 304), which is an address extraction means 304, and its inverted signal is input to the shift register SR. The waveform of the output do will be described later.

  Prior to the input of the extracted clock CK, the start signal ST superimposed on the control signal is similarly detected as the high level of the output do and input to the on-delay timer Ton. The waveforms of the start signal ST and the output st will be described later. In this on-delay timer Ton, the delay is 3t0 (t0 is one cycle of the clock CK), that is, the rising edge of the output st is delayed by 3t0 and falling. Is synchronized with the original signal ST. Therefore, the output st does not appear for a signal having a short high level time, that is, a clock CK or an end signal END described later. The output st is input to the differentiating circuit, and the differential signal is input to the preset addition counter 304 and the shift register SR at the rising edge of the output st, and used as the reset signal R. Note that an output do is also input to these.

  The address assigned to the slave station input unit 3 is set in the setting unit switch of the slave station address setting unit 303. With this address, for example, if the slave station 4 is provided at the point A in FIG. 1 (FIG. 1) and addresses 0 to 3 are assigned, these addresses are set. However, in FIG. 7, address 0 is shown for convenience of illustration. The preset addition counter 304 is reset by the rising differential signal of the output st, then counts the extracted clock CK at the rising edge, and while the count value matches the address of the setting unit switch, Output dc is output.

  The input data unit 305 holds a monitoring signal composed of one or a plurality of (bit) data values input from the corresponding sensor unit 7 and holds when an output dc from the preset addition counter 304 is input. The value of one or a plurality of data is output to the monitoring data signal generation means 306 as a serial signal in a predetermined order. That is, the input data unit 305 performs parallel / serial conversion on the monitoring signal. The monitoring data signal generation means 306 outputs a monitoring data signal according to the value of the monitoring signal data. The monitoring data signal output here is output from the DP signal line 8 and the DN by the line driver 307 as an output circuit. The signal is output on the signal line 9.

  The input data unit 305 has a shift register SR in its configuration. The shift register SR of the input data unit 305 shifts “1 (or high level)” in synchronization with the falling edge of the extracted clock CK during the period when the output dc is at high level. That is, “1” is shifted in this order in the unit circuits Sr1 to Sr4 of the shift register SR. Accordingly, the outputs dr1 to dr4 of the shift register SR are sequentially set to the high level (until the fall of the next period) in synchronization with the fall of the clock CK. Each of the outputs dr1 to dr4 is input to four 2-input AND gates.

  The AND gate section of the input data section 305 has the same number of 2-input AND gates as the assigned addresses (for example, the above-described addresses 0 to 3) (four addresses when the addresses are 0 to 3), and their outputs. OR gate receiving. The outputs dr1 to dr4 of the shift register SR are input to each of the four AND gates. As described above, the outputs dr1 to dr4 are sequentially set to the high level in synchronization with the fall of the clock CK period (until the fall of the next period). Therefore, during the period when the outputs dr1 to dr4 are at the high level, each of the four AND gates opens, and the monitoring signal (sensor unit 7 represented by the switch SW0 or the like representatively to be superimposed on the addresses 0 to 3). The signal based on the input of the signal “0” or “1” depending on the state of (1) is output from the OR gate through the AND gate in this order.

  The output of the OR gate is input to the 2-input NAND gate 308. An output of the inverter INV, that is, an inverted signal of the output do is input to the NAND gate 308. NAND gate 308 constitutes monitoring data signal generating means 306. Then, the NAND gate 308 opens in synchronization with the fall of the output do during the period when the monitoring signal of the address set in the setting unit switch is output, and the signal value depending on the state of the sensor unit 7 For example, a monitoring signal adopting “0011” or the like is output as an output dip.

  The output dip is level-converted via the line driver 307 and then output to the DP signal line 8 and the DN signal line 9. The line driver 307 includes transistors T1 and T2, a diode D, and resistors R3, R4, and Ris. The output dip is input to the large transistor T2 via the transistor T1. That is, when the monitoring data signal is “1”, for example, the transistor T2 is turned on by the low level of the output dip, and the current Iis that is the monitoring data signal flows through the DP signal line 8 and the DN signal line 9. Thereby, the current signal Iis which is “1” of the monitoring data signal is superimposed on the signal line DN signal line 9. Further, the current flowing through the transistor T2 is limited by appropriately selecting the resistors R3, R4, and Ris. For example, it is limited to 30 mA (milliamperes).

  As can be seen from the above, the monitoring signal is output from the slave station input unit 3 as a current signal on the DP signal line 8 and the DN signal line 9 in one cycle of the signal do (the extracted signal). (Superimposed). At this time, as described above, in the period in which the potential difference (Vx−Vs) between the DP signal line 8 and the DN signal line 9 is 19 V, the diode D0 is turned off and the DP signal line 8 to the DN signal line 9 are turned off. No current flows to charge the capacitor C0. Therefore, the charging current from the mediation station 1 does not collide with the monitoring data signal, and the monitoring data signal is the data of the control signal output on the DP signal line 8 and the DN signal line 9 at that time. Is superimposed on the value of. That is, the monitoring data signal is superimposed on the data position corresponding to the slave station 4 of the serial pulse voltage signal. In other words, since the monitoring signal data of the same address is superimposed on the control signal of the same address, the monitoring signal address (input address) and the control signal address (output address) in the transmission cycle are It will be the same.

  Next, the circuit configuration of the slave station output unit 2 will be described. As shown in FIGS. 4 and 6, the slave station output unit 2 includes a power supply voltage generation means (CV) 200, a line receiver 201, a control data signal extraction means 202, a slave station address setting means 203, an address extraction means 204, and an output. A data unit 205 is provided. Note that the power supply voltage generating means (CV) 200, the line receiver 201, the control data signal extracting means 202, the slave station address setting means 203, and the address extracting means 204 are the power supply voltage generating means 300 in the slave station input section 3 described above. Since the configuration is substantially the same as that of the line receiver 301, the control data signal extraction unit 302, the slave station address setting unit 303, and the address extraction unit 304, the description thereof will be simplified. For example, if the assigned address is the slave station output unit 2 at point B described above, it is the same as the slave station input unit 3 at point A (that is, in this case, addresses 0 to 3). Further, the same number of monitoring signal data as the number (4) of control signal data to be extracted is input.

  The power supply voltage generation means (CV) 200 generates a power supply voltage of a certain level from the data signal line, like the slave station input unit 3n power supply voltage generation means 300. That is, by smoothing and stabilizing the voltages of the DP signal line 8 and the DN signal line 9 by known means, stabilized outputs Vcg (19 V) and Vcp (24 V) are obtained. The output Vcg (19 V) is a power supply voltage of 5 V (corresponding to Vcc) when the output Vcp (24 V) is used as a reference voltage. This power supply voltage electrically drives a low power consumption circuit (for example, an LED display circuit) associated with the slave station output unit 2 and electrically drives the actuator unit 6 of the corresponding actuator 5. Used to do. That is, although not shown, the power supply voltage generating means 200 supplies the power to the actuator unit 6.

  The line receiver 201 as an input circuit takes in signals transmitted on the DP signal line 8 and the DN signal line 9 and outputs them to the control data signal extraction unit 202. The control data signal extraction unit 202 extracts a control data signal from the signal and outputs it to the address extraction unit 204 and the output data unit 205. The slave station address setting means 203 holds the local station address assigned to the slave station output unit 2. The address extracting unit 204 extracts an address that matches the local station address held in the slave station address setting unit 203 and outputs the extracted address to the output data unit 205. When an address is input from the address extraction unit 204, the output data unit 205 stores one or a plurality of signals held at that time in a (serial) signal transmitted over the DP signal line 8 and the DN signal line 9. Is output to the corresponding actuator unit 6 as a parallel signal. That is, the output data unit 205 performs serial / parallel conversion on the control signal.

  The line receiver 201 includes a buffer circuit B like the line receiver 301 of the slave station input unit 3, and outputs a signal do whose level changes according to the potential difference between the DP signal line 8 and the DN signal line 9. The signal do is input to the on-delay timer Ton and the off-delay timer Toff. The off-delay timer Toff outputs only the off (low level) period with a predetermined delay. That is, the falling edge of the input do is delayed, and the rising edge is synchronized with the original input do. The delay is 1 / 2t0 (t0 is one cycle of the clock CK). Although the waveform of the signal d1 will be described later, an output corresponding to the data value (“0” or “1”) of the control data signal is performed. Since the on-delay timer Ton is the same as that of the slave station input unit 3, the description thereof is omitted.

  The outputs dr1 to dr4 of the shift register 204 are set to the high level in order (until the rise of the next cycle) in synchronization with the rise in the cycle of the clock CK, unlike those of the slave station input unit 3. Outputs dr1 to dr4 are input as clocks to D-type flip-flop circuits FF1 to FF4 constituting output data unit 205, respectively. The output d1 (that is, the demodulated control signal data value) is also input to the flip-flop circuits FF1 to FF4. For example, the flip-flop circuit FF1 captures and holds the value of the output d1 at that time in synchronization with the rise of the output dr1, and outputs this as the signal out0. Similarly, the other flip-flop circuits FF2 to FF4 capture and hold the value of the output d1 at that time in synchronization with the rise of the outputs dr2 to dr4, and output them as signals out1 to out3.

  The outputs out0 to out3 are respectively inverted and then output as outputs O0 to O3 to the actuator unit 6 of the actuator 5 via the large driving transistors T0 to T3 whose emitters are connected to the capacitor C0. L0 etc. are controlled. As described above, power to the load L0 and the like is supplied from the slave station output unit 2.

  Next, the mediation station input unit 18 will be described. The monitoring signals output on the DP signal line 8 and the DN signal line 9 are input to and detected by the monitoring signal detection means 19 of the mediation station input unit 18, and the detection signal is inverted and output as output Diip. The waveform of the output Dip includes the monitoring data signal (only). In this output Diip, the monitoring signal data corresponding to the monitoring signal data address position exists at an address position delayed by one from the control signal data address position.

  The monitoring signal detection means 19 includes a transistor Ti, which is a current detection circuit that detects and outputs a current change on the DP signal line 8 and the DN signal line 9, and Zener diodes ZD1 and ZD2, and resistors R1, R2, and Ri. The Zener diode ZD1 whose breakdown voltage is 4.5V and the resistor R1 limit the amplitude to 5V = Vs. That is, during the period in which the potential difference (Vx−Vs) between the DP signal line 8 and the DN signal line 9 is 19 V, the current for charging the capacitor C0 from the DP signal line 8 to the DN signal line 9 is as described above. The detection current Is flows to the monitoring signal detection means 19 without flowing. At this time, when the monitoring data signal is “1”, the current Iis is superimposed. Therefore, the current Iis = 30 mA flows as the detection current Is of the monitoring data signal. The transistor Ti detects this current Is. Zener diode ZD2 breaks down when a current of 15 mA or more flows. This is the threshold value Ith for detecting the current Is. Therefore, the transistor Ti is turned on by the detection current Is = 30 mA based on the monitoring data signal “1”. When the monitoring data signal is “0”, since the current Iis does not flow, the detection current Is of the monitoring data signal does not flow. Therefore, the Zener diode ZD2 does not breakdown, and the transistor Ti is turned off by the monitoring data signal “0”.

  The detection current Is (= 30 mA), which is the monitoring data signal “1”, is converted into a voltage signal by a voltage drop in the collector resistance Ri, and is input to the monitoring data extraction means 20. Based on the detection current Is, an output Diip is formed by the inverter INV and input to the RS flip-flop FF of the monitoring data extraction means 1310. Further, the output Diis of the flip-flop FF is input to the storage area 12 of the MCU 10.

  The control data signal generator 14 outputs a binary (5V high level and 0V low level) signal to one signal line Pck. The signal output to the signal line Pck is output to the DP signal line 8 and the DN signal line 9 via the line driver 23. The line driver 23 is composed of a large transistor Td for supplying a charging current for the capacitor C0, and can be driven with a low impedance. The amplitude of the output is limited to 0V to 5V by the Zener diode ZD1 (4.5V breakdown voltage), and an inverted signal of the signal line Pck is output onto the DN signal line 9. The DP signal line 8 is supplied with the power supply potential Vx = 24V. Therefore, the signal between the DP signal line 8 and the DN signal line 9 is a binary signal (level Vx and “high potential low level”). In addition, a start signal ST described later is output as a signal having the level of the power supply potential Vx, and the end signal END is output as a signal having a “high potential and low level”.

Next, input / output waveforms in the mediation station 1 will be described.
A signal Dck shown in FIG. 11 is a clock CK (a signal formed by dividing the oscillation output from the oscillator (OSC) 11 in the mediation station 1 and formed in a predetermined cycle), continuously to the start signal ST, and thereafter. Output is started in synchronization with the fall, and a predetermined number (the number of addresses) is output.

  In this embodiment, the control signal to be distributed to the plurality of slave stations 4 is transmitted on the data signal line as a serial signal (serial pulsed voltage signal) from one intermediary station 1. An address count method is used. That is, the total number of control data signal data to be transmitted (distributed) to the slave stations 4 can be known in advance. Therefore, one address is assigned to each data of all control data signals. However, the number of addresses is not limited and may be 0 to 32, 0 to 63, 127, 255,. For example, if the address is from 0 to 31, a 32-bit control signal is output.

  As described above, the slave station 4 extracts the clock CK from the serial pulsed voltage signal, counts the number thereof, and the address (one or more) assigned to the data of the control data signal to be received by the local station In this case, the data value of the serial pulse voltage signal at that time is taken as a control signal. Note that the final address is also assigned to the mediation station 1 in order to form an end signal described later.

  Then, a start signal ST and an end signal are formed to determine the first and last for counting the address, respectively. The start signal ST and the end signal END are output by the timing generation means 13 of the mediation station 1. That is, prior to the output of the serial pulsed voltage signal, a start signal is formed and the start signal ST is output to the DP signal line 8, and the clock CK extracted from the serial pulsed voltage signal is counted and assigned to itself in advance. When the received address is extracted, the end signal END is output to the DP signal line 8 at that time. For this purpose, the timing generating means 13 includes a counting means (not shown).

  The counting means starts counting at the rising edge of the start signal ST. When the count output of the counting means reaches a predetermined value, the output of the clock CK is stopped. The end signal END is output continuously after detecting a predetermined number (number of addresses) of clocks CK. For this purpose, the timing generation means 13 also includes comparison means (not shown). That is, the comparison means sets the address of the mediation station 1 by the counting means. Then, the address of the intermediary station 1 and the count value are compared, and if they match, an end signal END is output for a predetermined period. The counting means is reset by the end signal END. Further, in synchronization with the end of the end signal END, the start signal ST is output again, and the same operation is repeated. A numerical value corresponding to the number of data transmitted in one transmission cycle (from one start signal ST to the end signal END immediately thereafter) is the maximum value of the address. For example, in the case of a 32-bit control signal, 31 which is the maximum address count value becomes the address of the mediation station, and an end signal END is output at the end of data processing at address 31 in the control signal.

  The start signal ST is a signal longer than one cycle t0 of the clock CK so as to be distinguishable from the control signal, and the end signal is a signal longer than one cycle t0 of the clock CK and shorter than the start signal. The start signal ST in this embodiment is a 24V (high level) signal output for a period of 5t0. On the other hand, the end signal END is a high level signal output for a period of 1.5 t0.

  However, since the start signal ST and the end signal END are signal definitions, they can be identified by specific data. Although not shown, in the case of a 4-bit address, the start signal ST can be defined using 1111 data as start data, and the 1110 data can be defined as an end signal END that is end data.

  Further, the data signal in this embodiment is 19V (“high potential low level” in this specific example, which may be simply referred to as “low level”) in the 3/4 period (3 / 4t0) before the clock CK1 period t0. The latter 1/4 cycle (1 / 4t0) is set to the high level, the previous 1/4 cycle (1 / 4t0) is set to the low level, and the subsequent 3/4 cycle (3 / 4t0) is set to the high level. The former indicates the value “0” and the latter indicates the value “1”. An address (input / output address) is assigned for each data value (one period (t0) of the clock CK). For example, in FIG. 11, when the data value of the signal Pck output from the control data generating means 14 is “0011”, the addresses (0 and 1) where the data value is “0” The ¾ cycle is “low level”, and the ¼ cycle after the clock is the level (high level) of the power supply voltage Vx. Further, in the addresses (2 and 3) where the data value is “1”, the ¼ period before the clock is “low level” and the ¾ period after the clock is high. That is, the duty ratio of the clock is changed according to the data value of the control data signal. As a result, the control data signal to be paralleled is output to the DP signal line 8 and the DN signal line 9 as a serial pulse voltage signal for output to the actuator unit 6.

  However, the low level width of the data signal (pulse width of pulse width modulation) can be variously selected. For example, contrary to the above example, when the data value is “0”, the pulse width is shortened (1 / 4t0), and when the data value is “1”, the pulse width is lengthened (3 / 4t0). You may do it.

  The signal of the output Dick serves as a detection trigger. Under the control of the timing signal, the mediation station input unit 18 uses the monitoring data signal superimposed on the serial pulse voltage signal transmitted through the data signal line as the presence / absence of the current signal Iis for each cycle of the clock CK. To detect. For this purpose, the timing generation means 13 forms an output Dick signal that triggers the detection. The signal of the output Dick is a pulse whose rising edge is delayed from the clock CK by a quarter cycle (1 / 4t0). Thereby, the value of each data in the serial monitoring signal is extracted, converted into a monitoring signal, and input to the control data signal generating means 20. That is, the presence / absence (on / off) of the monitoring signal is detected at the rising timing of the output Dick, in other words, at the timing when ¼ t0 in one cycle of each clock CK has elapsed. At this timing, if the current Iis, which is a monitoring signal, is smaller than Ith, it is OFF (“binary signal”) or “0”, and if it is larger, it is “ON” (binary signal) or “1”. Here, Ith is a threshold current of the monitoring signal detecting means 19, and Iis is a monitoring data signal. Ith is smaller than Iis.

  Therefore, for example, when the data value of the monitoring data signal is “0011”, the output (detection current Is) of the monitoring signal detection means 20 is an address (2 and 3) having the data value “1” as shown in FIG. ), The current Iis becomes a signal larger than Ith in the first 1 / 4t0 cycle.

  If the monitoring signal is OFF at this timing, that is, when ¼ t0 in one cycle of each clock CK has elapsed, the output signal of the signal line Pck (therefore, the DP signal line 8 and the DN signal line 9). Output pulse) ("low level", that is, a period of 19V) is increased, that is, the remaining period of the cycle is also set to "low level". As a result, the pulse width is set to 3 / 4t0. On the other hand, if the monitoring signal is on (Iis is 25 mA or more) at the timing, the pulse width is shortened, that is, the remaining period of the cycle is set to the power supply potential Vx (high level). The pulse width modulation of the control signal Pck is performed with 1 / 4t0.

  The output Diis is monitoring data stored in the storage area 12 in the MCU 10 and is output from the RS flip-flop FF of the monitoring data extraction unit 20. The flip-flop FF receives from the timing generating means 13 a signal of the output Dick (a pulse delayed from the clock CK by a ¼ period (1 / 4t0)) as its clock. Therefore, the output Diis of the flip-flop FF outputs the value of only the monitoring data signal for a period equal to 3/4 period of the clock CK at a timing delayed by 1/4 period from the original clock CK. That is, the output Diis is set to a high level (or “1”) or a low level (or “0”) every clock according to the data value of the monitoring signal. Thus, for example, “0011...” Is output.

  The clock 4CK is formed by the timing generation means 13 by dividing the oscillation output of the oscillator 11, and its frequency is four times (4f0) the frequency f0 of the clock CK. The control data signal generating means 14 counts the clock 4CK with a counter (not shown), and when the value of the control signal (the signal of the output Diis) is “1”, one of the first clocks 4CK is placed on the DP signal line 8. "High potential low level" is output in the cycle, and the high level Vx is output in the remaining three clocks 4CK. On the other hand, in the case of “0”, “high potential low level” is output in the period (3 / 4t0) for the first three clocks 4CK, and the high level Vx is output in the period of the remaining one clock 4CK. Output. As a result, the control data signal generating means 14 modulates (PWM) the clock CK based on the control signal.

Next, input / output waveforms in the slave station input unit 3 will be described.
As shown in FIG. 9, the signal waveform of the output do from the buffer circuit B of the line receiver 301 becomes the waveform of the clock CK modulated (PWM) based on the control signal (DP-DN). The value of the high level signal of the output do is 5V.

  The output st is from the on-delay timer Ton, the rising edge is delayed by 3t0 from the rising edge of the start signal ST, and the falling edge is synchronized with the start signal ST. As described above, the output st appears for the start signal ST having a high level period longer than 3t0, but the output st does not appear for a signal having a short high level time, that is, the clock CK or the end signal END. Therefore, the start signal ST can be detected.

  The output dc is from the preset addition counter 304, and is output while the output do, that is, the extracted clock CK is counted at the rising edge and the count value matches the address value of the setting unit switch. The As shown in FIG. 9, the waveform is at a high level in synchronization with the rising edge of the clock CK in the previous address cycle, and is at a low level in synchronization with the rising edge of the clock CK in the address cycle. For example, address 0 (tad = 0) is set to the high level in synchronization with the rise of the output st of the start signal ST that is the previous address, and is synchronized with the rise (3 / 4t0) in the cycle of the address. It becomes low level. In addition, the case where the address is 4 (tad = 4) is shown by hatching for reference. The output dc is input to the shift register in the input data unit 305.

  The outputs dr1 to dr4 are from the shift register SR of the input data unit 305, and “1 (or high level)” is synchronized with the falling edge of the extracted clock CK during the period when the output dc is high level. "Is a shift. That is, “1” is shifted in this order in the unit circuits Sr1 to Sr4 of the shift register SR. Accordingly, the outputs dr1 to dr4 of the shift register SR are sequentially set to the high level (until the fall of the next period) in synchronization with the fall of the clock CK. It can be seen from the waveforms of the outputs dr1 to dr4 shown in FIG. 9 that the timing is shifted by one clock. As in the case of the output dc, the case where the address is 4 (tad = 4) is indicated by hatching for reference.

  The outputs in0 to in3 are from the sensor unit 7, and in the embodiment shown in FIG. 9, the monitoring signals of the sensors given the addresses 0 to 3 are “0” “0” “1” “1”. It has become. The outputs in0 to in3 are input to the four AND gates together with the outputs dr1 to dr4, respectively, and take the value “0011” as shown in FIG. 9 during the high level period of the outputs dr1 to dr4. Therefore, each of the four AND gates is opened during the period in which the monitoring signal (address 0 to 3) “1” is being output, and the AND and the monitoring signals to be superimposed on the addresses 0 to 3 are arranged in this order. The signal is output from the OR gate through the gate.

  The output dip is from the NAND gate 308 of the monitoring data signal generating means 306. As described above, the output of the inverter INV, that is, the inverted signal of the output do and the output signal of the OR gate are input to the NAND gate 308. The NAND gate 308 opens in synchronization with the fall of the output do during the period in which the monitoring signal “1” of the address set in the setting unit switch is output, and the same value as the outputs in0 to in3 is obtained. It is output as a monitoring signal to be taken.

  TR2 is a time chart showing the on / off state of the transistor T2 in relation to the output dip. The output dip is input to the large transistor T2 via the transistor T1. That is, when the monitoring data signal is “1”, for example, the transistor T2 is turned on by the low level of the output dip, and the current Iis that is the monitoring data signal flows through the DP signal line 8 and the DN signal line 9.

  Next, input / output waveforms in the slave station output unit 2 will be described. As described above, since a part of the configuration of the slave station output unit 2 is the same as that of the slave station input unit 3, signals transmitted and received in those configurations are the same as those of the slave station output unit 2. . Therefore, the description of the output waveforms shown in FIG. 10 that are the same as those of the slave station output unit 3 is omitted.

  The output d1 is from the off-delay timer Toff. As described above, the off-delay timer Toff outputs only the off (low level) period with a predetermined delay (1 / 2t0 in this embodiment). The output do from the buffer circuit of the line receiver 301 is input to this off-delay timer Toff, its falling is delayed, and the rising is synchronized with the original input do is the signal d1. That is, when the data value at the input do is “1”, the “high potential low level” in the previous quarter period of the clock does not appear (it remains at the high level) because the off time is short. ). Further, in the case of “0”, the “high potential low level” of the previous 3/4 cycle of the clock has a long off time, so that only (3 / 4−1 / 2) = 1/4 cycle, “High potential low level” appears in the signal d1.

  The outputs dr1 to dr4 are from the shift register SR of the input data unit 205, and unlike the slave station input unit 3, the outputs dr1 to dr4 are sequentially synchronized with the rising edge of the clock CK (until the rising edge of the next period). ) High level.

  The outputs out0 to out3 are control signals at addresses 0 to 3 and are demodulated by the flip-flop circuits FF1 to FF4 constituting the output data unit 205. As described above, the flip-flop circuits FF1 to FF4 capture and hold the value of the signal d1 at that time in synchronization with the rise of the outputs dr1 to dr4, and output these as outputs out0 to out3. Therefore, in this embodiment, the data values of the outputs out0 to out3 are “0”, “0”, “1”, and “1”, respectively. These outputs out0 to out3 are inverted and then output as outputs O0 to O3 to the actuator unit 6 of the actuator 5 through the large transistors T0 to T3 for driving whose emitters are connected to the capacitor C0. .

  In each configuration, as a result of the input / output of signals as described above, signals transmitted / received in the mediation station 1 are as follows. In FIG. 8, the data value of addresses 0 to 3 of the control signal output from the mediation station 1 is “0101”, and the input from the sensor unit 7 assigned the addresses 0 to 3 is “0011”. Some cases are shown.

  In the serial pulsed voltage signal in this embodiment, one cycle (t0) of the clock CK, that is, each address is divided into at least an input period (i) and an output period (o) subsequent thereto. In FIG. 8, at address 0 and address 2 where the data value is “0”, the 3/4 period before “low level” is the input period, and the remaining 1/4 period is the output period. At address 1 and address 3 where the data value is “1”, the quarter period before “low level” is the input period and the remaining 3/4 period is the output period. In the input period, the monitoring data signal composed of the current signal Is is superimposed, and the mediation station input unit 18 extracts the superimposed monitoring data signal. On the other hand, in the output period, a control signal subjected to pulse width modulation (PWM) is superimposed. The intermediary station output unit 15 takes in the monitoring signal obtained at the previous output as a control signal, and superimposes the control data signal on the serial pulsed voltage signal in this output period to generate the DP signal line 8 and the DN signal. Output to line 9.

  As can be seen from the above, in this control / monitor signal transmission system, the input signal (monitor signal from the sensor unit 7) and the output signal (control signal to the actuator 6) are simply 1: 1 as described above. Transmit in response. As a result, a simple configuration in which the conventional control unit and master station are omitted can be realized, maintenance can be facilitated, and cost can be reduced. Further, for each input / output address in the transmission cycle, an output signal consisting of a pulse width modulation signal is controlled by an input signal consisting of a current signal. As a result, the transmission of the input signal and the output signal in a virtually bidirectional manner (in practice, the moment of transmission is not bidirectional, as will be described later), and the power line can be omitted.

  Further, as in this example, by using a current signal as a monitor signal and a pulse width modulated voltage signal as a control signal (combination of a current modulation monitor signal and a pulse width modulation control signal), the voltage noise is greatly degraded. A highly reliable transmission control system can be realized in a manufacturing plant or the like under conditions.

  As described above, the control signal in this embodiment includes a power supply voltage Vx, that is, a pulsed voltage having a level of 24V, and a smaller (absolute value) than this power supply voltage (absolutely) than a high level signal in other circuit portions. It is composed of a “high potential low level” which is a large level, ie, a pulse voltage of a level of 19V. Therefore, it is sufficiently larger than the CMOS high level signal 5V in other circuit parts (for example, a circuit part of CMOS logic). Since the potential difference Vs between the high level and the low level of the clock CK, that is, the pulse voltage is 5V, the threshold value is set to its intermediate value (21.5V when the DN signal line 9 is the reference level). Can be identified. In other words, the potential difference Vs is equal to the CMOS logic amplitude in another circuit part (for example, a CMOS logic circuit part). Therefore, it can be considered that the serial pulse-shaped voltage signal is obtained by level-shifting the clock of the potential difference Vs with a duty ratio of 50% and performing pulse width modulation according to the control data signal. On the other hand, according to the clock whose pulse width is modulated and whose amplitude is limited at a high potential, the average power supply voltage realized by the transmitted average power is approximately the center value of the amplitude, as shown by a one-dot chain line in FIG. It is a very high value of + 21.5V. Therefore, even if the power line P or the like is omitted, a power capacity sufficient for each of the plurality of slave stations 4 to operate can be transmitted to them.

  There are two means for changing the serial pulsed voltage signal on the DP signal line 8 and the DN signal line 9 in this way. According to the first means, according to the value of the control data signal, the potential of the DP signal line 8 is oscillated between the highest potential power supply voltage Vx = 24V and the “high potential low level” of 19V, The potential of the DN signal line 9 is set to the ground level. Note that the potential of the DP signal line 8 may be oscillated between 0 V and −5 V, and the potential of the DN signal line 9 may be set to −24 V, which is the lowest potential. According to the second means, according to the value of the control data signal, the potential of the DP signal line 8 is set to the highest potential ground level, and the potential of the DN signal line 9 is set to the lowest potential power supply voltage Vx = -24V. It is oscillated between −19 V which is “low level of high potential (large absolute value)”. Note that the potential of the DP signal line 8 may be set to + 24V, which is the highest potential, and the potential of the DN signal line 9 may be oscillated between + 5V and 0V. The waveform of FIG. 11 is based on this example. In any case, the relative potential difference between the DP signal line 8 and the DN signal line 9 is as described above.

  Note that when the refund power transmitted by the clock signal CK is low, the power line P cannot be omitted. For example, as a method that has been practically used, the power supply voltage Vx is similarly set to 24 V, and the amplitude obtained by modulating the amplitude of the control signal is set to a binary value of 12 V and 0 V. The average power transmitted by this clock is used. The average power supply voltage realized by is a low value of 12 V or less. Therefore, in such a case, if the power line P or the like is omitted, all the slave stations 4 cannot be operated, and the number of slave stations 4 must be limited. However, since this is not realistic, the power line P or the like has to be provided without actually limiting the number of slave stations 4.

  As mentioned above, although this invention was demonstrated according to the embodiment, this invention can be variously deformed within the scope of the gist.

  For example, for each cycle of the clock CK (within the same cycle), the first half (input period, i) and the second half (output period, o) are conceptually distinguished, and the input period is used to input the monitoring signal. In view of the fact that the output period is used to output the control signal, it can be further modified. That is, in the control / monitor signal transmission system of the present invention, the control signal to the slave station output unit 2 in the output period is turned on or off in response to the on or off of the monitor signal from the slave station input unit 3 in the input period. To do. Therefore, the input period precedes and overlaps the output period, and the monitor signal and the control signal are apparently transmitted bidirectionally in one cycle of the clock CK. And transmitted separately in the output period. The input period and the output period may not be ½t0, and may not necessarily have the same time length.

  In other words, the intermediary input unit 18 has the DP data signal line 8 and the DN data signal in the input period (i) when the period is divided into at least an input period and an output period subsequent thereto for each period of the clock CK. The monitoring data signal superimposed on the signal transmitted through the line 9 is extracted. On the other hand, the mediation station output unit 15 takes in the monitoring signal as a control signal, and superimposes the control data signal on the serial pulsed voltage signal for each cycle of the clock CK in the output period (o). The line 8 and the DN data signal line 9 are output.

  Further, an error check circuit may be provided in the mediation station 1. The error check circuit monitors the DP signal line 8 and checks the line condition (short circuit, etc.). The error check circuit may be configured as shown in, for example, Japanese Patent Laid-Open No. 03-006997.

  Further, although not shown in the figure, the operation in the mediation station 1 and the slave station 4 can be realized by executing the processing program for executing the above-described processes in the CPU (central processing unit) provided in each. Good.

  The present invention can be widely used for simplification of a transmission system and so-called wiring saving which is omission of wiring between control devices.

  Further, according to the present invention, in the control / monitoring signal transmission system, the advantages of the conventional system in which the control unit for performing the communication control and the intermediary station are provided in place of the master station can be directly enjoyed. In other words, the intermediary station transmits the monitoring signal from the sensor unit as a control signal to the actuator unit in a simple one-to-one correspondence in the same cycle of the clock, and further, the cycle is set to the input period and this. The monitoring signal from the sensor unit and the control signal to the actuator unit are transmitted while being superimposed on the input period and the output period, respectively, and the power line is also superimposed so that the power line is not necessary.

  As a result, a simple, small-scale, easy-to-maintain and inexpensive control / monitor signal transmission system that changes to the control unit and the master station is realized. High-speed signal transmission can be realized, and the monitoring signal and the control signal can be output to a common data signal line and transmitted in both directions. That is, in a simple, small-scale, easy-to-maintain and inexpensive control / monitor signal transmission system, it is not necessary to separately provide a period for transmitting the monitor signal or control signal on the data signal line, and the transmission rate is doubled compared to the conventional system. The speed can be increased, and the monitoring signal can be transmitted and the control signal can be transmitted even in a small wiring space of the actuator.

1 is an overall basic configuration diagram of a control / monitor signal transmission system according to an embodiment of the present invention. It is a functional block diagram of a mediation station. It is a schematic diagram of the transmission signal form in a storage area. It is a functional block diagram of a slave station output part, a slave station input part, and an actuator. It is a functional block wiring diagram of a slave station input unit. It is a block wiring diagram of a slave station output unit. It is a functional block wiring diagram of an intermediary station. It is a time chart figure of the control and monitoring signal transmission system which is an Example of this invention. It is a time chart figure of a slave station input part. It is a time chart figure of a slave station output part. It is a time chart figure of a mediation station.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Mediation station 2 Slave station output part 3 Slave station input part 4 Slave station 5 Actuator 6 Actuator part 7 Sensor part 8 DP signal line 9 DN signal line 10 MCU 11 OSC 12 Storage area 13 Timing generation means 14 Control data generation means 15 Mediation station output section 16 DP terminal 17 DN terminal 18 Mediation station input section 19 Monitoring signal detection means 20 Monitoring data extraction means 21 Power supply 200, 300 CV slave station power supply section 201, 301 Line receiver 202, 302 Control data signal extraction means 203, 303 Slave station address setting means 204 Shift register 205 Output data section 304 Address extraction means 305 Input data section 306 Monitoring data signal generation means 23, 307 Line driver 308 NAND gate

Claims (6)

A plurality of actuators each including an actuator unit and a sensor unit for monitoring the actuator unit; a plurality of slave stations provided corresponding to the plurality of actuators and connected by a common data signal line; and the data signal An intermediary station connected to the line,
The plurality of actuators are divided into one or a plurality of groups including at least two, and those belonging to the same group are in a correspondence relationship,
The intermediary station extracts the monitoring data from the monitoring signal transmitted from the sensor unit via the slave station, and another operation corresponding to the operating device including the sensor unit that has transmitted the monitoring data. Send it to the device as control data,
When the monitoring data is extracted, another monitoring data already stored in the storage area of the mediation station is transmitted as the control data, and then overwritten in the storage area. A control / monitoring signal transmission system characterized by being characterized.   2. The control / monitor signal transmission system according to claim 1, wherein the mediation station has a buffer area, and the monitoring data is stored in the buffer area and then transferred from the buffer area to the storage area. .   3. The control / monitor signal transmission system according to claim 1, wherein the overwriting storage is executed for each minimum unit of the monitor data.   3. The control / monitor signal transmission system according to claim 2, wherein the overwriting storage is executed for each block obtained by collecting a predetermined number of minimum units of the monitor data.   5. The monitoring data signal according to claim 1, wherein the monitoring data signal has an output period in which data is output from the mediation station to the actuating device, and an input period in which data is input from the actuating device to the mediation station. Characteristic control / monitor signal transmission system. 5. The control data according to claim 1, wherein the control data is transmitted following a start signal indicating the start of transmission, and the slave station is configured based on the start signal and a clock signal constituting the control data. A control / monitoring signal transmission system characterized in that, starting from a start signal, the address counter is sequentially updated by the clock signal to synchronize the transmission.

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