JP2002329280A - System for transmitting control/supervisory signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use ones between two control signals and two supervisory signals superimposed upon a clock signal for high-speed data transmission and to use the others for low-speed data transmission about a control/supervisory signal transmission system. SOLUTION: First control and supervisory data signals of a short transmission cycle are transmitted in each transmission cycle, and second control and supervisory data signals of a long transmission cycle are transmitted in each transmission frame composed of a plurality of transmission cycles. A master station outputting part 135 superimposes the first and second control data signals on the clock signal. A master station inputting part 139 extracts the value of each data of the first and second control data signals superimposed on the clock signal. A high-speed data slave station outputting part 14A extracts the first control data signal. A high-speed data slave station inputting part 15A superimposes the first supervisory data signal on the clock signal. A low-speed data slave station outputting part 14B extracts the second control data signal. A slow-speed data slave station inputting part 15B superimposes the second supervisory data signal on the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control / monitoring signal transmission system, and in particular, converts a parallel control signal from a control unit into a serial signal, transmits the serial signal, and transmits the serial signal. The serial / parallel conversion is performed to drive the device, and the monitoring signal of the sensor unit that detects the state of the device is parallel / serial converted and transmitted to the control unit side, and the serial / parallel conversion is performed and supplied to the control unit. The present invention relates to a control / monitoring signal transmission system that superimposes the control signal on a clock signal and further superimposes the monitoring signal on the control signal.

[0002]

2. Description of the Related Art A large number of controlled devices (for example, motors, solenoids, solenoid valves, relays, thyristors, lamps, etc.) at remote positions by transmitting control signals from control units such as sequence controllers, programmable controllers, and computers. It is widely used for automatic control to transmit the monitoring signal from the sensor unit (ON / OFF state of the reed switch, micro switch, push button switch, etc.) which controls the drive and detects the state of each device and supplies it to the control unit. Used in the technical field.

In such a technique, a plurality of lines such as a power supply line, a control signal line, and a ground line have conventionally been used to connect between a control unit and a controlled unit and to mutually connect a control unit and a sensor unit. Because of the wiring, the wiring work becomes difficult in order to arrange the equipment at high density with the recent miniaturization of the controlled device,
There is a problem that wiring space is reduced and cost is increased.

As a method for solving this problem,
"Signal-to-parallel conversion method" (Japanese Patent Application No. 62-229978)
No.) and “Serial transmission system for parallel sensor signals”
(Japanese Patent Application No. 62-247245).
According to these systems, one (1 bit) control signal (or sensor signal) can be superimposed on the clock signal line including the power supply corresponding to each clock, so that there is a gap between the control device and the controlled device. And the transmission system between the control device and the sensor device can be realized by a line with few wirings.

Further, according to the invention of the "control / monitoring signal transmission system" (Japanese Patent Application No. 1-140826), an input unit and an output unit are connected to a master station, and a clock signal superimposed on a power supply from the master station is transmitted. By outputting to a common data signal line, bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit can be realized with a simple configuration. That is, it can be configured with a small number of lines, the wiring cost is low, the arrangement and connection of the units can be simplified, and addresses can be arbitrarily assigned to each unit. Can be performed freely at the required position.

[0006]

According to the above-described conventional structure, bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit can be realized. However, since a signal from the control unit to the controlled unit (hereinafter, a control signal) and a signal from the sensor unit to the control unit (hereinafter, a monitoring signal) are output to a common data signal line, they are transmitted simultaneously. I couldn't. That is, the control signal and the monitoring signal are:
They could only be transmitted mutually exclusively and could not be transmitted in both directions at the same time. Therefore, it is necessary to separately provide a period for transmitting the control signal and a period for transmitting the monitoring signal as the transmission time on the common data signal line.

Further, the control signal and the monitoring signal are actually transmission signals (hereinafter, high-speed data) to be transmitted in a short cycle (high-speed or real-time) and transmission signals (sufficient in transmission in a long cycle (low-speed)). Hereinafter, low-speed data). The high-speed data includes, for example, a control signal (output signal) to an actuator in a controlled part and an input signal from an input sensor. That is, it is an original input / output signal (I / O data). The low-speed data includes, for example, a signal obtained by converting an analog signal (information signal) indicating various control values or measured values in the controlled unit into a digital signal for transmission. That is, an information signal (character data)
It is. According to the conventional configuration described above, bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit can be realized. However, during transmission of high-speed data, low-speed data must be inserted at a constant rate (see FIG. 2B described later). That is, high-speed data and low-speed data are mixed, and the transmission cycle time has to be greatly increased. That is, the transmission speed (period) of high-speed data to be transmitted in a short period is insufficient.

The present invention superimposes first and second control signals and first and second monitoring signals on a clock signal, and uses one of them for high-speed data transmission and the other for low-speed data transmission. It is an object to provide a monitoring signal transmission system.

[0009]

A control / monitoring signal transmission system according to the present invention comprises a control unit and a plurality of controlled devices each including a controlled unit and a sensor unit for monitoring the controlled unit. A control signal from the control unit is transmitted to the controlled unit via a data signal line common to the controlled device, and a monitoring signal from the sensor unit is transmitted to the control unit. The mobile station further includes a master station connected to the control unit and the data signal line, and a plurality of slave stations provided corresponding to the plurality of controlled devices and connected to the data signal line and the corresponding controlled device. Then, between the master station and the plurality of slave stations, the first control data signal and the first monitoring data signal having a short transmission cycle are updated every transmission cycle determined by a plurality of clocks, and are mutually transmitted on the data signal line. The second control data signal and the second monitoring data signal having a long transmission cycle are updated for each transmission frame having a period longer than the transmission cycle, and are mutually transmitted on the data signal line. The master station includes a timing generating means for generating a predetermined timing signal synchronized with the clock, a master station output section, and a master station input section. The master station output unit converts the first control data signal and the second control data signal input from the control unit into serial pulsed voltage signals under the control of the timing signal, and outputs these to a data signal line. The master station input unit extracts, under control of the timing signal, the value of each data of the first monitoring data signal and the second monitoring data signal superimposed on the serial pulse voltage signal transmitted through the data signal line. Then, these are converted into monitoring signals and input to the control unit.
Each of the plurality of slave stations includes a slave station output unit and a slave station input unit. The slave station output unit extracts the value of each data of the first control data signal or the value of each data of the second control data signal under control of the timing signal, and outputs the value to the slave station among the values of each data. The corresponding data is supplied to the corresponding controlled unit. The slave station input unit forms a first monitor data signal or a second monitor data signal according to the value of the corresponding sensor unit under the control of the timing signal, and converts the first monitor data signal or the second monitor data signal into data of the first or second monitor data signal. Is superimposed on the serial pulsed voltage signal.

According to the control / monitoring signal transmission system of the present invention, the first and second control signals and the first and second monitoring signals can be superimposed on the clock signal. Accordingly, high-speed bidirectional signal transmission between the control unit, the controlled unit, and the sensor unit can be realized, and the duplicated control signal and the duplicated monitor signal are output to a common data signal line. , And can be transmitted in both directions simultaneously. That is, the control signal and the monitoring signal can be completely duplicated. Further, one of the duplicated control signal and monitor signal can be used for transmitting high-speed data to be transmitted in a short cycle, and the other can be used for transmitting low-speed data sufficient for transmission in a long cycle. Therefore, it is not necessary to insert low-speed data during transmission of high-speed data, it is possible to prevent a long cycle time of high-speed data transmission, and to transmit high-speed data at a satisfactory transmission speed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1, 5 and 6 are basic structural diagrams of the present invention, and FIGS. 2 to 4 are diagrams for explaining signal transmission according to the present invention.

As shown in FIG. 1, the control / monitoring signal transmission system includes a control unit 10 and a plurality of controlled devices 12 each including a controlled unit 16 and a sensor unit 17 for monitoring the controlled unit 16. Become. The control unit 10 includes, for example, a sequence controller, a programmable controller, a computer, and the like. The controlled unit 16 and the sensor unit 17 are referred to as a controlled device 12. The controlled unit 16 includes various components constituting the controlled device 12, for example, an actuator, a (stepping) motor, a solenoid, a solenoid valve, a relay, a thyristor, a lamp, and the like. The sensor unit 17 is selected according to the corresponding controlled unit 16 and includes, for example, a reed switch, a micro switch, a push button switch, and the like, and outputs an on / off state (binary signal).

The plurality of controlled devices 12 are of two types, a first (high-speed data) controlled device 12A and a second (low-speed data) controlled device 12B. In response, the plurality of slave stations 11 form a first (high-speed data) slave station 11A corresponding to the first controlled device 12A and a second (low-speed data) corresponding to the second controlled device 12B. Slave station 11B
Consists of two types. In the control unit 10, a high-speed data input unit 101A and a high-speed data output unit 102A are provided corresponding to the high-speed data slave station 11A, and a low-speed data input unit 10A corresponding to the low-speed data slave station 11B.
1B and a low-speed data output unit 102B are provided. In each case, the “high-speed” side transmits high-speed data to be transmitted in a short cycle (high-speed or real-time), and the “low-speed” side transmits sufficiently low-speed data in a long cycle (low-speed). Circuits to which codes A and B are added like the slave stations 11A and 11B transmit high-speed data and low-speed data, respectively. When the code A or the like is not added as in the slave station 11, it indicates both the high-speed data slave station 11A and the low-speed data slave station 11B. The same applies to other cases. In addition, there is no distinction between high speed and low speed in the slave station power supply unit 20.

The control / monitoring signal transmission system includes a control unit 1 via a data signal line common to a plurality of controlled devices 12.
0 from the control unit 16
And a monitoring signal (sensor signal) from the sensor unit 17 is transmitted to the input unit 101 of the control unit 10.
As shown in FIG. 1, the control signal and the monitoring signal input / output to / from the control unit 10 are parallel signals of a plurality of bits. On the other hand, the control signal and the monitoring signal transmitted on the data signal line are serial signals. The master station (main station) 13 performs parallel / serial conversion on the control signal and performs serial / parallel conversion on the monitoring signal. The data signal line includes first and second data signal lines D + and D-. The first data signal line D +, as described later,
Supply of power supply voltage Vx, supply of clock signal CK, and
Used for simultaneous transmission of control and monitoring signals in both directions. The second data signal line D- is set to a common (signal) ground level for the master station 13 and the slave stations 11.

In this example, a plurality of slave stations 11
And a power line P for supplying a power supply voltage Vx to each of the slave station power supply units 20. The power line P is composed of first and second power lines P ₂₄ and P ₀ . First and second power lines P ₂₄
Are respectively the power supply voltage Vx (= 24 V) and the plurality of slave stations 1
1 is supplied with a common (power supply) ground level (= 0 V), and is connected to the local power supply 21 at one end (or both ends). The configuration of the power line P is described in, for example, Japanese Patent Application No. 1-1408.
The configuration shown in No. 26 may be adopted.

As shown in FIG. 1, the control / monitoring signal transmission system includes a master station 13 and a plurality of slave stations 11 for such signal transmission. Master station 13 is connected to control unit 10 and a data signal line. The plurality of slave stations 11 are provided corresponding to the plurality of controlled devices 12, are connected to data signal lines at arbitrary positions, and are connected to the corresponding controlled devices 12. Each of the plurality of slave stations 11 includes a slave station output unit 14 and a slave station input unit 15. The slave station output unit 14 and the slave station input unit 15 correspond to the controlled unit 16 and the sensor unit 17, respectively. As shown in FIG. 1, the control signal and the monitor signal input / output to / from the slave station input unit 15 and the slave station output unit 14 are multiple-bit parallel signals. The slave station output unit 14 performs serial / parallel conversion on the control signal, and the slave station input unit 15 performs parallel / serial conversion on the monitoring signal.

The master station 13 includes a master station output section 135 and a master station input section 139, as shown in FIG. Master station output unit 1
35 serially connects the first control data signal input from the control unit 10 via the control high-speed data unit 134A and the second control data signal input via the control low-speed data unit 134B under control of the timing signal. The signal is converted into a pulsed voltage signal, and these are output to a data signal line. Master station input unit 1
39 extracts each data value of the first monitor data signal and the second monitor data signal superimposed on the serial pulse voltage signal transmitted through the data signal line under the control of the timing signal, Is converted into a monitoring signal, and is input to the control unit 10 via the monitoring high-speed data unit 138A and the monitoring low-speed data unit 138B, respectively.

The master station 13 includes an oscillator (OSC) 131,
Imming generating means 132, master station address setting means 13
3. It has a command generating means 1313. Timing departure
The generating means 132 is based on the oscillation output output from the oscillator 131.
Then, a predetermined timer synchronized with the clock CK having a predetermined period
Generate an imaging signal. That is, the timing generation means 1
32 is the power supply voltage V applied to the generated clock CK._XSuperimpose
You. For this purpose, the timing generation means 132
For generating the power supply voltage Vx of a predetermined constant level.
Source means (not shown). For example, duty ratio 5
0%, the first half of one cycle of the clock CK is
Level (0+), and the latter half is the power supply voltage V _XLevel
It is said. The clock CK including the power supply voltage is basically
Is output to the terminal 13a and connected to the first data signal line D +.
Supplied. On the other hand, the ground level signal (GND)
The signal 13b is output to the second data signal line D-.

The clock CK including the power supply voltage output from the timing generator 132 and other various control signals are input to the master station output unit 135. The master station output unit 135 includes a control data signal generation unit 136 and a line driver 137. The output data unit 134 holds the parallel control data signal input from the control unit 10, converts this into a serial data string, and outputs it. Control data signal generating means 13
6 superimposes the value of each data of the serial data string from the output data unit 134 on the clock CK including the power supply voltage. The output of the control data signal generating means 136 is supplied to a first data signal line D via a line driver 137 which is an output circuit.
Output above +.

The command generation means 1313 generates a command signal based on the control signal output from the timing generation means 132, and outputs the master station output section 135 and the control low speed data section 1
34B, input to the monitoring low-speed data section 138B. That is,
The command is substantially only used in the low-speed side circuit in the master station 13 and the slave station 11 (low-speed data slave station 11B) described later. That is, it is a control signal (control information) for controlling transmission of the second control data signal and the second monitoring data signal. The command includes a cycle number as described later.

As shown in FIG. 2A, the master station output unit 13
5 is a low-speed data slave station 11 under the control of a timing signal.
Between the first control data signal and the first monitoring data signal (high-speed data I / O) having a short transmission cycle (Tc).
Are updated every transmission cycle determined by a plurality of clocks, and are mutually transmitted on the data signal line. Further, under control of the timing signal, the master station output section 135 outputs the second control data signal and the second control data signal having a long transmission cycle (2Tc in this example).
The monitoring data signal (low-speed data CR) is updated for each transmission frame having a period longer than the transmission cycle, and is transmitted mutually on the data signal line. The transmission frame in which the second control data signal and the second monitoring data signal are transmitted is the first transmission frame.
This is an integer (i) times the transmission cycle in which the control data signal and the first monitoring data signal are transmitted. In this example, it is twice (i = 2).

The transmission cycle of high-speed data consists of a start signal S at the head thereof and an I / O (input / output) signal I / O following the start signal S.
/ O. The transmission cycle of the low-speed data consists of a start signal S at the head thereof and character data C following the start signal S.
R. The command (command data) CM is inserted at the beginning of each transmission cycle (further before the start signal S at the beginning). Transmission cycles for high and low speed data are distinguished by an end signal E between them. Transmission frames are distinguished by counting the number of transmission cycles.

As shown in FIG. 3A: Transmission line transmission signal, the transmission cycle consists of n (32 in this example) clocks following the command signal CM and the start signal S. One (1 bit) first and second control signals and first and second monitoring signals (four in total) are superimposed on one clock, so that one transmission cycle is 4n in total. A bit data signal (serial signal) can be included. In addition, the command signal CM included in the N-th transmission cycle (N cycle) in one transmission frame is represented by CM
(N).

As shown by D: high-speed data output unit transmission signal and E: high-speed data input unit transmission signal in FIG. One transmission cycle includes n-bit output data (control data signal) and n-bit input data (monitoring data signal). High-speed data I / O
Each bit has an independent meaning as a control signal and a monitor signal. The high-speed data I / O has a transmission cycle equal to the transmission cycle Tc. That is, assuming that a control signal to a certain slave station 14 is output at the 0th bit (address 0) of a certain transmission cycle, the control signal to the slave station 14 is always output at the 0th bit position of each transmission cycle. You.

On the other hand, as shown in FIG. 3B: low-speed data output section transmission signal and C: low-speed data input section transmission signal, in transmission of low-speed data (or character data) CR, low-speed data CR A transmission frame consisting of i transmission cycles is i × n
It includes bit output data (control signal) and i × n-bit input data (monitoring signal). In FIG. 2A,
i = 2 (two channels). The command signal CM includes a start cycle number and an end cycle number. The cycle number is uniquely assigned to each transmission cycle, and is repeated from 1 to i in order. The value of the upper limit value i of the cycle number is predetermined for each transmission system. Let the i-th transmission cycle be (i-
1) Called a channel, one transmission frame includes a transmission cycle of i channel.

The low-speed data CR has, for each bit,
It has no independent meaning as a control or monitoring signal. That is, for example, the 12-bit low-speed data (and the added four control signals) CR is meaningful only after being converted into one analog signal, and all are extracted in one low-speed data slave station 11B. The data is input to the corresponding low-speed data controlled device 12B. The reverse is also true. The low-speed data CR has a transmission cycle of i × T
c (2Tc in this example). That is, a certain child station 1
Assuming that a plurality of control signals to the slave station 14 are output at the 0th bit or less in a certain transmission cycle, the control signal to the slave station 14 is always output to a plurality of bits at the 0th bit or less in the i-th transmission cycle. Is done.

Conventionally, as shown in the upper part of FIG. 2B, when only I / O signals are transmitted, the cycle time Tca can be shortened theoretically. However, actually, the character data (CR
2), the cycle time Tcb becomes longer as shown in the lower part of FIG. 2B, and as a result, the transmission speed of the I / O signal decreases.

As shown in FIG. 4, the master station output unit 135
Under the control of the timing signal, the value of each data of the first control data signal # 1 (high-speed data or I / O signal) input from the control unit 10 to the first output data unit 134 for each cycle of the clock , The duty ratio between the period of the power supply voltage other than the predetermined power supply voltage level and the subsequent period of the power supply voltage Vx level is changed (pulse width modulation). Similarly, master station output section 135 outputs power supply voltage according to the value of each data of second control data signal # 2 (low-speed data or CR signal) input from control section 10 to second output data section 134. A predetermined level (for example, Vx / 2) that is different from the power supply voltage Vx during a period other than the level
Alternatively, a pseudo ground level 0+ is set (voltage modulation is performed). Thereby, the first control data signal and the second control data signal are converted into serial pulsed voltage signals, and these are output to the data signal lines. For example, 0 + = 2V.

For example, when the data value of the first control data signal # 1 is "0", the 3/4 cycle before the clock is set to a predetermined level different from the power supply voltage Vx, and the cycle after the clock is set. A quarter cycle is the level of the power supply voltage Vx.
In the case of "1", the 1/4 cycle before the clock is set to a predetermined level different from the power supply voltage Vx, and the 3/4 cycle after the clock is set to the level of the power supply voltage Vx.
Further, a predetermined level different from the power supply voltage Vx is set to the second level.
When the data value of control data signal # 2 is "0", V
The level is x / 2, and in the case of “1”, it is a pseudo ground level 0+. Therefore, for example, when the data values of the first control data signal and the second control data signals # 1 and # 2 are "0011" and "1010", respectively, the result is as shown in FIG. That is, according to the data value of the control data signal,
The duty ratio of the clock (which was originally 50%) is changed. Thereby, the parallel control data signal is converted into a serial pulse-like voltage signal and output to the data signal line.
The address is assigned for each cycle of the clock CK.

On the other hand, the signal on first data signal line D + is taken into master station input section 139. Master station input unit 13
9 is a monitoring high-speed data signal detecting means 1311A, a monitoring high-speed data extracting means 1310A, a monitoring low-speed data signal detecting means 1311B, a monitoring low-speed data extracting means 1310B,
A line receiver 1312 common to the high-speed and low-speed circuits is provided. The monitoring signal detecting means 1311 is a line receiver 1
The signal on the first data signal line D + is fetched via 312, and the monitoring data signal superimposed on the signal is detected and output. The monitoring data extracting means 1310 outputs this detection output in synchronization with the clock CK including the power supply voltage from the timing generating means 132 (waveform shaping). The input data section 138 converts a serial data string composed of the detected monitoring data signals into a parallel monitoring data signal and outputs it.

As shown in FIG. 4, the master station input section 139
Under the control of the timing signal, a first monitoring data signal # 1 (high-speed data or I / O signal) composed of a frequency signal superimposed on a serial pulsed voltage signal transmitted through the data signal line for each cycle of the clock. ) Is detected. Similarly, the master station input unit 139 converts the second monitor data signal # 2 (low speed data or CR signal) superimposed on the serial pulse voltage signal transmitted through the data signal line into the monitor data signal and the power supply voltage Vx. At the time of rising of the level of the power supply voltage Vx as the presence or absence of the current signal Iis caused by competition with the power supply voltage Vx. As a result, each data value of the serial first monitoring data signal and the second monitoring data signal is extracted, converted to a monitoring signal, and input to the control unit 10 via the input data unit 138.

For example, when the data value of the first monitoring data signal # 1 is "0", the frequency signal is not superimposed and "1"
In the case of, the frequency signal is superimposed. By identifying these, the value of each data of the first monitoring data signal # 1 is extracted. Further, when the data value of the second monitoring data signal # 2 is “0”, a monitoring data signal that does not generate the current signal Iis due to competition with the power supply voltage Vx is superimposed.
In the case of “1”, a monitoring data signal that causes a current signal Iis due to competition with the power supply voltage Vx is superimposed. By identifying these, the value of each data of the second monitoring data signal # 2 is extracted. Therefore, for example, when the data values of the first monitoring data signal and the second monitoring data signals # 1 and # 2 are "1100" and "0101," respectively,
As shown in FIG.

As described above, the control signal to be distributed to the plurality of slave stations 11 is transmitted from the master station 13 as a serial signal (serial pulse-like voltage signal) on the data signal line. An address counting method is used. That is, the total number of control data signal data to be transmitted (distributed) to the slave station 11 can be known in advance. Therefore, one address is assigned to each data of all the control data signals. The slave station 11 extracts the clock CK from the serial pulse voltage signal and counts the number of the clock CK. The data value of the serial pulse voltage signal at that time is taken in as a control signal. Note that a final address is also assigned to the master station 13 in order to form an end signal.

The length of one transmission cycle (the number of clocks or the number of data bits) is determined by the value of the final address. The value of the final address is determined for each transmission system.
The length of the transmission cycle and the character data to be transmitted (C
The number i of transmission cycles included in one transmission frame is determined based on the total number of bits of the (R signal). In this example, since the length of the transmission cycle is 32 bits and i is 2, transmission of 64-bit character data is possible. This corresponds to four outputs of the AD converter having a resolution of 12 bits (with a control signal of 4 bits).

A start signal S and an end signal E are formed, respectively, to determine the start and end for address counting. The master station 13 includes the timing generation unit 1
32, the start signal S is formed prior to the output of the serial pulse voltage signal, and the first data signal line D +
Output to The start signal S is at the level of the power supply voltage Vx and is longer than one cycle of the clock CK so as to be distinguishable from the control signal. The master station address setting means 133 holds the address assigned to the master station 13. The master station 13 counts the clock CK extracted from the serial pulsed voltage signal, extracts an address assigned to itself in advance, and outputs an end signal E to the first data signal line D + at that time. The end signal E is longer than one cycle of the clock CK and shorter than the start signal S.

Each of the plurality of slave stations 11 has a slave station output unit 14
And a slave station input unit 15. The slave station output unit 14 extracts the value of each data of the first control data signal or the value of each data of the second control data signal under the control of the timing signal,
The data corresponding to the slave station in the value of each data is supplied to the corresponding controlled unit 12. The slave station input section 15 forms a first monitor data signal or a second monitor data signal according to the value of the corresponding sensor section 17 under the control of the timing signal, and outputs the first monitor data signal or the second monitor data signal. Is superimposed on the serial pulsed voltage signal as the data value of

As described above, the plurality of slave stations 11 can be classified into two types: a (second) low-speed data slave station 11B shown in FIG. 6 and a (first) high-speed data slave station 11A shown in FIG. Become.
As can be seen from a comparison between FIG. 6 and FIG. 7, the difference between the two is only the presence or absence of the command setting means 148B and 158B and the command extraction means 149B and 159B. That is, by adding these configurations to the configuration of the high-speed data slave station 11A, a low-speed data slave station 11B is obtained.

In FIG. 6, the low-speed data slave station 11B
When the own station is specified according to the command CM, the second
The value of each data of the control data signal is extracted, and the value of the data of the second monitoring data signal is superimposed. In order to comply with the command CM, a command setting unit 148B and a command extraction unit 149B are provided.

In the low-speed data slave station 11B, the low-speed data slave station output section 14B counts the clock extracted from the serial pulse voltage signal during the period from the start cycle number to the end cycle number assigned to the own station. Then, an address assigned to itself is extracted, and the data of the address is supplied to the corresponding low-speed data controlled device 12B. Also, during this period, the low-speed data slave station input unit 15B counts clocks extracted from the serial pulsed voltage signal, extracts an address assigned to itself in advance, and extracts the address of the serial pulsed voltage signal. The monitoring signal for the low-speed data controlled device 12B is superimposed on the control signal. That is, the low-speed data slave station output unit 14B extracts the value of each data of the second control data signal under the control of the timing signal, and corresponds to the data corresponding to the slave station among the values of each data. It is supplied to the low-speed data controlled unit 16B. Under the control of the timing signal, the low-speed data slave station input section 15B forms a second monitoring data signal according to the value of the corresponding low-speed data sensor section 17B, and uses this as the data value of the second monitoring data signal. , Superimposed on the serial pulsed voltage signal.

According to the command CM, the low-speed data slave station 11B extracts each data value of the second control data signal in the transmission cycle in which the cycle number of the command CM matches the start cycle number assigned to the own station. Start. Also, the low-speed data slave station 11B starts superimposing the data value of the second monitoring data signal, and
In the transmission cycle in which the cycle number of the second control data signal matches the end cycle number assigned to the own station, the extraction of each data value of the second control data signal ends, and the superimposition of the data value of the second monitor data signal ends. .

As shown in FIG. 6, the low-speed data slave station output section 14B includes a power supply voltage generating means (CV) 140, a line receiver 141B, and a control low-speed data signal extracting means 142.
B, a slave station address setting means 143B, an address extracting means 144B, an output low speed data section 145B, a command setting means 148B and a command extracting means 149B.

The power supply voltage generator 140 of the slave station output section 14 and the power supply voltage generator (CV) 150 of the slave station input section 15 described later constitute the slave station power supply section 20. The power supply voltage generating means (CV) 140 is a DC (DC) -DC converter, and electrically connects the low-speed data slave station output unit 14B (and the low-speed data controlled unit 16B of the corresponding low-speed data controlled device 12B). Power supply voltage Vc for driving
c is generated from the power line. That is, the power supply line P ₂₄
Is stabilized and smoothed by a known means to obtain a stabilized power supply voltage Vcc (5 V) and an output (12 V) to the line receiver 141B.

Line receiver 141B as input circuit
Captures a signal transmitted on the first data signal line D + and outputs it to the control low-speed data signal extraction means 142B. The control low-speed data signal extracting means 142B extracts a control data signal from the signal, and
4B and output to the output low-speed data section 145B. The slave station address setting means 143B holds the own station address assigned to the low-speed data slave station output unit 14B. The address extracting means 144B is provided with a slave station address setting means 143.
An address that matches the own station address held in B is extracted and output to the output low-speed data section 145B. When an address is input from the address extraction means 144B, the output low-speed data unit 145B holds the current one of the (serial) signals transmitted on the first data signal line D + at that time.
Alternatively, a plurality of data values are output as parallel signals to the corresponding low-speed data controlled unit 16B. That is, the output low-speed data unit 145B performs serial / parallel conversion on the control signal.

As shown in FIG. 4, under the control of the timing signal, the low-speed data slave station output section 14B outputs, during each cycle of the clock, a period other than the level of the power supply voltage of the serial pulsed voltage signal. By identifying whether the level is a predetermined voltage level (for example, Vx / 2) different from the power supply voltage Vx or a pseudo ground level, the value of each data of the second control data signal is extracted, and the value of each data is extracted. The data in the value corresponding to the slave station is supplied to the corresponding low-speed data controlled unit 16B.

On the other hand, as shown in FIG. 6, the low-speed data slave station input section 15B includes a power supply voltage generating means (CV) 150, a line receiver 151B, and a control low-speed data signal extracting means 1
52B, a slave station address setting unit 153B, an address extraction unit 154B, an input low speed data unit 155B, a monitoring data signal generation unit 156B, a line driver 157B, a command setting unit 158B, and a command extraction unit 159B.

As can be seen from FIG. 6, the power supply voltage generation means 150 to the address extraction means 154B have substantially the same configuration as the power supply voltage generation means 140 to the address extraction means 144B, and perform almost the same operation. The power supply voltage generating means 150 electrically drives a circuit constituting the slave station input section 15 and electrically drives the low speed data sensor section 17B of the corresponding low speed data controlled device 12B.
The c generated from the power line P _24.

The input low-speed data section 155B holds a monitoring signal consisting of one or a plurality of (bit) data values input from the corresponding low-speed data sensor section 17B.
The input low-speed data section 155B
When an address is input from B, the value of one or a plurality of held data is output to the monitoring data signal generating means 156B as a serial signal in a predetermined order. That is,
The input low-speed data unit 155B performs parallel / serial conversion on the monitoring signal. Monitoring data signal generating means 156B
Outputs a second monitoring data signal according to the data value of the second monitoring signal. The second monitoring data signal output from the monitoring data signal generating means 156B is output onto the first data signal line D + by a line driver 157B as an output circuit. Therefore, the second monitoring data signal is superimposed on the value of the data of the control signal output on the first data signal line D + at that time. That is, the second monitoring data signal is superimposed on the position of the data corresponding to the slave station 11B of the serial pulsed voltage signal. In other words, the data value of the second monitor signal at the same address is superimposed on the data value of the second control signal at the same address.

As shown in FIG. 4, under the control of the timing signal, the low-speed data slave station input section 15B has a binary level different from the power supply voltage Vx according to the value of the corresponding low-speed data sensor section 17B. The second monitoring data signal # 2 is formed, and is superimposed as a data value of the second monitoring data signal on a predetermined position of the serial pulse voltage signal. For example, when the data value of the monitoring data signal is “1”,
In one cycle of the clock CK, a monitoring data signal is formed and superimposed at a predetermined position, and when it is “0”, the monitoring data signal is not formed and is not superimposed. Therefore,
For example, when the data value of the monitoring data signal is “0101”, as a result of the superimposition of the monitoring data signal by the line driver 157B, as described above, the output (detection current) of the monitoring low-speed data signal detection unit 1311B is as shown in FIG. Become like

On the other hand, in FIG.
A ignores the command, extracts the value of each data of the first control data signal, and superimposes the data value of the first monitoring data signal. Since the command is ignored, no command setting means and no command extraction means are provided.

In the high-speed data slave station 11A, the high-speed data slave station output section 14A counts the clocks extracted from the serial pulsed voltage signal in the transmission cycle, extracts the address previously allocated to itself, and The address data is supplied to the corresponding high-speed data controlled device 12A. Also, the high-speed data slave station input unit 15A counts clocks extracted from the serial pulse voltage signal, extracts an address assigned to itself in advance, and applies the high-speed data reception to the address of the serial pulse voltage signal. A monitoring signal for the control device 12A is superimposed. That is, the high-speed data slave station output unit 14A, under the control of the timing signal,
The value of each data of the first control data signal is extracted, and the data corresponding to the slave station among the values of each data is supplied to the corresponding high-speed data controlled unit 16A. Under the control of the timing signal, the high-speed data slave station input section 15A forms a first monitoring data signal according to the value of the corresponding high-speed data sensor section 17A, and uses this as the data value of the first monitoring data signal. , Superimposed on the serial pulsed voltage signal.

Under the control of the timing signal, the high-speed data slave station output unit 14A outputs a period other than the power supply voltage level of the serial pulsed voltage signal and the subsequent power supply voltage Vx for each period of the clock. By identifying the duty ratio with the level period, the value of each data of the first control data signal is extracted, and the data corresponding to the slave station out of the values of each data is corresponded to the high-speed data controlled unit. 16A.

Under the control of the timing signal, the high-speed data slave station input section 15A receives the corresponding high-speed data sensor section 17A.
A first monitor data signal # 1 composed of a frequency signal is formed in accordance with the value of the first monitor data signal, and is superimposed as a data value of the first monitor data signal on a predetermined position of the serial pulsed voltage signal.

Hereinafter, the specific configuration and operation of this example will be described in order from the output of the control signal from the control unit 10 to the input of the monitoring signal to the control unit 10 with reference to FIGS. .

In FIG. 8 and FIG. 9, the master station 13
High-speed data control signals OUT0p to OUT31p, and second low-speed data control signals OUT0v to OUT31
v is superimposed on the clock CK. The master station 13 extracts the second low-speed data monitoring signals IN0i to IN31i in addition to the first high-speed data monitoring signals IN0f to IN31f.

First, the master station output unit 135 will be described. 8 and 9, the timing generator 132
Output a start signal ST, a predetermined number of clocks CK, and an end signal END. The start signal ST is output (set to a low level) in accordance with, for example, an input of a predetermined command (not shown) from the control unit 10. Similarly, the timing generation unit 132 is stopped by input of another predetermined command (not shown) from the control unit 10. The output period of the start signal ST is set to 5t0 to distinguish it from the clock CK. t0 is the time of one cycle of the clock CK. The clock CK is formed by dividing the oscillation output from the oscillator 131 to have a predetermined period. As shown by the output ck, the output of the clock CK is continuous with the start signal ST, and thereafter, the output is started in synchronization with the fall thereof, and a predetermined number (the number of addresses) is output. For this purpose, the timing generating means 132 includes a counting means (not shown). That is, the counting means starts counting at the rise of the start signal ST.
When the count output of the counting means reaches a predetermined value, the output of the clock CK is stopped. The end signal END is
Detecting a predetermined number (the number of addresses) of clocks CK,
After that, it is output continuously. For this purpose, the timing generating means 132 includes a comparing means (not shown). That is, the comparing means compares the count output of the counting means with the address set in the master station address setting means 133, and outputs an end signal END for a predetermined period when the addresses match. The end signal END is the clock C
In order to distinguish from K, the output period is set to 1.5t0. The counting means is reset by the end signal END. In synchronization with the end of the end signal END,
The start signal ST is output again, and the same operation is repeated. One transmission cycle (one start signal S
The number corresponding to the number of high-speed data (the number of bits) that can be transmitted in the period from T to the end signal END immediately thereafter is the maximum value of the address, which is the address of the master station 13.
One piece of data (one bit) corresponds to one clock.

For example, if the address (ie, the number of data of the control signal described above) is 0 to 31, the control signals OUT0p to OUT3 which are 32-bit parallel data are used.
1p is input from the high-speed data output unit 102A to the control high-speed data unit 134A. Control high-speed data section 13
4A is triggered by the fall of the start signal ST.
Control signals OUT0p to OUT3 in synchronization with clock CK
1p is shifted and output as an output Dops in this order. The addresses are 0 to 63, 127, 255,.
・ It may be. Control signals OUT0p to OUT31p
Are switched (updated) in synchronization with, for example, the start signal ST. The largest address (address 31) is set in the address setting means 133. Thus, the end signal END is output in accordance with the end of the processing of the data at the address 31 of the control signal. The address setting unit 133 closes the weighted switch by five digits from the left as shown in FIG.
10 "is formed, and address 31 is set (the same applies to other addresses).

The output Dops is controlled by control signals OUT0p to OUT0p-O.
The high level (or “1”) or the low level (or “0”) is provided every clock according to the data value of the UT 31p. As a result, for example, an output like “0011...” Is output. The output Dops is input to the control data signal generator 136. The start signal ST and the end signal END are also input to the control data signal generation means 136. The same applies to the output Dovs.

The timing generating means 132 includes the oscillator 13
By dividing the oscillation output of No. 1, a clock 4CK having a frequency (4f0) four times the frequency f0 of the clock CK is formed. The control data signal generating means 136 counts the clock 4CK by a counter (not shown). Of 1
0V (low level) is output only during the period of the four clocks 4CK, and 5V (high level) is output during the remaining three clocks 4CK. Conversely, if it is “0”, the first three
0V is output during the period of the four clocks 4CK and the remaining 1
5V is output only for the period of the clocks 4CK. As a result, the control data signal generation means 136 outputs the clock CK
Based on the control signals OUT0p to OUT31p (PW
M) Modulate.

One output (PWM modulated output) of the control data signal generating means 136 is binary (+5 V and 0 V)
And output to one signal line Pck. The signal output to the signal line Pck is input to the line driver 137 via the comparator COMP1, and the data signal line Dck
+ (And D-). Line driver 137
Comprises transistors TR1 to TR3 and the like. The transistors TR1 and TR3 and TR2 are complementarily connected to each other, and can be driven with low impedance. The transistor TR1 is for outputting the voltage Vx, and the transistor TR2 is for the pseudo ground level 0+ (2V).
, And the transistor TR3 outputs the voltage Vx
/ 2 is output. Transistor TR1
Is connected to a photocoupler PC which is a monitoring signal detecting means 1311. Comparator COMP1 has output P
ck is inverted, and the line driver 137 outputs a signal (output Pc
(inversion signal of k) and inversion. The output of the line driver 137 is limited to 2V to 24V, and outputs a signal similar to the signal line Pck. Therefore,
The signal on the first data signal line D + is also binary (level Vx
And 0+). Note that the second data signal line D-
Is 0 V (ground level 0-). The start signal ST is output as a signal at the level of the power supply potential Vx on the first data signal line D +, and the end signal EN is output.
D is output as a signal of Vx / 2 or a pseudo ground level 0+.

That is, in this example, the command CM is superimposed on the end signal END, and the end signal E is always output before the start signal S. The command CM includes a cycle number uniquely added for each transmission cycle. In this example, for simplicity of description, the cycle numbers are only 0 and 1. Therefore, in one low-speed data slave station 11B, the start cycle number and the end cycle number match, and the set cycle number is one. When the cycle numbers are 0 and 1, the end signal E is set to Vx / 2 or the pseudo ground level 0+, respectively. In the command generating means 1313, the counter counts the start signal ST and sets it to 0 (0CH) or 1 every two transmission cycles.
One of the outputs of (1CH) is repeated (the count is incremented by the start signal ST and the state is maintained until the next input). The output of the counter (or 0CH / 1CH cycle signal which is the command CM) is 0 or 1CH.
As shown in FIGS. 5 and 8, a cycle signal indicating which cycle of (channel) is transmitted from the command generation unit 1313 at the high level of the end signal END, and is input to the control unit 10. .

Thus, the low-speed data input unit 10
The 1B and low speed data output unit 102B can know whether the cycle is 0 or 1CH. The low-speed data input unit 101B or the like fetches the command CM (the value before the start signal changes by counting up) in synchronization with the start of the cycle (that is, the rise of the start signal), and sets 0 or 1CH. know. As shown in FIG. 9, if the fetched command CM is Vx / 2, it is 0CH, and if it is the pseudo ground level 0+, it is 1CH. For example, by setting the end signal E to a signal of the pseudo ground level 0+, outputting Vx / 2 or Vx after the output and designating the cycle number, and then outputting the signal of the pseudo ground level 0+ again, the cycle number is obtained. May be specified.

Similarly to the signal Dops for the first control signals OUT0p to OUT31p, the second control signal OUT0
Signals Dovs for v to OUT31v are formed. The control data signal generating means 136 outputs the signal Dovs
(And Pck) to form a signal Dvh. That is, during the period when the signal Pck is at the low level, the second
If the control signal is at a low level, a signal Dvh0 ("1") is formed, and if the second control signal is at a high level, a signal Dvh1 ("1") is formed. The signal Dvh is formed from the logical sum of the signal Dvh0 and the signal Dve0, and the signal Dvl is formed from the logical sum of the signal Dvh1 and the signal Dve1. The signal Dve0 is output from the command generation unit 1313.
Is the logical product of the 0-bit output of the binary counter and the end signal END, and the signal Dve1 is 1
This is the logical product of the bit output and the end signal END.

Therefore, the transistor TR1 is turned on for a predetermined period by the signal Pck pulse-modulated according to the signal Dops, and outputs the voltage Vx (24 V), and the transistor TR1 is turned off during the other periods. Transistor T
While R1 is off, the transistor TR2 or TR3 turns on. That is, the transistor TR2 is turned on by the high level of the signal Dvh0 formed according to the high level of the signal Dovs and by the high level of the signal Dve0, and outputs a pseudo ground level 0+ (2V).
Further, the transistor TR3 is turned on by the high level of the signal Dvh1 formed according to the low level of the signal Dovs and by the high level of the signal Dve1, and outputs the voltage Vx / 2 (12 V). Thereby, the signal D
a signal which is voltage-modulated to a pseudo ground level 0+ and a voltage Vx / 2 according to the high level and the low level of ovs,
Then, an end signal E of the pseudo ground level 0+ or the voltage Vx / 2 is formed according to the command CM.

Output Pc of control data signal generating means 136
k, Dvl and Dvh are the comparators COMP1 to COMP
3 is input to the line driver 137. The line driver 137 includes transistors TR1 to TR3 and the like.

On the basis of the inputs of the outputs Pck, Dvl and Dvh, the line driver 137 controls the power supply voltage V
While superimposing x, the signals (Dvl and Dvh) are level-converted and superimposed. That is, "1 (Vcc = 5V)" of the signal Dvl is converted into a voltage Vx / 2 (12V), and "1 (Vcc = 5V)" of the signal Dvh is converted into a pseudo ground level 0+ (for example, 2V). I do. The voltage Vx / 2 or the pseudo ground level 0+ is superimposed during a period when the signal Pck is at the low level.

As described above, there are two types of slave stations 11. In the low-speed data slave station 11B, the low-speed data slave station output unit 14B having the configuration of FIG. 10 detects and outputs the voltage-modulated second control data signal # 2 (OUT0v to OUT31v). The station input unit 15B outputs the current-modulated second monitoring data signal # 2 (IN0i to IN0i).
31i) to the master station 13. High-speed data slave station 11A
In FIG. 14, the high-speed data slave station output unit 14A having the configuration of FIG.
1 detects the first control data signal # 1 (OUT0p to OUT31p) subjected to pulse width modulation (or phase modulation), and
The high-speed data slave station input section 15A having the configuration of FIG.
Is transmitted to the master station 13.

First, the low-speed data slave station output section 14B will be described. 10 and 11, the signal on the first data signal line D + mainly corresponds to the line receiver 141.
B is input. The line receiver 141B is connected to the data signal line and detects and outputs the state according to a serial pulse voltage signal. Considering the control signals out0 to out31 (serial pulsed voltage signals) on which the clock CK is superimposed, the transmission clock extraction circuit 1421B
A high-level signal is output when the signal on the first data signal line D + is 16 V or more, and a low-level signal is output otherwise. This is the signal d0. That is, it is the data value of the demodulated control signal. This may be considered to include the phase modulated clock CK. The signal d0 or the like is output from the preset addition counter 144B and the shift register 14
51B. As shown in FIG. 11, the waveform of the signal d0 is based on the control signals out0 to out31 (P
WM) The waveform of the modulated clock CK is obtained. Note that C
Since the power supply Vcc is supplied from V, the value of the high level signal of the signal d0 is 5V.

Similarly, the transmission level extracting circuit 1422B receiving the output from the line receiver 141B outputs a low level signal when the signal on the first data signal line D + is 8 V or less, and outputs a high level signal otherwise. Output a signal. This is the data value of the control signal before modulation. This is the signal del.

Prior to this, the start signal ST is similarly detected as the high level of the signal d0 and is input to the start signal extraction circuit 1423B comprising an on-delay timer. The delay is 3t0. That is, the output st
Is delayed by 3t0, and the falling is synchronized with the original signal ST. Therefore, as for the end signal END and the clock CK, the high level time is short.
The output st does not appear. The output st is input to the differentiating circuit ∂, and when the output St rises, the differentiated signal is converted into a preset addition counter 144B and a shift register (SR) 145.
1B and used as a reset signal R thereof. The signal d0 (accordingly, the extracted clock CK) is also input to them.

The address assigned to the low-speed data slave station output unit 14B, for example, addresses 0 to 15 (FIG. 10 shows address 0) is set in the slave station address setting means 143B. The preset addition counter 144B outputs the output s
After being reset by the rising differential signal of t, the extracted clock CK is counted at its rising, and the output dc is output while the count value matches the address of the slave station address setting means 143B. That is, it is set to the high level in synchronization with the rise of the clock CK in the cycle of the immediately preceding address, and is set to the low level in synchronization with the rise of the clock CK in the cycle of the address. In addition, the address 0 is set to a high level in synchronization with the rise of the output st, and is as shown in FIG. The output dc is input to the shift register 1451B.

On the other hand, the signal d0 is an end signal extraction circuit 1491B comprising an on-delay timer with a delay of t0.
And outputs a signal de in the same manner as the start signal extraction circuit 1423B. This signal dE and the signal de
1 and its inverted signal are input to the shift register via an AND gate as shown, and its output, the output of the command setting means 148B and its inverted signal are output via an AND gate and an OR gate as shown. I do. Thus, when the start (and end) cycle number is 0, the signal dc is at a high level, and when the start cycle number is 1, the signal dc is at a low level. In this example, since the output of the command setting unit 148B is “1 off”, that is, 0, the shift register 1451B performs the shift operation when the cycle number of the transmission cycle is 0.

The shift register 1451B outputs the extracted clock CK during the period when the output dc is at the high level.
"1 (or high level)" is shifted in synchronization with the rising edge of. That is, “1” is the shift register 1451
The B unit circuits Sr1 to Sr16 shift in this order. Accordingly, the output s of the shift register 1451B
r1 to sr16 are in the cycle of the clock CK,
In synchronization with the rise, the level is sequentially set to the high level (until the rise of the next cycle). The outputs sr1 to sr16 are
Each is input as a clock to the D-type flip-flop circuits FF1 to FF16.

The flip-flop circuits FF1 to FF16, which are the output low-speed data section 145B, receive a signal d1 (ie, a signal d1).
The data value of the demodulated control signal) is input. Therefore, for example, the flip-flop circuit FF1 outputs the output sr1
In synchronization with the rise of the signal d1, the value of the signal d1 at that time is captured and held, and is output. In this case, a low level is output. Other flip-flop circuits FF2 to FF
Similarly, 16 also takes in and holds the value of the signal d1 at that time and outputs it. As a result, address 0
The value of the data of the control signal at addresses ~ 15 "0011 ..."
Are demodulated as signals out0 to out15, and D / A
Input to the converter DAC. The D / A converter DAC converts predetermined 12 bits into an analog signal (for example, a voltage signal) using predetermined 4 bits of the input 16-bit signal as a control signal, and outputs the low-speed data controlled section. 1
6B.

Next, the low-speed data slave station input section 15B will be described. 12 and FIG. 13, as can be seen from the comparison with FIG. 6 and FIG.
The 0 to address extraction unit 154B has substantially the same configuration as the power supply voltage generation unit 140 to the address extraction unit 144B. That is, while the output low-speed data section 145B is omitted, the input low-speed data section 155B and the line driver 15 are omitted.
7B is added. The assigned address is, for example, the same as the low-speed data slave station output unit 14B (that is, addresses 0 to 15 in this case). Also, the same number of monitor signal data as the number of control signal data to be extracted (16) is input.

The A / D converter ADC of the input low-speed data section 155B converts an analog signal (for example, a voltage signal) input from the low-speed data sensor section 17B into a 12-bit digital signal with a 4-bit control signal. , Signal in0
~ In15 is output. The input low-speed data section 155B
16 of the same number as assigned addresses 0 to 15
It consists of (two or more) two-input AND gates and an OR gate receiving these outputs. As shown in FIG. 12, each of the 16 AND gates has a shift register 1551B.
Output sr1 to sr16 are input. Output sr1-s
As described above, r16 is sequentially set to the high level (until the fall of the next cycle) in synchronization with its fall in the cycle of the clock CK as described above. Therefore, the output sr1
During the high level period of 〜sr16, each of the 16 AND gates is opened, and the monitoring signals in0 to in15 are output from the OR gate via the AND gates in this order. The monitoring signals in0 to in15 are the control signals ou of FIG.
This corresponds to t0 to out15.

The output of the OR gate is input to a two-input NAND gate 1562B. NAND gate 1562B
, The output of the inverter INV2, that is, an inverted signal of the signal d0 is input. NAND gate 1562B forms monitoring data signal generating means 156B. Monitoring signal in
For example, 0 to in15 take values as shown in FIG. 13 during the high level period of the outputs sr1 to sr16. Therefore, while the monitoring signals in0 to in15 are being output, the NAND gate 1 is synchronized with the fall of the signal d0.
562B is opened, and the monitoring signals in0 to in15 are output as the output dip.

The output dip is supplied to the first data signal line D + after level conversion through the line driver 157B.
Is output to That is, the output dip is output from the photocoupler PC
After being electrically separated from the above-described clock extracting unit by the second circuit 2, the signal is input to the transistor TR3p constituting the level conversion circuit and further input to the output transistor TRi.
That is, when the photocoupler PC2 is turned on, the transistors TRp and TRi are turned on. As a result, a signal proportional to the signal dip is output to the first data signal line D +. The high level of this monitoring signal indicates that the transistor TR
Since i becomes high resistance when it is turned off, it depends on the signal potential of the data signal line D +, and the low level is
Since the transistor TRi has a low resistance when turned on, the voltage is set to 4V (because the breakdown voltage of the Zener diode ZD2 is 3V, etc.).

As can be seen from the above, the monitor signal is output from the low-speed data slave station input unit 15B by the (extracted) clock d.
In one cycle of 0, the data is output (superimposed) on the first data signal line D +. However, the first data signal line D
The voltage value of the signal on the + side is forcibly set to the voltage value of the control signal irrespective of the voltage value of the monitor signal. For this,
The line driver 137 of the master station output unit 135 has a sufficiently large driving capability (current supply capability) that can cancel the monitoring signal and set the first data signal line D + to the voltage value of the control signal.

The current flowing through the transistor TRi is limited. For this purpose, the transistor TRi
As shown in FIG. 12, a Zener diode ZDi and a resistor R are connected to the base side of. As a result, the current flowing through the transistor TRi is limited to, for example, 100 mA (milliamps) or less. Therefore, the potential of the first data signal line D + can be easily pulled up to around Vx = 24 V by turning on the transistor TR1 of the master station output unit 135 described above. At the time of this pull-up, since the transistor TRi is ON, a current of about 100 mA temporarily flows through the emitter of the transistor TR1. The flowing time is, for example, 2 μsec. This is detected as Iis.

Next, the high-speed data slave station output unit 14A will be described. 14 and 15, as can be seen from a comparison with FIGS. 10 and 11, the high-speed data slave station output unit 1
4A, the command setting means 148B, the command extraction means 149B, D
This is a configuration excluding the / A converter DAC.

The high-speed data slave station output unit 14A shown in FIG.
The signal d0 is obtained by the same configuration as the low-speed data slave station output unit 14B in FIG. 10, and the outputs sr1 to sr4 are obtained from the unit circuits Sr1 to Sr4 of the shift register 144B. Here, it is assumed that, for example, addresses 0 to 3 (0 is shown in the figure) are specified as addresses of the slave station 11A in the slave station address setting unit 143A. On the other hand, the signal d1
Is formed as shown in FIG. 15 by a phase data signal demodulation circuit 1424A having substantially the same configuration as the start signal extraction circuit 1423A (1423B). That is, when the signal on the first data signal line D + has a level other than the level Vx for a period of 3/4 (or 1/2) CK or more (ie, Vx / 2 or a pseudo ground level), a low level signal is output. Otherwise, a high-level signal is output. Therefore, the signal d1 is substantially the data value of the control signal before the modulation.

The signal d1 (ie, the data value of the demodulated control signal) is input to the flip-flop circuits FF1 to FF4 as the output data section 145A. Therefore, for example, the flip-flop circuit FF1 captures and holds the value of the signal d1 at that time in synchronization with the rise of the output sr1, and outputs this. In this case, a high level is output. The same applies to the other flip-flop circuits FF2 to FF4. As a result, the data value “0011” of the control signal at the addresses 0 to 3 becomes the signal out0p to out
Demodulated as 3p.

Next, the high-speed data slave station input section 15A will be described. 16 and 17, as can be seen from comparison with FIGS. 12 and 13, the high-speed data slave station input unit 1
5A includes a low-speed data slave station input unit 15B to a command setting unit 158B, a command extraction unit 159B, A
This is a configuration excluding the / A converter. The configuration of the input high-speed data section 155A is different from the configuration of the input low-speed data section 155B. Note that the slave station input unit 15 does not need to be aware of whether the monitoring signals in0 to in3 to be superimposed are the first or second monitoring signals.

The high-speed data slave station input unit 15A shown in FIG.
With a configuration similar to that of the low-speed data slave station input unit 15B in FIG. 12, a serial signal of the monitoring signals in0 to in3 synchronized with the extracted clock CK is obtained as the output of the OR circuit. The output of the OR circuit is a two-input AND gate circuit 156.
2A. AND gate circuit 1562A
The other side receives the oscillation output of the oscillator (OSC) 1561. The frequency of this oscillation output is, for example, 8f0. f0 is the frequency of the clock CK. Note that the frequency of the oscillation output is not limited to eight times the frequency of the clock CK, but may be a higher frequency, for example, 16 times.
An AND gate circuit 1562A and an oscillator 1561 are provided as monitoring data signal generating means 156A which is a frequency signal superimposing means.
Is configured. For example, the monitoring signals in0 to in3 take a value “1100” as shown in FIG. 17 during the high level period of the outputs sr1 to sr4. Therefore, while the monitoring signals in0 and in1 are being output, the AND gate circuit 1562A is opened, and the oscillation output 8f0 of the oscillator 1561 is opened.
Is output as an output difp. On the other hand, the monitoring signal i
While n2 and in3 are being output, the AND gate circuit 1562A is closed, and the oscillation output 8f0 of the oscillator 1561 is not output.

The output difp is output to the drivers 1571 and 1571.
572, and is output to the line transformer T.
Power MOSF from line transformer T to line driver
It is applied as a signal dif to the gate electrode of ET. Since the FET repeats on / off according to the signal dif, a signal proportional to the signal dif is output to the first data signal line D +. That is, as shown in FIG. 17, the first monitoring signal is superimposed on the first control signal. The amplitude of the superimposed first monitoring signal is a diode connected in series,
It is limited by the resistance value of the FET and the resistor. When the control signal is at the pseudo ground level 0+ (2 V), the signal has an amplitude within the difference between the true ground level (0 V) and the pseudo ground level 0+ (in this case, within 2 V). Since the monitoring signal is superimposed on the control signal, it should not be a signal affecting the control signal and must be distinguishable therefrom.

Next, the master station input section 139 will be described. 8 and 9 again, the first and second monitoring data signals output on the first data signal line D + are:
The signal is input to the line receiver 1312, and the detection signal is output. This detection signal is sent to the monitoring low-speed data signal detecting unit 1311B and the monitoring high-speed data signal detecting unit 1311B.
A is input to A. Up to this point, the monitoring signal data corresponding to the address position of the monitoring signal data exists at the same address position as the control signal data address position.

The master station input section 139 is a low-speed data monitoring signal detecting means 1311B for detecting the second monitoring data signal.
A current detection circuit for detecting and outputting a change in current on the first data signal line D +. That is, as shown in FIG. 8, a photocoupler PC is inserted on the emitter side of the transistor TR1 forming the line driver 137 of the master station output unit 135. Note that the emitter of the transistor TR2 forming the line driver 137 is connected to a predetermined potential (pseudo ground level 0+, for example, 2 V) without passing through a Zener diode. The photocoupler PC, which is the monitoring low-speed data signal detecting means 1311B,
(And FIG. 4). That is, the current flowing to the emitter side of the transistor TR1 when the power supply voltage Vx rises is detected. The value of the emitter current Iis is determined when the power supply voltage Vx rises.
Depending on the presence or absence of a competing current between the monitoring signal and the monitoring signal, by setting a predetermined threshold value, "0" or "1"
It is said. Therefore, in FIG. 9, the current Iis is indicated by an arrow in the falling direction (competition direction) and a mark “*” (the same applies to the following figures). If the current flowing through the photocoupler PC is equal to or more than a certain value Ith during a period in which the output from the slave station input unit 15 is present, the photocoupler PC is turned on.

As shown in FIG. 18, there are two states based on the monitoring signal "0" or "1", and the magnitude of the current signal Iis is determined. When the monitor signal is "1", a competing current flows between the transistor TR1 and the power supply voltage Vx, so that the emitter current Iis of the transistor TR1 is about 100 mA. On the other hand, when the monitoring signal is “0”,
Since no competing current flows between this and the power supply voltage Vx,
The current Iis is a current equal to the current ip flowing through the slave station output unit 14, the line receiver of the slave station input unit 15, and the power supply voltage generation unit. That is, when the potential on the first data signal line D + is forcibly set to the power supply voltage Vx (= 24 V), the (transistor) of the slave station input unit 15 changes from ON to OFF because there is no data signal. I do. Therefore, when the power supply voltage Vx is forcibly supplied when the monitoring signal is “1”, the pulse current Iis flows. It is assumed that the circuit on the high-speed data slave station 11A side consumes a small amount of current and the current ip is small.

Here, the threshold value Ith = is for detecting the value of the current Iis is determined. The threshold is set to the slave station input unit 15
Of the transistor TR2 of this example is set to an intermediate value between the limit current (about 100 mA) and the current ip. Thereby, the current Iis
Is larger than the threshold value, the monitoring signal “1” is detected, and if the value is the opposite, the monitoring signal “0” is detected. Actually, this threshold value is realized by making the value of the resistor R1 connected to the photocoupler PC appropriate.

As shown in FIG. 9, when the monitor signal is "1" at the rise of the power supply voltage Vx, the transistor of the photocoupler PC is turned on, and the low level is caused by the voltage drop of the collector resistor connected thereto. Inverter INV
Is input to Therefore, a high-level pulse signal is input to the input data unit 138 as the signal Diis. The monitoring low-speed data unit 138B outputs the high-level signal Diis
Take in. Therefore, the monitoring signal "1" can be reliably detected. On the other hand, when the power supply voltage Vx rises, if the monitoring signal is “0”, the transistor of the photocoupler PC is turned off, and the high level is set to the inverter IN.
V. Therefore, the monitoring low-speed data section 138B
Captures a low-level signal Diis. That is, the monitoring signal “0” is detected.

The current signal Iis flowing through the photocoupler PC
Is converted into a voltage signal by a voltage drop in the collector resistor R1 connected thereto, and is input to the flip-flop FF of the monitoring low-speed data extracting means 1310B via the inverter INV. A signal Dick, which is a clock delayed by one cycle from the clock CK, is input from the timing generation unit 132 to the flip-flop FF. Therefore, the signal Diis output from the flip-flop FF outputs the value of only the monitoring data signal at a timing delayed by one cycle from the original clock CK for a period equal to 1/4 cycle or 3/4 cycle of the clock CK. Signal. The signal Diis is input to the monitoring low-speed data section 138B.

The monitoring low-speed data section 138B fetches the input signal Diis into predetermined bits in a predetermined order,
This is held and output until a new data value is input. Therefore, the signal Dick is output from the monitoring low-speed data unit 13.
8B. As a result, in the next cycle of the original clock CK, the signal Diis is output from the monitoring low-speed data unit 1.
It is fetched into a predetermined bit position of the 38B register.
Accordingly, 32 bits from address 0 to address 31 are finally obtained.
Monitoring signals IN0i to IN which are bit parallel data
31i is converted from serial / parallel to the monitored low-speed data unit 13
8B is input to the low-speed data input unit 101B. Thereby, the monitoring signal becomes, for example, "0101 ...
・ ”.

On the other hand, the first monitor signal superimposed on the control signal on the first data signal line D + is output from the line transformer T. The signal from the line transformer T is supplied to the amplifier AMP of the monitoring high-speed data signal detecting means (frequency signal detecting means) 1311A for detecting the first monitoring data signal.
Is input to the comparator COMP4, and is further input to the comparator COMP4, where the waveform is shaped (wave height is made uniform), and the output Difp is output.
Is output as At the output Difp, the data of the monitoring signal corresponding to the data of the control signal exists at the same address position as that of the data of the control signal. The output Difp is supplied to the counter C of the monitoring high-speed data extracting means 1310A via the two-input OR gate circuit OR3.
Input to NT.

The counter CNT counts the number of pulses at the input output Difp for each cycle of the clock CK, and outputs the result as a signal Difs. For this purpose, the reset input of the counter CNT is provided with the signal D
is input through a differentiating circuit ∂, and the count output Difs of the counter CNT is input through a two-input OR gate circuit OR3. The counter CNT outputs the signal D
The signal is reset by the signal “ick”, reset every clock of the signal Dick, and outputs a count result. In this counting, the threshold value N held in the holding means (register, not shown) is used. For example, N = 5. That is, as described later, since the frequency of the first monitoring signal is eight times (8f0) that of the control signal, eight pulses should be counted in one clock CK cycle. Therefore, a value slightly larger than 1/2 is set as the threshold value N. For example, since the data of the monitoring signal at address 0 of the control signal is “1”, the count value becomes eight, and “1 (or high level)” is output as the signal Difs. Since the data of the monitoring signal at address 3 of the control signal is "0", the count value becomes four or less, and "0 (or low level)" is output as the signal Difs. However, since the data of the monitoring signal is counted, the output of the resulting signal Difs is shifted by one from the control signal. For example, the signal Difs of the monitoring signal superimposed on the address 0 of the control signal is 1 of the control signal.
It is output at the address timing. In other words, this is the address 0 of the monitoring signal. Since the period of the end signal END is 1.5 to, the last address (address 31)
, A count result can be output.

The monitoring high-speed data section 138A, like the monitoring low-speed data section 138B, has a monitoring signal IN0 that is 32-bit parallel data from address 0 to address 31.
f to IN31f are serially / parallel converted and input from the monitoring high-speed data unit 138A to the high-speed data input unit 101A. Thereby, the monitoring signal becomes, for example, "1100 ...
・ ”.

Although the present invention has been described in accordance with the embodiments, various modifications are possible within the scope of the present invention.

For example, as shown in FIG. 19, it is preferable to provide a termination unit 18 and / or 19 at one or both ends of the first data signal line D + and the second data signal line D-. The configuration of the terminal units 18 and 19 may be, for example, a configuration as disclosed in Japanese Patent Application No. 1-140826.

Further, for example, as shown in FIG. 19, the master station 13 may be provided with an error check circuit. The error check circuit monitors the first data signal line D + to check the state of the line (such as short circuit). The configuration of the error check circuit may be, for example, as shown in Japanese Patent Application No. 1-140826.

For example, as shown in FIG. 19, when the power supply capacity of the slave station 11 can be satisfied with 24 V superimposed on the first data signal line D + output from the master station 13, the external power supply is changed to the slave station. 11. may be omitted power line P to be supplied to the controlled device 12 (P ₂₄ and P _0).

Although not shown, for example, Japanese Patent Application No.
As shown in No. 140826, the master station output unit 1 of the master station 13
35 and a plurality of master station input units 139 may be provided to correspond to a specific slave station. In this case, the master station output section 135 and the slave station output sections 14 are each provided with m pieces (m ≧ 1), are associated with each other on a one-to-one basis, and have a predetermined sequence for the data signal lines. Connected. On the other hand, the number of master station input units 139 and slave station input units 15 is n (n ≧ n).
1) are provided one by one, and are related in a one-to-one correspondence,
The data signal lines are connected in a predetermined sequence. Each associated part is sequentially operated under the control of a timing signal to transmit control data to the associated controlled part 16 and a monitoring signal from the sensor part 17. Further, such a configuration may be regarded as one group, and a plurality of groups may be provided. The number of stations in each group may be different.

Further, although not shown, the operations in the master station 13 and the slave station 11 are realized by executing the respective processing programs for executing the above-described processing in the CPUs (central processing units) provided respectively. May be.

[0102]

According to the present invention, in the control / monitoring signal transmission system, the first and second control signals and the first and second monitoring signals can be superimposed on the clock signal. It is possible to realize bidirectional high-speed signal transmission between the controlled part and the sensor part, and output a duplicated control signal and a duplicated monitor signal to a common data signal line, and It can be transmitted in both directions at the same time. Further, since the control signal and the monitoring signal can be duplicated, one of the duplicated control signal and the monitoring signal is used for transmitting high-speed data to be transmitted in a short cycle.
The other can be used for transmission of low-speed data sufficient for transmission at a long cycle, and as a result, there is no need to insert low-speed data during transmission of high-speed data, thereby increasing the cycle time of high-speed data transmission. , And high-speed data can be transmitted at a satisfactory transmission speed.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of signal transmission according to the present invention.

FIG. 3 is an explanatory diagram of signal transmission according to the present invention.

FIG. 4 is an explanatory diagram of signal transmission according to the present invention.

FIG. 5 is a basic configuration diagram of the present invention.

FIG. 6 is a basic configuration diagram of the present invention.

FIG. 7 is a basic configuration diagram of the present invention.

FIG. 8 is a configuration diagram of an example of a master station.

FIG. 9 is a waveform chart at the master station in FIG. 8;

FIG. 10 is a configuration diagram of an example of a low-speed data slave station output unit.

11 is a waveform chart at the low-speed data slave station output unit in FIG. 10;

FIG. 12 is a configuration diagram of an example of a low-speed data slave station input unit.

FIG. 13 is a waveform diagram at the low-speed data slave station input unit in FIG. 12;

FIG. 14 is a configuration diagram of an example of a high-speed data slave station output unit.

FIG. 15 is a waveform chart at the high-speed data slave station output unit in FIG. 14;

FIG. 16 is a configuration diagram of an example of a high-speed data slave station input unit.

FIG. 17 is a waveform chart at the high-speed data slave station input unit in FIG. 16;

FIG. 18 is an explanatory diagram of monitoring signal detection.

FIG. 19 is another basic configuration diagram of the present invention.

[Explanation of symbols]

10: control unit 11: slave station 12: controlled device 13: master station 14: slave station output unit 15: slave station input unit 16: controlled unit 17: sensor unit D +: first data signal line D-: second Data signal lines P ₂₄ and P ₀ : power lines

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) DC04 EA14 EB01 EB02 EB05 HA01 HA02

Claims (9)

[Claims] 1. A control unit, comprising a plurality of controlled devices each including a controlled unit and a sensor unit for monitoring the controlled unit, via a data signal line common to the plurality of controlled devices. In a control / monitoring signal transmission system that transmits a control signal from the control unit to the controlled unit and transmits a monitoring signal from the sensor unit to the control unit, a control / monitor signal transmission system connected to the control unit and a data signal line. And a plurality of slave stations provided corresponding to the plurality of controlled devices and connected to the data signal lines and the corresponding controlled devices, between the master station and the plurality of slave stations. Updating the first control data signal and the first monitoring data signal having a short transmission cycle for each transmission cycle determined by a plurality of clocks and mutually transmitting the data signals on the data signal line; 2 monitoring data Timing generating means for updating a signal for each transmission frame consisting of a period longer than the transmission cycle and mutually transmitting on the data signal line, wherein the master station generates a predetermined timing signal synchronized with the clock Under the control of the timing signal, convert the first control data signal and the second control data signal input from the control unit into serial pulsed voltage signals, and output these to the data signal line. A master station output unit, and under control of the timing signal, each data of the first monitoring data signal and the second monitoring data signal superimposed on the serial pulsed voltage signal transmitted through the data signal line And converting them into the monitoring signal,
A master station input unit for inputting to the control unit, wherein the plurality of slave stations each have a value of each data of the first control data signal or a value of the second control data signal under control of the timing signal. A slave station output unit that extracts a value of each data and supplies data corresponding to the slave station in the value of each data to the corresponding controlled unit, and under control of the timing signal, A first monitoring data signal or a second monitoring data signal is formed according to the value of the sensor unit, and these are superimposed on the serial pulsed voltage signal as the data value of the first or second monitoring data signal. A control unit comprising a slave station input unit;
Monitoring signal transmission system. 2. The transmission cycle according to claim 1, wherein the transmission frame in which the second control data signal and the second monitoring data signal are transmitted is the transmission cycle in which the first control data signal and the first monitoring data signal are transmitted. A control / monitoring signal transmission system characterized by being an integral multiple of the following. 3. The plurality of slave stations according to claim 1, wherein the plurality of slave stations include a first slave station and a second slave station, and wherein the first slave station controls the timing signal under the control of the timing signal. A slave station output unit for extracting a value of each data of the first control data signal and supplying data corresponding to the slave station among the values of the data to the corresponding controlled unit; and controlling the timing signal. A slave station input that forms a first monitoring data signal according to a value of the corresponding sensor unit and superimposes the first monitoring data signal on the serial pulse voltage signal as a data value of the first monitoring data signal. The second slave station extracts a value of each data of the second control data signal under control of the timing signal, and corresponds to the slave station in the value of each data. A slave station output unit for supplying data to the corresponding controlled unit; Under the control of the imaging signal, a second monitoring data signal is formed in accordance with the value of the corresponding sensor unit, and this is superimposed on the serial pulse voltage signal as the data value of the second monitoring data signal. A control / monitoring signal transmission system, comprising: 4. The command according to claim 3, wherein the master station is further inserted at the beginning of each of the transmission cycles to generate a command for controlling transmission of the second control data signal and the second monitoring data signal. Generating means, wherein the first slave station ignores the command, and
The value of each data of the control data signal is extracted, and the first
Superimposing the data value of the monitoring data signal, the second slave station extracts the value of each data of the second control data signal when the own station is designated according to the command, A control / monitoring signal transmission system, which superimposes a data value of a second monitoring data signal. 5. The command according to claim 4, wherein the command comprises a start cycle number and an end cycle number indicating a cycle number uniquely assigned to each of the transmission cycles. In the transmission cycle in which the cycle number of the command matches the start cycle number assigned to the own station, the extraction of the value of each data of the second control data signal is started, and the extraction of the data value of the second monitoring data signal is started. The superimposition is started, and in the transmission cycle in which the cycle number of the command matches the end cycle number assigned to the own station, the extraction of the value of each data of the second control data signal is completed, and the second monitoring data signal A control / monitoring signal transmission system characterized by terminating the superimposition of the data value of the control / monitor. 6. The first slave station according to claim 5, wherein, in the first slave station, the slave station output unit counts a clock extracted from the serial pulsed voltage signal and allocates the clock to itself in the transmission cycle in advance. Extracted address, and supply the data of the address to the corresponding controlled unit, the slave station input unit counts the clock extracted from the serial pulsed voltage signal and was previously assigned to itself. Extracting an address, superimposing a monitor signal on the controlled unit on the address of the serial pulsed voltage signal, and arranging the second slave station from the start cycle number assigned to the own station to the end cycle number. Within the period until
The slave station output unit counts a clock extracted from the serial pulsed voltage signal, extracts an address assigned to itself in advance, supplies data of the address to the corresponding controlled unit, and The station input unit counts a clock extracted from the serial pulsed voltage signal, extracts an address assigned to itself in advance, and sends a monitor signal for the controlled unit to the address of the serial pulsed voltage signal. Control / monitoring signal transmission system characterized by superimposing. 7. The second slave station according to claim 6, wherein, in the second slave station, the slave station output unit converts data of the address assigned to the slave unit into an analog signal and supplies the analog signal to the corresponding controlled unit. A control / monitoring signal transmission system, wherein the slave station input unit converts an analog signal that is a monitoring signal for the controlled unit into a digital signal and superimposes the digital signal on an address assigned to the slave unit. 8. The data output device according to claim 1, wherein the master station output unit controls a value of each data of the first control data signal input from the control unit every one cycle of the clock under the control of the timing signal. A duty ratio between a period of a level other than the predetermined power supply voltage level and a subsequent period of the power supply voltage level according to the value of each data of the second control data signal input from the control unit. The first control data signal and the second control data signal in series by setting the level in a period other than the level of the power supply voltage to a predetermined level different from the power supply voltage or a pseudo ground level in accordance with And outputs these to the data signal line. The master station input unit controls the data signal at each cycle of the clock under the control of the timing signal. Detecting a first monitoring data signal comprising a frequency signal superimposed on the serial pulsed voltage signal transmitted through the signal line, and detecting a first monitoring data signal superimposed on the serial pulsed voltage signal transmitted through the data signal line; (2) By detecting the monitoring data signal as the presence or absence of a current signal caused by competition between the monitoring data signal and the power supply voltage when the power supply voltage level rises,
Extracting each data value of the first monitoring data signal and the second monitoring data signal in series, converting them into the monitoring signal, and inputting them to the control unit; Under signal control, for each cycle of the clock, identify a duty ratio between a period of a level other than the power supply voltage level of the serial pulsed voltage signal and a subsequent period of the power supply voltage level. Extracting the value of each data of the first control data signal, or discriminating whether the level in a period other than the level of the power supply voltage is a predetermined voltage level different from the power supply voltage or a pseudo ground level Thereby extracting the value of each data of the second control data signal,
The data corresponding to the slave station among the values of the respective data is supplied to the corresponding controlled unit, and the slave station input unit responds to the value of the corresponding sensor unit under the control of the timing signal. Forming a first monitoring data signal consisting of a frequency signal or a second monitoring data signal consisting of different binary current levels, and using these as the data value of the first or second monitoring data signal, A control / monitoring signal transmission system, which is superimposed on a predetermined position of a voltage signal. 9. The system according to claim 1, wherein the master station outputs a start signal longer than one cycle of the clock to the data signal line at the beginning of the transmission cycle, and one cycle of the clock prior to the start signal. A control / monitor signal transmission system, which outputs an end signal longer than the start signal and superimposes the command on the end signal.