JP2010098068A - Light emitting diode, manufacturing method thereof, and lamp - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting diode which is superior in light extraction efficiency and has high brightness, a manufacturing method thereof, and a lamp using the light emitting diode. <P>SOLUTION: The light emitting diode has a chip structure wherein a compound semiconductor layer 20 including at least a light emission layer is laminated on a principal surface of a substrate and the upper surface side of the compound semiconductor layer 20 is made into a light emission surface 20a, and the substrate is, in a plane view, an approximately regular triangle wherein all of angles between adjacent side surfaces 11b, 11c, and 11d are acute. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a light-emitting diode in which a compound semiconductor layer is laminated on a substrate, a method for manufacturing the same, and a lamp.

Conventionally, as a light emitting diode (LED) that emits red, orange, yellow, or yellowish green visible light, for example, aluminum phosphide, gallium indium (composition formula (Al _X Ga _1-X ) _Y In _1-YP ; A compound semiconductor LED having a light emitting layer composed of 0 ≦ X ≦ 1, 0 <Y ≦ 1) is known. In such an LED, for example, a compound semiconductor layer including a light-emitting layer made of (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1) is generally formed from a light-emitting layer. It is formed on a substrate made of a material such as gallium arsenide (GaAs) that is optically opaque to the emitted light and that is not mechanically strong.

  Recently, for the purpose of obtaining a brighter visible LED and further improving the mechanical strength of the device, the substrate material opaque to the emitted light is removed, and then the emitted light is transmitted or reflected. In addition, a technique is disclosed in which a support (substrate) made of a material having excellent mechanical strength is bonded to a compound semiconductor layer to form a bonded LED (for example, see Patent Documents 1 to 5). According to Patent Documents 1 to 5, it is said that the brightness and mechanical strength of the LED can be improved by bonding a substrate made of a transparent material having excellent mechanical strength to the compound semiconductor layer.

Also, in order to obtain a brighter visible LED, a method for improving the light extraction efficiency by the element shape has been proposed. For example, in the element structure of the light emitting diode, a technique for increasing the luminance by the shape of the element side surface is proposed. It is disclosed (for example, see Patent Document 6). According to the technique described in Patent Document 6, the efficiency of taking out the light emitted from the light emitting layer provided in the compound semiconductor layer to the outside of the device is improved by making the side surface of the substrate an inclined surface (inclined side surface). It is said that a light-emitting diode with high brightness can be obtained.
In addition, a light emitting diode has been proposed in which the element shape is composed of non-equivalent side surfaces and is substantially triangular in plan view (see, for example, Patent Document 7).
Japanese Patent No. 3230638 JP-A-6-302857 JP 2002-246640 A Japanese Patent No. 2588849 JP 2001-57441 A US Pat. No. 6,229,160 JP-T-2004-538663

In the conventional light emitting diodes as described in Patent Documents 1 to 7, a part of the light emitted from the compound semiconductor layer including the light emitting layer is incident on the substrate. For this reason, for example, by extracting the light incident on the inside of the substrate to the outside, the light extraction efficiency can be improved and the luminance of the light emitting diode can be further increased.
However, for example, when using GaP, sapphire, SiC, or the like as the substrate material, the greater the difference in the refractive index between the substrate and the resin covering the LED chip, the light at the shallow incident angle at the interface due to the optical law. Since the light is reflected and returned to the inside of the chip, it is difficult to take it out. For example, when the substrate is configured in a parallelogram, there is a problem in that light has the same incident angle on each facing surface, and thus it is difficult to extract to the outside. In addition, when the substrate is a regular square, rectangle, etc., chemical processing such as roughening is performed so that the crystal surface with high light extraction efficiency is exposed on one of the four side surfaces facing each other. However, there is a problem in that crystal faces having different chemical characteristics are exposed on the other opposing side faces, and the light extraction efficiency on this face is lowered. In such a case, there is a high probability that light incident on the substrate will be reflected and confined inside, and it will be difficult to take out the light to the outside. there were. Further, at the interface between the substrate and the semiconductor layer including the light emitting layer, as described above, there is a problem that light transmission to the substrate side becomes more difficult as the difference in the refractive index between them increases.

  The present invention has been made in view of the above problems, and an object thereof is to provide a light emitting diode excellent in light extraction efficiency and having high luminance, a method for manufacturing the same, and a lamp using the light emitting diode.

The inventors of the present invention have intensively studied to improve the luminance of the light emitting diode, and have completed the following inventions.
That is, the present invention relates to the following.

[1] A light emitting diode having a chip structure in which a compound semiconductor layer including at least a light emitting layer is stacked on a main surface of a substrate, and an upper surface side of the compound semiconductor layer is a light emitting surface. A light emitting diode characterized in that each of the angles between adjacent side surfaces is an acute regular triangle.
[2] The light emitting diode according to the above [1], wherein each side surface of the substrate is made of a crystal plane having a substantially equivalent plane orientation.
[3] The light-emitting diode according to [2], wherein each side surface of the substrate is a (011) plane or a (110) plane.
[4] The light-emitting diode according to any one of [1] to [3], wherein the main surface of the substrate is a (111) plane.
[5] The light-emitting diode according to any one of [1] to [4], wherein each side surface of the substrate is a cleavage plane.
[6] The light-emitting diode according to any one of [1] to [4], wherein each side surface of the substrate is a rough surface.
[7] The light-emitting diode according to any one of [1] to [6], wherein the substrate is made of a translucent material.
[8] The light-emitting diode according to [7], wherein the substrate is made of GaP.
[9] The light-emitting diode according to any one of [1] to [8], wherein a difference in refractive index between the substrate and the light-emitting layer is 0.5 or less.
[10] The light-emitting diode according to any one of [1] to [9], wherein the substrate has a refractive index of 3 or more.

[11] Any one of the above [1] to [10], wherein the compound semiconductor layer is formed by laminating a p-type semiconductor layer, a light emitting layer, and an n-type semiconductor layer on the main surface of the substrate. 2. A light emitting diode according to item 1.
[12] The light-emitting diode according to any one of [1] to [11], wherein the light-emitting surface of the compound semiconductor layer is a (111) plane.
[13] The light-emitting diode according to any one of [1] to [12], wherein the light-emitting layer is made of a III-V group compound semiconductor.
[14] The light emitting diode according to the above [13], wherein the light emitting layer is made of a GaP-based compound semiconductor.
[15] The light-emitting diode according to [13], wherein the light-emitting layer is made of an AlGaInP-based compound semiconductor.

[16] The light emitting device according to any one of [1] to [15], wherein the light emitting surface of the compound semiconductor layer and the substrate are substantially similar in plan view. diode.
[17] The compound semiconductor layer is a layer formed in advance on an epitaxial growth substrate, and the compound semiconductor layer formed in advance is bonded to the main surface of the substrate. The light-emitting diode according to any one of [1] to [16].
[18] The light-emitting diode according to any one of [1] to [17], wherein a length of each side of the substrate that is a substantially equilateral triangle is 600 μm or more.

  [19] An epitaxial process of forming a compound semiconductor layer by laminating at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in this order on an epitaxial growth substrate, and a bonding process of attaching the substrate to the compound semiconductor layer And removing the epitaxial growth substrate from the compound semiconductor layer to expose a light emitting surface, thereby forming a laminated semiconductor wafer, and cutting the laminated semiconductor wafer to form adjacent planar surfaces in a plan view. And a dividing step of dividing the chip into unit chips so that all of the angles are substantially equilateral triangles with acute angles.

[20] A light-emitting diode obtained by the production method according to [19].
[21] A lamp comprising the light-emitting diode according to any one of [1] to [18] or [20].

According to the light-emitting diode of the present invention, a compound semiconductor layer including at least a light-emitting layer is stacked on the main surface of the substrate, and the top surface side of the compound semiconductor layer has a light-emitting surface. In the plan view shape, the angles between adjacent side surfaces are all substantially equilateral triangles having acute angles. The material used for the substrate has a refractive index greater than that of the resin material to be sealed, the internal reflection at the interface is large, and there is an acute angle between the side surfaces of the substrate, and the incident angle on each side surface is different, Since the light incident on the substrate can be prevented from being repeatedly reflected inside, the light extraction efficiency from the side surface of the substrate can be improved.
In addition, when the substrate is configured in a substantially equilateral triangle, each side surface can have substantially equivalent characteristics, and when the light extraction efficiency of all the side surfaces is improved, the light emitted from the substrate side surface to the outside is reduced. On the other hand, when the amount of light extraction from all sides is suppressed, the amount of light extraction from the light emitting diode light emitting surface increases. It becomes possible to set.
Therefore, a light emitting diode with excellent light extraction efficiency and increased luminance can be realized.

  Moreover, according to the lamp of the present invention, since the light emitting diode of the present invention is used, the light emitting characteristics are excellent.

  Hereinafter, a light-emitting diode, a manufacturing method thereof, and a lamp that are embodiments of the present invention will be described with reference to FIGS. 1 to 6 as appropriate. FIG. 1 is a schematic plan view showing a light-emitting diode according to this embodiment, and FIG. 2 is a schematic cross-sectional view of the light-emitting diode shown in FIG. 3 and 4 are schematic views for explaining the method of manufacturing the light emitting diode according to this embodiment, and are cross-sectional views showing the layer structure of the semiconductor laminated wafer. 5 and 6 are schematic cross-sectional views of a lamp using the light emitting diode of this embodiment. The drawings referred to in the following description are for explaining the light emitting diode of the present embodiment, the manufacturing method thereof, and the lamp. The size, thickness, dimensions, and the like of each part shown are the actual light emitting diodes, etc. This is different from the dimensional relationship.

[Laminated structure of light emitting diode (laminated semiconductor wafer)]
In the light emitting diode 1 of the present embodiment, as in the example shown in FIGS. 1 and 2, the compound semiconductor layer 20 including at least the light emitting layer 15 is bonded or stacked on the main surface 11 a of the substrate 11. 1 is a light emitting diode 1 having a chip structure in which the upper surface 20a side (the n-type semiconductor 14 side shown in FIGS. 1 and 2) is a light emitting surface, and a substrate 11 is in a plan view shape and has adjacent side surfaces 11b and 11c. , 11d are generally configured as substantially equilateral triangles having acute angles.
1 and 2, the light emitting surface 20a of the compound semiconductor layer 20 and the substrate 11 (in this example, the entire compound semiconductor layer 20 and the substrate 11) are substantially similar in plan view. It is.

In the light emitting diode 1 of the example shown in FIGS. 1 and 2, an n-type ohmic electrode (negative electrode) 18 is stacked on the n-type semiconductor layer 14, and an exposed region formed in the p-type semiconductor layer 16. A p-type ohmic electrode (positive electrode) 19 is formed on 16d.
Hereinafter, the laminated structure of the light emitting diode 1 of the present embodiment will be described in detail.

"substrate"
Generally, as a substrate material, it is possible to epitaxially grow III-V group semiconductor crystals such as sapphire (α-Al ₂ O ₃ single crystal), silicon carbide (SiC), gallium phosphide (GaP), and GaN on the surface. A substrate material can be appropriately selected and used. Of these, the use of a light-transmitting material is preferable from the viewpoint of improving the light extraction efficiency of the light-emitting diode and increasing the luminance, and among them, the use of GaP is most preferable from the viewpoint of workability and mass productivity. Further, as the substrate material, it is preferable to employ a single crystal substrate capable of making three side surfaces equivalent, but it is also possible to employ an amorphous material such as glass. Furthermore, as a material for the substrate, it is more preferable to adopt a material whose physical properties such as a thermal expansion coefficient and a refractive index are similar to those used for the light emitting layer 15 described later. For example, when a light emitting layer made of AlGaInP is employed, a combination of using a substrate made of GaP and using a substrate made of GaN for a light emitting layer made of GaInN can be mentioned.

  Further, the size of the substrate 11 is usually about 2 inches or 3 inches in diameter, but is not limited to this, for example, a larger or larger substrate such as a circular or rectangular substrate having a diameter of 4 to 6 inches. It is also possible to use a substrate.

  Conventionally used as a support substrate of a light emitting diode, for example, when a single crystal substrate made of a material such as GaP is divided into a square chip such as a quadrangle in a plan view, one opposing side surface and the other opposing surface The side faces have different structures of exposed crystal faces, and in particular, chemical characteristics may be different. In such a case, for example, when a crystal surface (coarse surface) with high light extraction efficiency is exposed on one opposing side surface by chemical treatment, the surface on the other opposing side surface becomes rough. In addition, since the crystal plane that is not so high in light extraction efficiency is exposed, there is a problem in that the light extraction efficiency on each of the other opposing side surfaces is low. In addition, the light emitting diode having such a conventional configuration has a problem that light extraction from each side surface of the chip is not uniform.

On the other hand, the board | substrate 11 with which the light emitting diode 1 of this invention is equipped is planar view shape, and is comprised as a substantially equilateral triangle with which all the angles between the adjacent side surfaces 11b, 11c, and 11d are acute angles. Thus, by making the substrate 11 of the light-emitting diode 1 into a substantially equilateral triangle, the change in angle between the side surfaces 11b, 11c, and 11d is increased, and is substantially equivalent to each of the side surfaces 11b, 11c, and 11d of the substrate 11. It becomes possible to expose the crystal plane of the plane orientation.
Further, when the principal surface 11a of the substrate 11 is a (111) plane, each of the side surfaces 11b, 11c, and 11d is composed of a crystal plane having a substantially equivalent plane orientation including chemical properties, and the crystal plane has a light extraction efficiency. By making the crystal plane appropriate for improving the above, that is, the (011) plane or a plane off the same angle from this plane, the light incident on the substrate 11 is repeatedly reflected inside. Can be suppressed. Therefore, light incident on the substrate 11 from the compound semiconductor layer 20 described later is not repeatedly reflected inside the substrate 11 and can be efficiently extracted toward the outside of the substrate 11.

  As described above, in the light emitting diode 1 according to the present invention, the light emitted from the light emitting layer 15 provided in the compound semiconductor layer 20 described later is also incident on the substrate 11 through the main surface 11a. Such light incident on the inside of the substrate 11 is formed on each of the side surfaces 11b, 11c, and 11d by configuring the side surfaces 11b, 11c, and 11d of the substrate 11 as substantially equivalent crystal planes as described above. The light extraction characteristic is also substantially equivalent.

Here, for example, when each side surface 11b, 11c, 11d of the substrate 11 is formed in a mirror shape as a cleavage plane, the light extraction amount from each side surface 11b, 11c, 11d is suppressed, and the compound semiconductor layer 20 The light incident on the inside of the substrate 11 is emitted from the main surface 11 a side and travels toward the compound semiconductor layer 20 again. Thereby, the light emission ratio from the light emitting surface 20a side of the light emitting diode 1 increases.
On the other hand, when the side surfaces 11b, 11c, and 11d of the substrate 11 are roughened by, for example, mechanical processing, a chemical processing method, etc., the light extraction efficiency of the side surfaces 11b, 11c, and 11d is further increased. The amount of light extraction from the side surface is further increased, and the light extraction characteristics become substantially equivalent characteristics.
As described above, when the side surfaces 11b, 11c, and 11d of the substrate 11 are configured by crystal planes having substantially equivalent plane orientations, the light extraction efficiency of all the side surfaces 11b, 11c, and 11d is improved. When the light emitted to the outside from each side surface increases and the light extraction amount of all the side surfaces 11b, 11c, and 11d is suppressed, the luminance from the light emitting surface 20a side of the light emitting diode 1 is increased. Thus, for example, it is possible to appropriately set the direction in which light is efficiently extracted according to the usage pattern of the light emitting diode. Therefore, it is possible to realize the light emitting diode 1 having higher luminance.

In the light emitting diode according to the present invention, it is necessary to select the crystal plane orientation of the main surface 11a of the substrate 11. In the present embodiment, it is particularly preferable that the main surface 11a of the substrate 11 is a (111) plane from the viewpoint that a compound semiconductor layer having good crystallinity can be formed.
Further, when the substrate 11 is divided with the main surface 11a as the (111) plane, the substrate 11 has a characteristic that it has a surface (cleavage surface) that is easily broken along the crystal planes in three directions. Further, in this case, since the surfaces having the same characteristics are exposed on all of the six surfaces which are the side surfaces of the (111) surface, when the substrate 11 is divided into substantially equilateral triangles, all the surfaces including the chemical characteristics are included. It can be easily configured as a substantially equivalent characteristic.

  Further, as a method of cutting the substrate 11 into a substantially equilateral triangle as described above to expose a crystal plane having a substantially equivalent plane orientation and dividing the substrate 11 into element units, for example, a conventionally known dicing saw or the like is used. Can do. In this case, although there is no size restriction, for example, one side is about 400 μm, and all the side surfaces 11b, 11c, and 11d of the substrate 11 are in the range of 0 to 30 degrees off-plane from the (110) plane. It can be set as the method of giving a cutting | judgement and cut | disconnecting to a substantially equilateral triangle by planar view. Alternatively, the side surfaces 11b, 11c, and 11d can be (110) planes, and the side surfaces 11b, 11c, and 11d can be mirrored by cutting by a scribing method. As a cutting technique used at this time, when a small chip is cut, the yield may be reduced. Therefore, a relatively large chip whose length per side of a substantially equilateral triangle is 600 μm or more. It is preferable to configure.

  In the light emitting diode according to the present invention, the difference in refractive index between the substrate 11 and the light emitting layer 15 provided in the compound semiconductor layer 20 described later in detail is preferably 0.5 or less. By setting the refractive index between the substrate 11 and the light emitting layer 15 within the above range, light emitted from the light emitting layer 15 (compound semiconductor layer 20) is easily incident on the substrate 11, so that the luminance can be further increased. It becomes possible. Further, the refractive index of the substrate 11 is more preferably 3 or more from the viewpoint of further enhancing the above effect.

Compound semiconductor layer
As shown in FIGS. 1 and 2, a compound semiconductor layer 20 including a p-type semiconductor layer 16, a light emitting layer 15, and an n-type semiconductor layer 14 in this order is provided on the main surface 11 a of the substrate 11. Yes.
In the illustrated example, the compound semiconductor layer 20 of the present embodiment is substantially similar to the substrate 11 in a plan view shape. The compound semiconductor layer 20 described in the present embodiment is a layer formed in advance on the epitaxial growth substrate 30 (see FIGS. 3 and 4), which will be described in detail in a manufacturing method described later. Reference numeral 1 denotes a structure in which a surface 16 a of a p-type semiconductor layer 16 provided in a compound semiconductor layer 20 formed in advance is bonded onto a main surface 11 a of a substrate 11.

The compound semiconductor layer 20 of the present embodiment has a laminated semiconductor structure including the light emitting layer 15 and is formed on the main surface 11a of the substrate 11 as shown in the schematic cross-sectional view of FIG. 2 (see also FIGS. 3 and 4). , P-type semiconductor layer 16, light-emitting layer 15, and n-type semiconductor layer 14 are sequentially stacked. The general formula (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1, A III-V group compound semiconductor represented by 0 <Y ≦ 1) can be preferably used.
Specifically, the compound semiconductor layer 20 has a structure as described below.

The p-type semiconductor layer 16 has p-type characteristics doped with a predetermined amount of Mg, Zn or the like, and is a p-type contact layer made of, for example, GaP. As a raw material for doping Mg, for example, known biscyclopentadiethyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) is used.
In the present invention, the GaP is preferably used for the p-type semiconductor layer 16 in order to further improve the luminance. However, for example, any III-V group compound semiconductor crystal such as AlGaAs, AlGaInP, etc. It is possible to employ without limitation.

Emitting layer 15 is provided on the p-type semiconductor layer 16, in this order from the p-type semiconductor layer 16 side, for example, a p-type characteristics doped Mg, and Zn or the _{like, (Al} 0.7 Ga _0.3) and _0.5 an in _0.5 P a p-type cladding layer and _{(Al 0.5 Ga 0.5) 0.5 in} 0.5 P of a thin film made of p-type cladding layer 15c, an undoped A barrier layer made of (Al _0.2 Ga _0.8 ) _0.5 In _0.5 P and a well layer made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P are alternately 20 a multi-quantum well layer 15b are laminated in pairs, Si, having n-type properties doped with Te or the like _{(Al 0.7} Ga _0.3) n-type cladding layer 15a composed of 0.5 _{an in 0.5} P And are laminated. At this time, without a known light emitting layer 15 (multi-quantum well layer 15b) having a structure such as a multiple quantum well _{layer, (Al X Ga 1-X} ) Y In 1-Y P (0 ≦ X ≦ 1,0 < The configuration of the barrier layer and the well layer having a composition of Y ≦ 1) can be appropriately determined so that a desired emission wavelength can be obtained. In addition, the composition, thickness, carrier concentration, and the like of the barrier layers forming the p-type cladding layer 15c, the n-type cladding layer 15a, and the multiple quantum well layer 15b may be adjusted as appropriate so that the light emission efficiency is increased. Moreover, in the light emitting diode of this embodiment, it is also possible to set it as the layer structure which switched the said n-type and p-type polarity.

  The material of the light emitting layer 15 is not limited to the above-described example, and any known material such as GaInN-based or AlGaAs-based material can be used, but the light-emitting layer made of a GaP-based compound semiconductor that is directly grown on the GaP substrate. No. 15 can be suitably used from the point that a pasting process is unnecessary. In particular, a combination of an AlGaInP system with high luminous efficiency and a GaP substrate is most preferable.

  The light emitting layer 15 provided in the light emitting diode 1 of the present embodiment has a so-called pn junction type double heterojunction structure composed of a p-type cladding layer 15c, a multiple quantum well layer 15b, and an n-type cladding layer 15a. Yes. The light emitting layer 15 can employ a known structure such as a double hetero structure in order to confine carriers.

The multiple quantum well layer 15b as described above can be composed of a compound semiconductor of either n-type or p-type conductivity.
In addition, the light emitting layer 15 of the present embodiment is configured to include a multiple quantum well layer 15b having a multiple quantum well structure (MQW) having the above-described configuration. This is not a limitation. For example, in addition to the multiple quantum well structure, a single quantum well (SQW) structure can be adopted, but a multiple quantum well structure is preferable in order to obtain light emission excellent in monochromaticity. .
Such a light emitting layer 15 can be formed on the surface of a single crystal substrate such as lattice-matched GaAs or a III-V group compound semiconductor such as InP or GaP. In addition to the structure of the light emitting layer, a functional layer which is a conventionally known technique, for example, a contact layer, a current diffusion layer, a current element layer, or the like can be provided.

The n-type semiconductor layer 14 is provided on the light emitting layer 15 and has an n-type characteristic in which Si, Te, and Sn are doped with a predetermined amount. For example, the Si-doped (Al _0.5 Ga _{0. 5} ) An n-type contact layer made of _0.5 In _0.5 P. For example, disilane (Si ₂ H ₆ ) is used as a raw material for doping Si.

Further, as in the example shown in FIGS. 1 and 2, the light emitting surface 20 a of the compound semiconductor layer 20 is substantially similar to the substrate 11 in a plan view, which further improves the luminance of the light emitting diode 1. To preferred. In the illustrated example, the upper surface of the compound semiconductor layer 20, that is, the light emitting surface 20 a that is the upper surface of the n-type semiconductor layer 14 is below the position except for the position corresponding to the exposed region 16 d formed on the p-type semiconductor layer 16. The substrate 11 is substantially similar to the substrate 11 in plan view.
Further, as illustrated, the entire compound semiconductor layer 20 is configured to be substantially similar to the substrate 11 in a plan view, and each of the side surfaces 20b, 20c, and 20d of the compound semiconductor layer 20 is replaced with each side surface 11b of the substrate 11, The formation along the lines 11c and 11d is preferable in that the luminance of the light emitting diode 1 can be further increased.

"N-type ohmic electrode and p-type ohmic electrode"
The n-type ohmic electrode 18 is an electrode provided on the n-type semiconductor layer 14 described above. As the material and structure of the n-type ohmic electrode 18, for example, various configurations such as an AuGe / Ni alloy film and a laminated film made of an Au film are well known, and these known materials and structures are used without any limitation. Can do.

The p-type ohmic electrode 19 is provided in contact with the p-type semiconductor layer 16 in a semiconductor layer in which the p-type semiconductor layer 16, the light emitting layer 15, and the n-type semiconductor layer 14 are sequentially stacked on the substrate 11. Therefore, when the p-type ohmic electrode 19 is provided, the exposed region 16a of the p-type semiconductor layer 16 is formed by removing at least a part of the n-type semiconductor layer 14 and the light emitting layer 15, and the p-type ohmic electrode 19 is formed thereon. An ohmic electrode 19 is formed.
As the material of the p-type ohmic electrode 19, various configurations such as an AuBe alloy film and a laminated film made of an Au film are well known, and can be provided by conventional means well known in this technical field.

  As described above, according to the light emitting diode 1 according to the present invention, the compound semiconductor layer 20 including at least the light emitting layer 15 is stacked on the main surface 11a of the substrate 11, and the upper surface side of the compound semiconductor layer 20 is the light emitting surface 20a. The substrate 11 is configured to be a substantially equilateral triangle in which the angle between the adjacent side surfaces 11b, 11c, and 11d is an acute angle in a plan view. The material used for the substrate 11 has a refractive index larger than that of the resin material, the internal reflection at the interface is large, and there is an acute angle between the side surfaces 11b, 11c, and 11d of the substrate 11, and the side surfaces 11b, 11c, Since the incident angles at 11d are different, it is possible to suppress the light incident on the substrate 11 from being repeatedly reflected inside, so that it is possible to improve the light extraction efficiency from the side surfaces 11b, 11c, and 11d. .

  Further, when the substrate 11 is configured in a substantially equilateral triangle, the side surfaces 11b, 11c, and 11d can have substantially equivalent characteristics, and the light extraction efficiency of all the side surfaces 11b, 11c, and 11d is improved. The light emitted from the side surface of the substrate increases to the outside. On the other hand, when the light extraction amount of all the side surfaces 11b, 11c, and 11d is suppressed, the light extraction amount from the light emitting surface 20a of the light emitting diode 1 increases. Therefore, it is possible to appropriately set the direction in which light is efficiently extracted according to the usage pattern of the light emitting diode. Therefore, a light emitting diode with excellent light extraction efficiency and increased luminance can be realized.

  Further, the present invention is not limited to the coplanar electrode type light emitting diode as shown in the examples shown in FIG. 1 and FIG. 2. For example, the upper and lower electrode type in which an ohmic electrode is formed on a substrate made of GaP. The same effect can be obtained even when applied to a device, and in this case, it is possible to realize an upper and lower electrode type light emitting diode excellent in luminance.

  The present invention includes, for example, an AlGaInP light emitting diode obtained by attaching a compound semiconductor layer to a (111) plane substrate made of GaP as in the example described in the present embodiment, and a single GaP (111) plane. This is a suitable example because it can be easily applied to yellow-green and red GaP light-emitting diodes obtained by epitaxially growing a compound semiconductor layer including a light-emitting layer on a crystal substrate by a liquid phase epitaxial method (LPE method).

[Method for manufacturing light-emitting diode]
In the method of manufacturing the light emitting diode according to the present embodiment, the compound semiconductor layer 20 is formed by stacking at least the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 in this order on the epitaxial growth substrate 30. A bonding step of attaching the substrate 11 to the compound semiconductor layer 20, a removal step of forming the laminated semiconductor wafer 21 by removing the epitaxial growth substrate 30 from the compound semiconductor layer 20 to expose the light emitting surface 20a, A step of cutting the semiconductor wafer 21 into a light emitting diode 1 by dividing the semiconductor wafer 21 into chips in element units so that all the angles between the adjacent side faces are acute angles substantially equilateral triangles in a plan view shape. It is a prepared method. Moreover, in the manufacturing method of this embodiment, the process of forming an electrode is provided between the said removal process and a division | segmentation process.
Moreover, in the said division | segmentation process with which the manufacturing method of this embodiment is equipped, each side surface of the board | substrate 11 which comprises the laminated semiconductor wafer 21, and the compound semiconductor layer 20, ie, each side surface 11b, 11c, 11d of the board | substrate 11, and a compound Each of the side surfaces 20b, 20c, and 20d of the semiconductor layer 20 is divided in a plan view shape so that the angles between the adjacent side surfaces are all substantially equilateral triangles with acute angles.

In this embodiment, the n-type ohmic electrode 18 is stacked on the n-type semiconductor layer 14, and the p-type ohmic electrode 19 is stacked on the exposed region 16 d formed on the p-type semiconductor layer 16. A forming step is provided (see FIGS. 1 and 2).
Hereinafter, the manufacturing method of the light emitting diode of this embodiment is explained in full detail.

"Epitaxial process"
In the epitaxial process, first, an epitaxial growth substrate 30 made of GaAs single crystal having n-type characteristics doped with Si and inclined by 15 ° from the (100) plane is prepared, and an n-type semiconductor is formed on this substrate. The layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are laminated in this order to form the compound semiconductor layer 20.
In this embodiment, as an epitaxial process, first, a buffer layer 13 made of n-type GaAs doped with Si is formed on an epitaxial growth substrate 30, and a Si-doped (Al _0.5 Ga ₀₎ is formed thereon. _.5) having n-type characteristics of _0.5 an in _0.5 n-type semiconductor layer 14 made of P, Si-doped _{(Al 0.7} Ga _0.3) n-type cladding consisting of 0.5 _{an in 0.5} P a layer 15a, undoped _{(Al 0.2 Ga 0.8) 0.5 in} 0.5 a barrier layer made of P _{(Al 0.7} Ga _0.3) wells consisting of 0.5 _{an in 0.5} P A multiple quantum well layer 15b in which 20 layers are alternately stacked, and a second layer made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P having Mg-doped p-type characteristics. cladding layer and _{(Al 0.5 Ga} 0.5) _.5 an In _0.5 P of the p-type cladding layer 15c and the light-emitting layer 15 formed by laminating of a thin film, and an example of sequentially stacking a p-type semiconductor layer 16 made of GaP having a p-type characteristics of Mg-doped explain.

In the epitaxial process of this embodiment, trimethylaluminum ((CH ₃ ) ₃ Al), trimethyl is formed when the buffer layer 13, the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 having the above composition are formed. Each layer is formed on the substrate 30 for epitaxial growth by a low pressure metal organic chemical vapor deposition method (MOCVD method) used as a raw material for gallium ((CH ₃ ) ₃ Ga) and trimethylindium ((CH ₃ ) ₃ In) group III constituent elements. Can be formed.

As described above, biscyclopentadiethylmagnesium (bis- (C ₅ H ₅ ) ₂ Mg) is used as the Mg raw material to be doped when forming the p-type cladding layer 15 c and the p-type semiconductor layer 16. it can. Further, disilane (Si ₂ H ₆ ) can be used as a raw material of Si to be doped when forming the n-type semiconductor layer 14 and the n-type cladding layer 15a.
In addition, phosphine (PH ₃ ) or arsine (AsH ₃ ) can be used as a raw material for the group V constituent element.

  As a growth temperature when forming the compound semiconductor layer 20, for example, the p-type semiconductor layer 16 made of GaP can be grown at about 700 to 780 ° C. In addition to the other layers, that is, the n-type semiconductor layer 14 and the light emitting layer 15, the growth temperature of each layer including the barrier layer 13 can be grown at about 700 to 780 ° C.

Here, the buffer layer 13 made of GaAs has a carrier concentration of about 0.1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ , which is about the same as that of a single crystal substrate, and a film thickness of about 0.1 to 1 μm. It can be.
_{Further, (Al 0.5 Ga 0.5) 0.5} In 0.5 n -type semiconductor layer 14 made of P is a carrier concentration of about ^{0.1 × 10 18 cm -3 ~5 ×} 10 18 cm -3 The film thickness can be about 1 to 8 μm.
The n-type cladding layer 15a constituting the light emitting layer 15 can have a carrier concentration of about 1 × 10 ¹⁷ cm ⁻³ to 30 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.1 to 2 μm. The multiple quantum well layer 15b is undoped and can have a thickness of about 0.2 to 2 μm. The p-type cladding layer 15c can have a carrier concentration of about 1 × 10 ¹⁷ cm ^{−3 to} 20 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.1 to ³ μm.
The p-type semiconductor layer 16 can have a carrier concentration of about 0.5 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and a film thickness of about 0.5 to 20 μm. If the thickness of the p-type semiconductor layer 16 is small, current diffusion becomes insufficient and current is not uniformly supplied to the light emitting layer 15, which may cause a decrease in light emission efficiency. Further, when the film thickness is unnecessarily thick, the cost increases, and the layer growth may be technically difficult. Furthermore, when the carrier concentration of the p-type semiconductor layer 16 is low, current diffusion becomes insufficient, and when it is too high, the crystal quality may be deteriorated.

"Joining process"
Next, in the bonding step, the substrate 11 is attached to the compound semiconductor layer 20 on the p-type semiconductor layer 16 side.

As the substrate 11, for example, a GaP single crystal substrate in which Si is added so that the carrier concentration is about 0.5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ and the plane orientation is (111). Is preferably used. Further, as the diameter of the substrate 11, for example, one having a diameter of about 50 mm and a thickness of about 50 to 250 μm, which is usually used in the field of stacked semiconductors, can be used without any limitation. Further, the substrate 11 is finished to a mean square value (rms) of 1 nm or less, more preferably 0.2 nm or less by mirror polishing the main surface 11a.

Next, the p-type semiconductor layer 16 of the compound semiconductor layer 20 and the substrate 11 are joined. At this time, a commonly used semiconductor material pasting apparatus can be used, and any known method such as a thermocompression bonding method or an adhesive can be used. It can be used without limitation. Among them, it is preferable to use a room temperature bonding method with low stress and high bonding strength. In such a method, first, a compound semiconductor is placed on the substrate 11 and the epitaxial growth substrate 30 in the semiconductor material pasting apparatus. The wafer on which the layer 20 is formed is carried in, and the inside of the apparatus is depressurized in vacuum.
Next, both the main surface 11a of the substrate 11 and the p-type semiconductor layer 16 are irradiated with an Ar beam. Then, the principal surface 11a of the substrate 11 and the p-type semiconductor layer 16 (surface 16a) of the compound semiconductor layer 20 are overlapped, and a load is applied so that the pressure on each surface is 10 to 500 g / cm ² . Join directly at room temperature.

  In addition, although detailed illustration is abbreviate | omitted, in this embodiment, it can be set as the method of interposing the sticking board | substrate between the board | substrate 11 and the p-type semiconductor layer 16 with which the compound semiconductor layer 20 is equipped. In such a case, for example, the substrate 11 is bonded to the compound semiconductor layer 20 after the bonding substrate is bonded to the surface 16a of the p-type semiconductor layer 16 provided in the compound semiconductor layer 20 or the substrate 11. It can be a procedure.

"Removal process"
Next, in the removing step, the laminated semiconductor wafer 21 is formed by removing the epitaxial growth substrate 30 from the compound semiconductor layer 20 and exposing the light emitting surface 20a.
Specifically, it is preferable to employ a method of selectively etching the epitaxial growth substrate 30 and the buffer layer 13 using mechanical polishing, ammonia-based etchant, or the like.

"Electrode formation process"
Next, in the electrode formation step, the n-type ohmic electrode 18 is stacked on the n-type semiconductor layer 14 and the p-type ohmic electrode 19 is stacked on the exposed region 16d formed on the p-type semiconductor layer 16 (FIG. 1). And see FIG.

  Specifically, first, an n-type ohmic electrode 18 is formed on the n-type semiconductor layer 14. For example, the n-type ohmic electrode 18 is formed by sequentially depositing an AuGe / Ni alloy film having a thickness of 0.1 to 1 μm and an Au film having a thickness of 1 to 3 μm in order from the n-type semiconductor layer 14 side by vacuum deposition. After the deposition, patterning is performed using a general photolithography means to form a shape as shown in FIGS.

  When the p-type ohmic electrode 19 is formed, first, a part of the n-type semiconductor layer 14 and the light-emitting layer 15 on the substrate 11 is removed by a method such as wet etching or dry etching, whereby a p-type semiconductor is formed. An exposed region 16d of the layer 16 is formed. Then, on this exposed region 16d, for example, in order from the surface side of the exposed region 16d, an AuBe alloy film having a thickness of 0.1 to 1 μm, AuZn, and a thickness using a general vacuum deposition method, a sputtering method, or the like. A laminated film with an Au film having a thickness of 1 to 3 μm is deposited. Then, heat treatment is performed at a temperature of 400 to 500 ° C. for 10 minutes, and alloying is performed to form the p-type ohmic electrode 19 having a low contact resistance. At this time, a barrier metal such as Pt, Ti, Cr, or W may be interposed between the alloy layer and the Au film.

"Division process"
Next, in the dividing step, the laminated semiconductor wafer 21 is cut by dicing, and is divided into chips in element units so that all the angles between the adjacent side faces become acute triangles in a plan view shape. Set to 1.

Specifically, first, the compound semiconductor layer 20 is removed by etching along a scribe line which is a cutting scheduled line.
Next, using a dicing saw, all the side surfaces 11b, 11c, and 11d of the substrate 11 are cut so that each of the side surfaces 11b, 11c, and 11d is off by 30 degrees from the (110) surface. By cutting into a substantially equilateral triangle, a chip-like light emitting diode 1 is obtained.

In addition, after division | segmentation by dicing, a crushing layer may arise in each side surface 11b, 11c, 11d by cutting. In such a case, the crushed layer may be removed by performing chemical etching on the side surfaces 11b, 11c, and 11d.
Further, as described above, when the side surfaces 11b, 11c, and 11d are roughened for the purpose of improving the light extraction efficiency from the inside of the substrate 11, the side surfaces 11b, 11c, and 11d are further chemically treated. It is preferable to use the method of applying from the viewpoint of low cost.

  In the present embodiment, the method of forming the side surfaces 11b, 11c, and 11d with the (110) plane 30 degrees off is described as an example. For example, the side surfaces 11b, 11c, and 11d are set to (110). It is also possible to make each side surface 11b, 11c, and 11d into a mirror surface by cutting the surface by a scribing method. When the side surfaces 11b, 11c, and 11d are mirror surfaces, the light extraction amount from each of the side surfaces is suppressed, but the light extraction amount from the light emitting surface 20a that is the upper surface side of the light emitting diode 1 is increased. In addition, by combining various plane orientations and cutting methods, it is possible to manufacture a light-emitting diode chip in which light extraction characteristics from each side surface are intermediate characteristics.

[lamp]
Using the light emitting diode according to the present invention, a lamp can be constituted by means well known to those skilled in the art. As such a lamp, it can be used for any purpose such as a bullet type for general use, a side view type for portable equipment, and a top view type used for a display.

For example, as in the example shown in FIGS. 5 and 6, when the coplanar electrode type light emitting diode 1 is mounted in a top view type, an n electrode terminal 43 and a p electrode provided on the surface of the mounting substrate 45. The substrate 11 side of the light emitting diode 1 is bonded to one of the terminals 44 (n electrode terminal 43 in FIGS. 5 and 6), and the p-type ohmic electrode 19 of the light emitting diode 1 is connected to the p electrode terminal 44 by a wire 46. The n-type ohmic electrode 18 is bonded to the n-electrode terminal 43 by the wire 47. Then, by molding the periphery of the light emitting diode 1 with a mold resin 41 made of a transparent resin, a top view type lamp 4 as shown in FIGS. 5 and 6 can be manufactured.
The lamp 4 of the present embodiment is formed by using the light emitting diode 1 according to the present invention, and therefore has extremely high luminance and excellent light emission characteristics.

  Hereinafter, the light-emitting diode, the manufacturing method thereof, and the lamp of the present invention will be described in more detail by way of examples. However, the present invention is not limited to these examples.

[Example 1]
1 and 2 are schematic views of a light-emitting diode manufactured in this example, FIG. 1 is a plan view, and FIG. 2 is a cross-sectional view taken along the line II shown in FIG. 3 and 4 are cross-sectional views showing the layer structure of the semiconductor laminated wafer, and FIGS. 5 and 6 are schematic cross-sectional views of lamps manufactured using the light-emitting diodes shown in FIG.
In the present embodiment, an epitaxial laminated structure (semiconductor laminated wafer) provided on an epitaxial growth substrate made of GaAs and a substrate made of GaP are joined, and the light emitting layer is made of an AlGaInP-based compound semiconductor and emits red light. A diode was manufactured, and a top view type lamp was manufactured using the light emitting diode.

“Growth of compound semiconductor layers (epitaxial process)”
First, an epitaxial growth substrate 30 made of a GaAs single crystal having n-type characteristics doped with Si and having a surface inclined by 15 ° from the (100) plane was prepared.
Then, a buffer layer 13 made of n-type GaAs doped with Si is first formed on the epitaxial growth substrate 30, and Si-doped (Al _0.5 Ga _0.5 ) _0.5 In is formed thereon. _An n-type semiconductor layer 14 made of _0.5 P, an n-type cladding layer 15 a made of Si-doped n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, and an undoped ( 20 pairs of barrier layers made of Al _0.2 Ga _0.8 ) _0.5 In _0.5 P and well layers made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P alternately a multi-quantum well layer 15b formed by laminating, has the p-type characteristics of _{Mg-doped, (Al 0.7 Ga 0.3) 0.5} in 0.5 second cladding layer made of P and _{(Al 0.} consisting ₅ Ga _0.5) of _0.5 an in _0.5 P film Emitting layer 15 and the type cladding layer 15c are laminated, and were sequentially stacked a p-type semiconductor layer 16 made of GaP having a p-type characteristics of Mg-doped.

In this embodiment, when the buffer layer 13, the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 having the above composition are formed, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium (( Each layer was formed on the substrate 30 for epitaxial growth by a low pressure metal organic chemical vapor deposition method (MOCVD method) used as a raw material of a group ₃ constituent element of CH ₃ ) ₃ Ga) and trimethylindium ((CH ₃ ) ₃ In).

Further, biscyclopentadiethylmagnesium (bis- (C ₅ H ₅ ) ₂ Mg) is used as a raw material of Mg doped into the p-type cladding layer 15 c and the p-type semiconductor layer 16, and the n-type semiconductor layer 14 and the n-type semiconductor layer 14 are used. Disilane (Si ₂ H ₆ ) was used as a raw material for Si doped into the cladding layer 15a.
Further, phosphine (PH ₃ ) or arsine (AsH ₃ ) was used as a raw material for the group V constituent element.
As the growth temperature of each layer, the p-type semiconductor layer 16 made of GaP is grown at 750 ° C., and the layers including the n-type semiconductor layer 14 and the light emitting layer 15 and the barrier layer 13 are grown at 730 ° C. It was.

In the film forming process, the buffer layer 13 made of GaAs was formed with a carrier concentration of about 5 × 10 ¹⁸ cm ⁻³ and a film thickness of about 0.2 μm.
The n-type semiconductor layer 14 was formed with a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a film thickness of about 1.5 μm.
The n-type cladding layer 15a constituting the light emitting layer 15 has a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a film thickness of about 1 μm, and the multiple quantum well layer 15b is undoped and has a film thickness of about 0.8 μm. In addition, the p-type cladding layer 15c was formed with a carrier concentration of about 2 × 10 ¹⁷ cm ⁻³ and a film thickness of about 1 μm.
The p-type semiconductor layer 16 was formed with a carrier concentration of about 3 × 10 ¹⁸ cm ⁻³ and a film thickness of about 9 μm.

  Through the above process steps, the compound semiconductor layer 20 was formed by laminating the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 in this order on the epitaxial growth substrate 30.

“Bonding of compound semiconductor layer and substrate (bonding process)”
Next, the substrate 11 was attached to the p-type semiconductor layer 16 side of the compound semiconductor layer 20 formed in the above process.
At this time, first, mirror polishing is performed by polishing a region extending from the surface of the p-type semiconductor layer 16 to a depth of about 1 μm so that the surface roughness of the p-type semiconductor layer 16 is about 0.18 nm. did.
Further, a substrate 11 made of GaP was prepared as a support substrate for bonding to the surface of the p-type semiconductor layer 16. The substrate 11 is a single crystal substrate in which Si is added so that the carrier concentration is about 2 × 10 ¹⁷ cm ⁻³ and the plane orientation is (111), and the diameter is about 50 mm and the thickness is about 250 μm. We prepared what was said. Furthermore, the principal surface 11a of the substrate 11 was mirror-polished to obtain a square average square root value (rms) of about 0.12 nm. Further, in this example, as shown in FIG. 2, a pasting substrate made of the same material as the substrate 11 described above, thinner than the substrate 11 and subjected to the same mirror polishing treatment was prepared.

Next, the wafer on which the compound semiconductor layer 20 was formed on the substrate 11, the substrate for pasting, and the substrate for epitaxial growth 30 was carried into the semiconductor material pasting device, and the inside of the device was decompressed to about 3 × 10 ⁻⁵ Pa. Next, the main surface 11a of the substrate 11, both surfaces of the pasting substrate, and the surface of the p-type semiconductor layer 16 were each irradiated with a neutral Ar beam neutralized by colliding electrons with each other for about 3 minutes. In the apparatus maintained in a vacuum, the main surface 11a of the substrate 11 and one surface of the pasting substrate, and the other surface of the pasting substrate and the surface of the p-type semiconductor layer 16 are overlapped, and the pressure on each surface is 200 g / cm. By applying a load so as to be ² , bonding was performed directly at room temperature.

“Removal of epitaxial growth substrate (removal process)”
Next, the substrate for epitaxial growth 30 was removed from the compound semiconductor layer 20 to expose the light emitting surface 20a, whereby the laminated semiconductor wafer 21 was formed. At this time, the epitaxial growth substrate 30 and the buffer layer 13 were selectively removed using an ammonia-based etchant or the like.

“Formation of n-type ohmic electrode and p-type ohmic electrode (electrode formation process)”
Next, the n-type ohmic electrode 18 was stacked on the n-type semiconductor layer 14, and the p-type ohmic electrode 19 was stacked on the exposed region 16 d formed on the p-type semiconductor layer 16.

  First, an AuGe / Ni alloy film having a thickness of 2 μm and an Au film having a thickness of 1 μm are sequentially deposited on the light emitting surface 20a of the exposed n-type semiconductor layer 14 in this order, By patterning with a lithography means, an n-type ohmic electrode 18 having a shape as shown in FIGS. 1 and 2 was formed.

  Further, an exposed region 16d of the p-type semiconductor layer 16 was formed by removing part of the n-type semiconductor layer 14 and the light emitting layer 15 on the substrate 11 by dry etching. Then, a laminated film of an AuBe alloy film having a thickness of 0.2 μm and an Au film having a thickness of 1.8 μm was deposited in this order on the exposed region 16d using a vacuum deposition method. Thereafter, a p-type ohmic electrode 19 having a low contact resistance was formed by performing a heat treatment at a temperature of 450 ° C. for 10 minutes to form an alloy.

"Chip division (division process)"
Next, the laminated semiconductor wafer 21 was cut by dicing, and divided into chips in element units so that all the angles between adjacent side faces in a plan view shape were substantially equilateral triangles with acute angles.
First, after removing the compound semiconductor layer 20 by etching along the cutting line, all of the side surfaces 11b, 11c, and 11d of the substrate 11 are turned off by 30 degrees from the (110) plane using a dicing saw. Cutting was performed as follows. Further, after the division by dicing, the crushed layer generated on each of the side surfaces 11b, 11c, and 11d by cutting was removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution. Further, the side surfaces 11b, 11c, and 11d were dipped in a hydrochloric acid-based etchant to finish each of the side surfaces 11b, 11c, and 11d to a rough surface.
Through the above procedures, a chip-shaped light emitting diode 1 having a shape of a plan view and a substantially equilateral triangle having a side of 700 μm was manufactured.

"Production of lamp"
By mounting the light emitting diode 1 obtained by the above procedure, a top view type lamp 4 as shown in FIGS. 5 and 6 was produced.
First, the substrate 11 side of the light emitting diode 1 was bonded to the n-electrode terminal 43 provided on the surface of the mounting substrate 45. Next, the p-type ohmic electrode 19 of the light-emitting diode 1 was joined to the p-electrode terminal 44 with a wire 46, and the n-type ohmic electrode 18 was joined to the n-electrode terminal 43 with a wire 47. Then, a lamp 4 as shown in FIGS. 5 and 6 was manufactured by molding the periphery of the light emitting diode 1 with a mold resin 41 made of a transparent resin.

“Measurement of luminous characteristics”
Next, for the lamp 4 on which the light-emitting diode 1 obtained by the above procedure is mounted, between the n-type ohmic electrode 18 and the p-type ohmic electrode 19 via the n-electrode terminal 43 and the p-electrode terminal 44. When a forward current was passed, red light having a dominant wavelength of 620 nm was emitted. Further, the forward voltage (Vf) when a forward current of 20 mA was passed between the electrodes was about 2.0 V, reflecting good ohmic characteristics. In addition, the emission intensity when the forward current is 20 mA is improved by the configuration of the compound semiconductor layer and the substrate as described above, and the side surface of the substrate is roughened, and the light extraction efficiency to the outside is increased. As a result, the brightness was improved to 700 mcd.

  From the above results, it is clear that the light-emitting diode according to the present invention and the lamp using the light-emitting diode have excellent light extraction efficiency and high luminance.

[Example 2]
In this example, the same as that of Example 1 above, except that a GaP substrate 12 whose main surface 12a is a (111) surface is used and the upper and lower electrode structures are as shown in FIGS. 7 (a) and 7 (b). The light emitting diode 2 was produced by the method described above.

“Attaching GaP substrate”
In this example, a GaP substrate 12 which is a p-type GaP single crystal substrate was attached to the p-type semiconductor layer 16 (surface 16a) side of the compound semiconductor layer 20 formed in the same procedure as in Example 1.
The GaP substrate 12 is a p-type single crystal substrate in which Zn is added so that the carrier concentration is about 1 × 10 ¹⁸ cm ⁻³ and the plane orientation is (111), the diameter is about 50 mm, and the thickness is Is about 250 μm. Furthermore, the main surface 12a of the substrate 12 was mirror-polished to obtain a square average square root value (rms) of about 0.11 nm.

“Formation of n-type ohmic electrode and p-type ohmic electrode (electrode formation process)”
Next, an n-type ohmic electrode 28 was stacked on the n-type semiconductor layer 14 and a p-type ohmic electrode 29 was stacked on the GaP substrate 12 made of p-type GaP.

"Production of lamp"
By mounting the light emitting diode 2 obtained by the above procedure, a top-view type lamp was manufactured in the same manner as the lamp 4 shown in FIGS.

“Measurement of luminous characteristics”
For the lamp in which the light emitting diode 2 obtained by the above procedure is mounted, a forward current is passed between the n-type ohmic electrode 28 and the p-type ohmic electrode 29 via the n-electrode terminal and the p-electrode terminal. As a result, red light having a dominant wavelength of 620 nm was emitted. Further, the forward voltage (Vf) when a forward current of 20 mA was passed between the electrodes was about 2.0 V, reflecting good ohmic characteristics. In addition, the emission intensity when the forward current is 20 mA is improved by the configuration of the compound semiconductor layer and the substrate as described above, and the side surface of the substrate is roughened, and the light extraction efficiency to the outside is increased. As a result, the brightness was improved to 600 mcd.
From the above results, it has been clarified that the light emitting diode 2 according to the present invention using a GaP substrate and having an upper and lower electrode structure and the lamp using the same have excellent light extraction efficiency and high luminance.

[Comparative example]
In this comparative example, a light-emitting diode was produced in the same manner as in Example 1 except that when the substrate was divided, the substrate was divided into a square of 350 μm per side along a line that was turned off by 45 degrees from the (110) plane. Further, a top view type lamp was manufactured by using the light emitting diode in the same manner as in Example 1.

About the lamp on which the light emitting diode manufactured in this comparative example is mounted, when a forward current is passed between each electrode of the n-type ohmic electrode and the p-type ohmic electrode via the n-electrode terminal and the p-electrode terminal, Red light having a dominant wavelength of 620 nm was emitted. Further, the forward voltage (Vf) when a forward current of 20 mA was passed between the electrodes was about 2.0 V, reflecting good ohmic characteristics. However, the emission intensity when the forward current was 20 mA was 450 mcd, which was inferior to those of Examples 1 and 2. This is because the light-emitting diode manufactured in this comparative example has a roughened side surface, which improves the light extraction efficiency from each side surface to the outside, but the substrate is formed in a square shape. This is probably because the light extraction from each side of the chip is uneven.
Thus, it became clear that the light-emitting diode having a square substrate manufactured in this comparative example has lower light extraction efficiency than the light-emitting diodes of Examples 1 and 2 according to the present invention.

  From the above results, it is clear that the light emitting diode according to the present invention and the lamp using the same are excellent in light extraction efficiency and have high luminance.

It is a top view which illustrates typically an example of the light emitting diode which concerns on this invention. It is a figure which illustrates an example of the light emitting diode which concerns on this invention typically, and is II sectional drawing shown in FIG. It is a figure which illustrates typically an example of the light emitting diode which concerns on this invention, and is sectional drawing which shows the layer structure of a semiconductor laminated wafer. It is a figure which illustrates typically an example of the light emitting diode which concerns on this invention, and is sectional drawing which shows the layer structure of a semiconductor laminated wafer. It is a top view explaining typically an example of the lamp | ramp which uses the light emitting diode which concerns on this invention. It is a figure which illustrates an example of the light emitting diode which concerns on this invention typically, and is KK sectional drawing shown in FIG. It is a figure which illustrates typically an example of the light emitting diode which concerns on this invention, and is the schematic which shows the light emitting diode of an upper-lower electrode structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 ... Light emitting diode 11, 12 ... Board | substrate, 11a, 12a ... Main surface, 11b, 11c, 11d ... Side surface (board | substrate), 14 ... N type semiconductor layer, 15 ... Light emitting layer, 16 ... P type semiconductor layer, DESCRIPTION OF SYMBOLS 20 ... Compound semiconductor layer, 20a ... Light emission surface, 20b, 20c, 20d ... Side surface (compound semiconductor layer), 21 ... Semiconductor laminated wafer, 30 ... Epitaxial growth substrate, 4 ... Lamp

Claims (21)

A light emitting diode having a chip structure in which a compound semiconductor layer including at least a light emitting layer is stacked on a main surface of a substrate, and an upper surface side of the compound semiconductor layer is a light emitting surface,
The light emitting diode according to claim 1, wherein the substrate has a shape in plan view and is a substantially equilateral triangle in which angles between adjacent side surfaces are all acute angles.   2. The light emitting diode according to claim 1, wherein each side surface of the substrate is made of a crystal plane having a substantially equivalent plane orientation.   The light emitting diode according to claim 2, wherein each side surface of the substrate is a (011) plane or a (110) plane.   The light emitting diode according to any one of claims 1 to 3, wherein a main surface of the substrate is a (111) plane.   5. The light-emitting diode according to claim 1, wherein each side surface of the substrate is a cleavage plane.   5. The light-emitting diode according to claim 1, wherein each side surface of the substrate is a rough surface.   The light emitting diode according to any one of claims 1 to 6, wherein the substrate is made of a translucent material.   The light emitting diode according to claim 7, wherein the substrate is made of GaP.   9. The light emitting diode according to claim 1, wherein a difference in refractive index between the substrate and the light emitting layer is 0.5 or less.   The light emitting diode according to claim 1, wherein the substrate has a refractive index of 3 or more.   11. The compound semiconductor layer according to claim 1, wherein a p-type semiconductor layer, a light emitting layer, and an n-type semiconductor layer are stacked on a main surface of the substrate. Light emitting diode.   The light emitting diode according to any one of claims 1 to 11, wherein the light emitting surface of the compound semiconductor layer is a (111) surface.   The light emitting diode according to any one of claims 1 to 12, wherein the light emitting layer is made of a group III-V compound semiconductor.   The light emitting diode according to claim 13, wherein the light emitting layer is made of a GaP-based compound semiconductor.   The light emitting diode according to claim 13, wherein the light emitting layer is made of an AlGaInP-based compound semiconductor.   The light emitting diode according to any one of claims 1 to 15, wherein the light emitting surface of the compound semiconductor layer and the substrate are substantially similar in plan view.   The compound semiconductor layer is a layer formed in advance on a substrate for epitaxial growth, and the compound semiconductor layer formed in advance is bonded to the main surface of the substrate. Item 17. The light-emitting diode according to any one of Item 16.   18. The light-emitting diode according to claim 1, wherein a length of each side of the substrate that is a substantially equilateral triangle is 600 μm or more. An epitaxial step of forming a compound semiconductor layer by laminating at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in this order on an epitaxial growth substrate;
A bonding step of attaching a substrate to the compound semiconductor layer;
Removing the epitaxial growth substrate from the compound semiconductor layer to expose the light emitting surface, thereby forming a laminated semiconductor wafer; and
A step of cutting the laminated semiconductor wafer and dividing the wafer into chip units in an element unit so that all of the angles between adjacent side faces are acutely equilateral triangles in a shape in plan view. A method for manufacturing a light emitting diode.   The light emitting diode obtained by the manufacturing method of Claim 19.   A lamp comprising the light emitting diode according to any one of claims 1 to 18 or claim 20.

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