KR101364167B1

KR101364167B1 - Vertical light emitting diode and method of fabricating the same

Info

Publication number: KR101364167B1
Application number: KR1020070016151A
Authority: KR
Inventors: 김창연; 윤여진; 김윤구
Original assignee: 서울바이오시스 주식회사
Priority date: 2007-02-15
Filing date: 2007-02-15
Publication date: 2014-02-18
Also published as: KR20080076344A

Abstract

The present invention provides a vertical light emitting diode, comprising: a conductive substrate, a metal reflective layer formed on the conductive substrate, an N-type semiconductor layer formed on the metal reflective layer, an active layer formed on the N-type semiconductor layer, and P formed on the active layer. Provided is a vertical light emitting diode including a semiconductor layer.

According to the present invention, since a vertical light emitting device having a structure in which a conductive substrate is bonded to an N-type semiconductor layer can be fabricated, leakage in the bonding interface between a thin thickness P-GaN and a conductive substrate in a conventional vertical light emitting device structure Due to the formation of the current, it is possible to solve the problem that the luminous efficiency of the vertical LED is reduced.

VLED, vertical, diode, light emitting, roughing

Description

Vertical light emitting diode and its manufacturing method {VERTICAL LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME}

1 is a cross-sectional view for explaining a vertical light emitting diode according to the prior art.

2 is a cross-sectional view illustrating a vertical light emitting diode according to an embodiment of the present invention.

3 to 8 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode according to an embodiment of the present invention.

9 is a cross-sectional view for describing a vertical light emitting diode according to another exemplary embodiment of the present invention.

51: sacrificial substrate 53: buffer layer

55: N-type semiconductor layer 57: active layer

59: P-type semiconductor layer 61: adhesive layer

63: SiO ₂ layer 65: bonding metal layer

71: temporary substrate 81: metal reflective layer

83: adhesive layer 91: sacrificial substrate

93: electrode pad

The present invention relates to a vertical light emitting diode and a method of manufacturing the same, and more particularly, to a vertical light emitting diode in which the P-type electrode is located on top of the light emitting diode and a method of manufacturing the same.

In general, nitrides of Group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition energy band structure. As a lot of attention. In particular, blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high-density light sources, high resolution output systems and optical communication.

The nitride semiconductor layer of such a group III element, in particular, GaN, is difficult to fabricate a homogeneous substrate capable of growing it, and thus, it is difficult to fabricate a homogeneous substrate capable of growing it, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy; MBE) and other processes. A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate. However, since sapphire is an electrical insulator, it restricts the light emitting diode structure, and is very stable mechanically and chemically, making it difficult to process such as cutting and shaping, and low thermal conductivity. In recent years, a technology for growing a nitride semiconductor layer on a heterogeneous substrate such as sapphire and then separating the heterogeneous substrate to fabricate a vertical-type LED has been researched.

1 is a cross-sectional view illustrating a conventional vertical light emitting diode.

Referring to FIG. 1, the vertical type light emitting diode includes a conductive substrate 31. The compound semiconductor layers including the N-type semiconductor layer 15, the active layer 17, and the P-type semiconductor layer 19 are located on the conductive substrate 31. In addition, a metal reflection layer 23 and an adhesive layer 27 are interposed between the conductive substrate 31 and the P-type semiconductor layer 19.

Compound semiconductor layers are generally grown on a sacrificial substrate (not shown), such as a sapphire substrate, using metalorganic chemical vapor deposition or the like. Thereafter, the metal reflection layer 23 and the adhesive layer 27 are formed on the compound semiconductor layers, and the conductive substrate 31 is attached. Subsequently, the sacrificial substrate is separated from the compound semiconductor layers using a laser lift-off technique or the like, and the N-type semiconductor layer 15 is exposed. Thereafter, an electrode pad 33 is formed on the exposed N-type half body layer 15. Accordingly, by adopting the conductive substrate 31 having excellent heat-releasing performance, the light-emitting efficiency of the light-emitting diode can be improved, and the light-emitting diode of FIG. 1 having a vertical structure can be provided.

However, in the conventional vertical light emitting diode, the thickness of P-GaN used as the P-type semiconductor layer 19 bonded to the conductive substrate 31 is about 1000 to 3000 mW. Therefore, a leakage current may be formed at the junction interface between the thin P-GaN 19 and the conductive substrate 31, thereby reducing the luminous efficiency of the vertical LED.

An object of the present invention is to improve the light emitting efficiency by improving the junction structure between the compound semiconductor layer and the conductive substrate in the structure of the vertical light emitting diode.

According to one aspect of the present invention for achieving the above technical problem, in a vertical light emitting diode, a conductive substrate, a metal reflective layer formed on the conductive substrate, an N-type semiconductor layer formed on the metal reflective layer, and the N-type Provided is a vertical light emitting diode comprising an active layer formed on a semiconductor layer and a P-type semiconductor layer formed on the active layer.

Preferably, the vertical light emitting diode may further include a transparent electrode layer formed of ITO or Ni / Au on the P-type semiconductor layer.

Preferably, the N-type semiconductor layer may be a surface in contact with the metal reflection layer is roughened.

Preferably, the vertical light emitting diode may further include an adhesive layer interposed between the metal reflective layer and the conductive substrate, and a diffusion barrier layer interposed between the adhesive layer and the metal reflective layer.

According to another aspect of the invention, the step of forming a compound semiconductor layer comprising an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the sacrificial substrate, and forming a temporary substrate on the P-type semiconductor layer via an adhesive layer Separating the sacrificial substrate to expose the N-type semiconductor layer, forming a metal reflective layer on the exposed N-type semiconductor layer, forming a conductive substrate on the metal reflective layer, and forming the compound semiconductor It provides a vertical light emitting diode manufacturing method comprising the step of separating the temporary substrate from the layer.

Preferably, the vertical light emitting diode manufacturing method may further include forming a diffusion barrier layer and an adhesive layer on the metal reflection layer before forming the conductive substrate.

Preferably, the temporary substrate forming step may form a temporary substrate on the P-type semiconductor layer through the polymer-based adhesive film.

Preferably, the forming of the temporary substrate may include forming a SiO ₂ layer on the P-type semiconductor layer, forming a bonding metal on the SiO ₂ layer, and forming a temporary substrate on the bonding metal. Can be.

Preferably, the sacrificial substrate separation step separates the sacrificial substrate through laser lift-off, and the metal reflection layer forming step forms a metal reflection layer thereon while the N-type semiconductor layer exposed through the laser lift-off is roughened. can do.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

Referring to FIG. 2, compound semiconductor layers including an N-type semiconductor layer 55, an active layer 57, and a P semiconductor layer 59 are positioned on the conductive substrate 91. The conductive substrate 91 is a substrate such as Si, GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN or InGaN, but Al, Zn, Ag, W, Ti, Ni, Au, Mo, Pt, Pd, Cu, It may be a single metal of Cr or Fe or an alloy substrate thereof. On the other hand, the compound semiconductor layers are III-N compound semiconductor layers. For example, an (Al, Ga, In) N semiconductor layer.

The n-type semiconductor layer 55 is subjected to roughing. Accordingly, light generated from the active layer can be reflected at the roughened interface.

A metal reflection layer 81 is interposed between the compound semiconductor layers and the conductive substrate 91. The metal reflection layer 81 is formed of a metal material having a high reflectance such as silver (Ag) or aluminum (Al).

Meanwhile, an adhesive layer 83 may be interposed between the metal reflection layer 81 and the conductive substrate 91, and the adhesive layer 83 may improve the adhesion between the conductive substrate 91 and the metal reflection layer 81 to form the conductive substrate 91. ) Is prevented from being separated from the metal reflection layer 81.

In addition, although not shown, a diffusion barrier layer may be interposed between the adhesive layer 83 and the metal reflection layer 81. The diffusion barrier layer may maintain the reflectivity of the metal reflection layer 81 by preventing the metal elements from being diffused from the adhesive layer 83 or the conductive substrate 91 into the metal reflection layer 81.

Meanwhile, the electrode pad 93 is positioned on the upper surface of the compound semiconductor layers to face the conductive substrate 91. Accordingly, light can be emitted by supplying a current through the conductive substrate 91 and the electrode pad 93.

Referring to FIG. 3, compound semiconductor layers are formed on the sacrificial substrate 51. The sacrificial substrate 51 may be a sapphire substrate, but is not limited thereto and may be another hetero substrate. The compound semiconductor layers include an N semiconductor layer 55, an active layer 57, and a P-type semiconductor layer 59. The compound semiconductor layers are III-N-based compound semiconductor layers, and may be grown by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE).

Meanwhile, the buffer layer 53 may be formed before forming the compound semiconductor layers. The buffer layer 53 is adopted to mitigate lattice mismatch between the sacrificial substrate 51 and the compound semiconductor layers, and may generally be a gallium nitride-based material layer.

Referring to FIG. 4, the temporary substrate 71 is formed on the compound semiconductor layers through the adhesive layer 61. The adhesive layer 61 may be a polymer-based adhesive film, but is not limited thereto. The temporary substrate 71 may be, for example, a sapphire substrate, but is not limited thereto.

Referring to FIG. 5, the sacrificial substrate 51 is separated from the compound semiconductor layers. The sacrificial substrate 51 may be separated by laser lift off (LLO) technology or other mechanical or chemical methods. At this time, the buffer layer 53 is also removed to expose the N-type semiconductor layer 55.

Referring to FIG. 6, the N-type semiconductor layer 55 is roughened by performing photoelecrochemical (PEC) etching while the N-type semiconductor layer 55 exposed by the laser lift-off (LLO) technique is exposed. As the rough surface is formed on the N-type semiconductor layer 55 through the roughing process, the light reflectance is improved at the interface between the rough surface of the N-type semiconductor layer 55 and the metal reflective layer 81.

Referring to FIG. 7, the metal reflection layer 81 is formed on the roughened N-type semiconductor layer 55. The metal reflection layer 81 may be formed using, for example, plating or vapor deposition of silver (Ag) or aluminum (Al).

On the other hand, a conductive substrate 91 is formed on the metal reflection layer 81. The conductive substrate 91 is a substrate such as Si, GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN or InGaN, but Al, Zn, Ag, W, Ti, Ni, Au, Mo, Pt, Pd, Cu, It can be formed by attaching a single metal of Cr or Fe or an alloy substrate thereof onto the compound semiconductor layers. In this case, the conductive substrate 91 may be attached to the metal reflection layer 81 through the adhesive layer 83, and the conductive substrate 91 may be formed using a plating technique. That is, the conductive substrate 91 may be formed by plating a metal such as Cu or Ni on the metal reflection layer 81, and an adhesive layer 83 may be added to improve adhesion.

In addition, although not shown, a diffusion barrier layer for preventing diffusion of metal elements may be formed on the metal reflection layer 81 before forming the adhesive layer 83.

Referring to FIG. 8, the temporary substrate 71 is separated from the compound semiconductor layers. The sacrificial substrate 71 may be separated by laser lift off (LLO) technology or other mechanical or chemical methods.

At this time, the adhesive layer 61 is also removed to expose the P-type semiconductor layer 59. Subsequently, an electrode pad 93 is formed on the P-type semiconductor layer 59. The electrode pad 93 is in ohmic contact with the P-type semiconductor layer 59.

Although not shown, an electrode pad 93 may be formed after forming a conductive transparent electrode layer such as ITO or Ni / Au on the P-type semiconductor layer 59. When the transparent electrode layer is formed, the light efficiency may be further improved. .

Meanwhile, in the present embodiment, a method of manufacturing a single vertical light emitting diode has been described. In general, a plurality of vertical light emitting diodes may be manufactured by cutting the conductive substrate 91 and separating them into individual LED chips. In this case, electrode pads 93 are formed on the light emitting diode chip regions, and the conductive substrate 91 is cut along predefined scribing lines.

Referring to FIG. 9, the vertical light emitting diode according to the present embodiment is compared with the vertical light emitting diode described with reference to FIG. 4, and instead of the adhesive layer on the compound semiconductor layers, the SiO ₂ layer 63 and the bonding metal layer ( The structure for forming the temporary substrate 71 via 65 is different, and the other components are the same.

The invention being thus described, it will be obvious that the same way may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention as defined by the appended claims.

For example, in the exemplary embodiment of the present invention, the roughening treatment is performed on the surface of the N-type semiconductor layer in contact with the metal reflective layer. However, the present invention is not limited thereto. .

In addition, when the roughening process is performed on the N-type semiconductor layer to be bonded to the metal reflective layer while the rough surface is formed, the light generated from the active layer can be reflected at the roughened interface to further improve the vertical light emitting diode emission efficiency. Can be improved.

Claims

In a vertical light emitting diode,

A conductive substrate,

A metal reflective layer formed on the conductive substrate;

An N-type semiconductor layer formed on the metal reflective layer,

An active layer formed on the N-type semiconductor layer,

A P-type semiconductor layer formed on the active layer,

An adhesive layer interposed between the metal reflective layer and the conductive substrate;

A diffusion barrier layer interposed between the adhesive layer and the metal reflective layer;

It includes a transparent electrode layer formed on the p-type semiconductor layer,

The n-type semiconductor layer is a vertical light emitting diode having a surface in contact with the metal reflective layer roughened.

The vertical light emitting diode of claim 1, wherein the transparent electrode layer is formed of ITO or Ni / Au.

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Forming compound semiconductor layers including an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the sacrificial substrate;

Forming a temporary substrate on the P-type semiconductor layer through an adhesive layer;

Separating the sacrificial substrate to expose the N-type semiconductor layer;

Forming a metal reflective layer on the exposed N-type semiconductor layer;

Forming a diffusion barrier layer on the metal reflective layer;

Forming an adhesive layer on the diffusion barrier layer;

Forming a conductive substrate on the metal reflective layer;

Separating the temporary substrate from the compound semiconductor layer;

And separating the temporary substrate to expose the P-type semiconductor layer, and forming a transparent electrode layer on the exposed P-type semiconductor layer.

delete

The method of claim 5, wherein the temporary substrate forming step,

The method of claim 1, wherein a temporary substrate is formed on the P-type semiconductor layer through a polymer-based adhesive film.

The method of claim 5, wherein the temporary substrate forming step,

Forming a SiO ₂ layer on the P-type semiconductor layer,

Forming a bonding metal on the SiO ₂ layer,

And forming a temporary substrate on the bonding metal.

The method of claim 5,

The sacrificial substrate separation step of separating the sacrificial substrate through a laser lift off,

The metal reflective layer forming step of forming a metal reflective layer on the N-type semiconductor layer exposed through the laser lift-off is roughening process, characterized in that for forming a vertical light emitting diode.