[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP2008228347A - High-frequency power amplifier module - Google Patents

High-frequency power amplifier module Download PDF

Info

Publication number
JP2008228347A
JP2008228347A JP2008136687A JP2008136687A JP2008228347A JP 2008228347 A JP2008228347 A JP 2008228347A JP 2008136687 A JP2008136687 A JP 2008136687A JP 2008136687 A JP2008136687 A JP 2008136687A JP 2008228347 A JP2008228347 A JP 2008228347A
Authority
JP
Japan
Prior art keywords
transistor
electrode
bonding
power amplifier
amplifier module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008136687A
Other languages
Japanese (ja)
Inventor
Osamu Kagaya
修 加賀谷
Kenji Sekine
健治 関根
Hidekazu Hase
英一 長谷
Kiichi Yamashita
喜市 山下
Shizuo Kondo
静雄 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2008136687A priority Critical patent/JP2008228347A/en
Publication of JP2008228347A publication Critical patent/JP2008228347A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency power amplifier module capable of more improving high-frequency characteristics. <P>SOLUTION: In a high-frequency power amplifier module wherein a semiconductor chip including multiple amplification stage transistors is installed on a wiring board, an angle formed with a first auxiliary line connecting bonding portions at both ends of an input bonding wire 105 connecting a gate electrode (input electrode for bonding) 102a corresponding to a certain single first-stage transistor (amplification stage transistor) 102 and a wiring board 113 and a second auxiliary line connecting bonding portions at both ends of an output bonding wire 108 connecting a drain electrode (output electrode for bonding) 103b corresponding to a second-stage transistor (amplification stage transistor) 103 positioned on the stage next to the single amplification stage transistor and the wiring board 113 is set to 72° to 180°, and an interval between the bonding portions of the gate electrode (input electrode for bonding) 102a and the drain electrode (output electrode for bonding) 103b is set to 0.3 mm or more. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明はＵＨＦからマイクロ波帯の信号の増幅を行う高周波電力増幅器モジュールに係り、特に小型化の必要な携帯電話機に用いられる高周波電力増幅器モジュールに関する。   The present invention relates to a high-frequency power amplifier module that amplifies a signal in the microwave band from UHF, and more particularly, to a high-frequency power amplifier module used in a mobile phone that needs to be downsized.

トランジスタを用いた高周波電力増幅器モジュールはＰＤＣ（Ｐｅｒｓｏｎａｌ Ｄｉｇｉｔａｌ Ｃｅｌｌｕｌａｒ）方式、ＧＳＭ（Ｇｒｏｂａｌ Ｓｙｓｔｅｍ ｆｏｒ Ｍｏｂｉｌｅ ｃｏｍｍｕｎｉｃａｔｉｏｎｓ）方式等の移動体通信の携帯電話機のキーデバイスであり、その需要は近年急激に伸びている。また、その仕様としては、移動体通信システムに対する高周波特性の他、小型、低価格であることが要求されている。   A high-frequency power amplifier module using a transistor is a key device of a mobile communication mobile phone such as a PDC (Personal Digital Cellular) system or a GSM (Global System for Mobile communications) system, and the demand thereof has been increasing rapidly in recent years. In addition to the high-frequency characteristics for the mobile communication system, the specifications are required to be small and inexpensive.

この要求に応える一つの方法が特許第２７５５２５０号公報（特許文献１）に記載されている。図１１の平面図，図１２の斜視図に示すように，１つの半導体チップ１上に２個のトランジスタ２，３を近接して配置することにより、小型、低価格化している。また、初段トランジスタ２のボンディング用入力電極２ｂと配線基板のボンディング用電極７ｄは入力ボンディングワイヤ９ｄで接続されている。２段目トランジスタ３のボンディング用出力電極３ｃと配線基板６のボンディング用電極７ａは出力ボンディングワイヤ９ａで接続されている。半導体チップ１上のボンディング用電極１０ａと配線基板６のボンディング用電極１２ａはシールド用ボンディングワイヤ１３ａで接続されている。シールド用ボンディングワイヤ１３ａは入力ボンディングワイヤ９ｄと出力ボンディングワイヤ９ａとの間に設けられており、かつその両端のボンディング用電極１０ａと１２ａは各々半導体チップ１および配線基板に形成されたバイアホール（Ｖｉａ Ｈｏｌｅ（図示せず））を通して高周波的に接地されている。このシールド用ボンディングワイヤ１３ａを設けることにより、入力ボンディングワイヤ９ｄと出力ボンディングワイヤ９ａとの間の相互インダクタンスによる結合が低減して高周波入出力端子間のアイソレーション劣化を改善することができ、高周波特性が向上する。   One method that meets this requirement is described in Japanese Patent No. 2755250 (Patent Document 1). As shown in the plan view of FIG. 11 and the perspective view of FIG. 12, two transistors 2 and 3 are arranged close to each other on one semiconductor chip 1 to reduce the size and the price. Further, the bonding input electrode 2b of the first stage transistor 2 and the bonding electrode 7d of the wiring substrate are connected by an input bonding wire 9d. The bonding output electrode 3c of the second-stage transistor 3 and the bonding electrode 7a of the wiring substrate 6 are connected by an output bonding wire 9a. The bonding electrode 10a on the semiconductor chip 1 and the bonding electrode 12a on the wiring substrate 6 are connected by a shielding bonding wire 13a. The shielding bonding wire 13a is provided between the input bonding wire 9d and the output bonding wire 9a, and bonding electrodes 10a and 12a at both ends thereof are via holes (Via formed in the semiconductor chip 1 and the wiring board, respectively. It is grounded at high frequency through a hole (not shown). By providing the shielding bonding wire 13a, the coupling due to the mutual inductance between the input bonding wire 9d and the output bonding wire 9a can be reduced, and the deterioration of isolation between the high frequency input / output terminals can be improved. Will improve.

入力ボンディングワイヤ９ｄと出力ボンディングワイヤ９ａとの間の相互インダクタンスによる結合の問題は、初段トランジスタ２と２段目トランジスタ３とが、入出力の位置を逆にして並置されているため、両者が近接する結果生じる。この問題は特に、初段トランジスタ２の入力ボンディングワイヤ９ｄと、２段目トランジスタ３の出力ボンディングワイヤ９ａの間で顕著である。これは初段トランジスタ２に入力される高周波信号電力に比べ、２段目トランジスタ３から出力される高周波信号電力の方が２０ｄＢ〜３０ｄＢ（１００〜１０００倍）大きく，出力から入力への正帰還が働くことによる。一方，初段トランジスタ２の出力ボンディングワイヤ９ｃと２段目トランジスタ３の入力ボンディングワイヤ９ｂも近接しているが，両者に流れる高周波信号電力の比は０ｄＢ（１倍）以下と小さく、高周波特性劣化の問題は生じない。   The problem of coupling due to mutual inductance between the input bonding wire 9d and the output bonding wire 9a is that the first-stage transistor 2 and the second-stage transistor 3 are juxtaposed with their input / output positions reversed, so that they are close to each other. Result. This problem is particularly remarkable between the input bonding wire 9d of the first-stage transistor 2 and the output bonding wire 9a of the second-stage transistor 3. This is because the high-frequency signal power output from the second-stage transistor 3 is 20 dB to 30 dB (100 to 1000 times) larger than the high-frequency signal power input to the first-stage transistor 2, and positive feedback from the output to the input works. It depends. On the other hand, the output bonding wire 9c of the first-stage transistor 2 and the input bonding wire 9b of the second-stage transistor 3 are close to each other, but the ratio of the high-frequency signal power flowing through them is as small as 0 dB (1 times) or less, and the high-frequency characteristics are degraded. There is no problem.

なお、図１１，１２において、２ａ，３ａはトランジスタの本体部分、２ｄ，３ｄはトランジスタのソース電極、２ｃは初段トランジスタ２のボンディング用出力電極、３ｂは２段目トランジスタ３のボンディング用入力電極、４は接地電極、７ｂ，７ｃ は配線基板６のボンディング用電極、８ａ〜８ｄはリード電極、１０４はキャビティである。
特許第２７５５２５０号公報 In FIGS. 11 and 12, 2a and 3a are transistor body portions, 2d and 3d are transistor source electrodes, 2c is a bonding output electrode for the first stage transistor 2, 3b is a bonding input electrode for the second stage transistor 3, 4 is a ground electrode, 7b and 7c are bonding electrodes for the wiring board 6, 8a to 8d are lead electrodes, and 104 is a cavity.
Japanese Patent No. 2755250

上記従来技術のシールド用ボンディングワイヤ１３ａの効果を図５により説明する。図５は、増幅器の入出力ボンディングワイヤ間の結合係数（相互インダクタンス（単位：ｎＨ））を、長さ１ｍｍ（実物に近い長さ）の平行した２本の入出力ボンディングワイヤのボンディング部の間隔ｄに対し、算出したものである。ここで、結合係数０．１２の個所を示す破線は、結合係数が０．１２以下のとき増幅器が安定に動作することを示す。この０．１２という値は、結合係数と増幅器の安定係数の関係を示す図６から求めた。安定係数が１以上で増幅器は安定に動作する。ここで、ボンディング部の間隔ｄは、最も近接した２つのボンディングワイヤのボンディング部の中心間の距離で定義される。   The effect of the above-described conventional shield bonding wire 13a will be described with reference to FIG. FIG. 5 shows the coupling coefficient (mutual inductance (unit: nH)) between the input / output bonding wires of the amplifier and the distance between the bonding portions of two parallel input / output bonding wires having a length of 1 mm (length close to the actual one). It is calculated for d. Here, the broken line indicating the location of the coupling coefficient of 0.12 indicates that the amplifier operates stably when the coupling coefficient is 0.12 or less. This value of 0.12 was obtained from FIG. 6 showing the relationship between the coupling coefficient and the stability coefficient of the amplifier. The amplifier operates stably with a stability factor of 1 or more. Here, the distance d between the bonding portions is defined by the distance between the centers of the bonding portions of the two closest bonding wires.

図５に示されるように、シールド用ボンディングワイヤを設けるという対策を施している上記従来技術の場合は、そうでない場合（図中、「対策なし」と表示）に比べて、結合係数が小さくなっており、高周波数特性が向上している。また、結合係数が０．１２以下のボンディング部の間隔ｄの範囲が広がり、設計の自由度が増している。さらには、ボンディング部の間隔ｄを０．５５ｍｍまで小さくすることが可能となるため、チップ面積を小さくでき、モジュールの小型化、コストの低減が可能となる。   As shown in FIG. 5, the coupling coefficient is smaller in the case of the above-described conventional technique in which measures are taken to provide a shielding bonding wire as compared with the case where this is not the case (indicated as “no countermeasure” in the figure). The high frequency characteristics are improved. Further, the range of the distance d between the bonding portions having a coupling coefficient of 0.12 or less is widened, and the degree of freedom in design is increased. Furthermore, since the distance d between the bonding portions can be reduced to 0.55 mm, the chip area can be reduced, and the module can be reduced in size and cost.

しかし、現実には、シールド用ボンディングワイヤ１３ａの両端にバイアホールによるインダクタンスが直列に加わるため、上記従来技術では充分な高周波特性の向上が得られない。   However, in reality, since inductance due to via holes is added in series to both ends of the shielding bonding wire 13a, the above-described prior art cannot sufficiently improve the high-frequency characteristics.

本発明の目的は、より高周波特性を向上させることができる高周波電力増幅器モジュールを提供することにある。   An object of the present invention is to provide a high frequency power amplifier module capable of further improving high frequency characteristics.

上記目的は、誘電体材料を基体とする配線基板上に半導体チップが設置された高周波電力増幅器モジュールにおいて、半導体チップに、２段以上の増幅段トランジスタ、これらの増幅段トランジスタへ高周波電力を入力するためのボンディング用入力電極、およびこれらの増幅段トランジスタから高周波電力を出力するためのボンディング用出力電極を設け、ある一つの増幅段トランジスタに対応するボンディング用入力電極と配線基板を接続する入力ボンディングワイヤの両端のボンディング部同士を結ぶ第１の補助線と、この一つの増幅段トランジスタの次段に位置する増幅段トランジスタに対応するボンディング用出力電極と配線基板を接続する出力ボンディングワイヤの両端のボンディング部（その中心部）同士を結ぶ第２の補助線のなす角度が、７２〜１８０゜の範囲に入るように、かつボンディング用入力電極とボンディング用出力電極のボンディング部の間隔が０．３ｍｍ以上０．８ｍｍ未満の範囲に入るように高周波電力増幅器モジュールを設計することにより達成できる。   The above-described object is to provide a high frequency power amplifier module in which a semiconductor chip is installed on a wiring substrate having a dielectric material as a base, and two or more amplification stage transistors are input to the semiconductor chip, and high frequency power is input to these amplification stage transistors. An input bonding wire for connecting a bonding input electrode corresponding to a certain amplification stage transistor and a wiring board by providing a bonding input electrode for bonding and an output electrode for bonding for outputting high frequency power from these amplification stage transistors Bonding at both ends of the output bonding wire connecting the wiring board and the first auxiliary line connecting the bonding portions at both ends of the first and the output electrodes for bonding corresponding to the amplification stage transistor located at the next stage of the one amplification stage transistor Second auxiliary line connecting parts (its central part) The high-frequency power amplifier module is arranged so that the angle formed is within the range of 72 to 180 ° and the distance between the bonding portion of the bonding input electrode and the bonding output electrode is within the range of 0.3 mm to less than 0.8 mm. This can be achieved by designing.

ここで、０．３ｍｍ以上０．８ｍｍ未満というボンディング部間隔の条件にかかわらず、上記２つの増幅段トランジスタの安定係数が１以上となるように高周波電力増幅器モジュールを設計すれば上記目的を達成できる。   Here, the above object can be achieved if the high frequency power amplifier module is designed so that the stability factor of the two amplification stage transistors is 1 or more regardless of the condition of the bonding portion interval of 0.3 mm or more and less than 0.8 mm. .

本発明によれば，高周波電力増幅器モジュールの高周波特性をより向上させることができ、これに伴い電力増幅器モジュールの小型化、またこれを用いた携帯電話端末の小型・薄型化が可能となる。   According to the present invention, the high frequency characteristics of the high frequency power amplifier module can be further improved, and accordingly, the power amplifier module can be reduced in size, and the mobile phone terminal using the same can be reduced in size and thickness.

図５に示されるように、本発明の場合は上記従来技術の場合より更に結合係数が小さくなっており、高周波数特性が向上している。また、結合係数が０．１２以下（安定係数が１以上）のボンディング部の間隔ｄの範囲も更に広がり、設計の自由度が増している。さらには、ボンディング部の間隔ｄを０．３ｍｍまで小さくすることが可能となるため、チップ面積を更に小さくでき、更なるモジュールの小型化、コストの低減が可能となる。   As shown in FIG. 5, in the case of the present invention, the coupling coefficient is further smaller than that in the case of the above prior art, and the high frequency characteristics are improved. Further, the range of the distance d between the bonding portions having a coupling coefficient of 0.12 or less (stability coefficient of 1 or more) is further expanded, and the degree of freedom in design is increased. Furthermore, since the distance d between the bonding portions can be reduced to 0.3 mm, the chip area can be further reduced, and the module can be further reduced in size and cost.

また、図５は入出力ボンディングワイヤ間のなす角度φが９０゜の場合であるが、図７に示されるように、この角度φは７２〜１８０゜の範囲にあれば良い。また、角度φが１４０゜のとき結合係数が最小になっており、極小点が存在することが分かる。   FIG. 5 shows the case where the angle φ between the input / output bonding wires is 90 °. However, as shown in FIG. 7, this angle φ may be in the range of 72 to 180 °. Further, it can be seen that when the angle φ is 140 °, the coupling coefficient is minimum and there is a minimum point.

本発明の高周波電力増幅器モジュールの具体的設計に当たっては、以上のことを踏まえて、ボンディング部間隔ｄと角度φを選ぶことになる。   In the concrete design of the high-frequency power amplifier module of the present invention, the bonding portion interval d and the angle φ are selected based on the above.

さらには、以上の説明から明らかなように、本発明は角度φを従来のように０゜にしないことがその根底にある。したがって、角度φが７２〜１８０゜の範囲にあり、入出力ボンディングワイヤに対応する２つの増幅段トランジスタの安定係数が１以上となるように高周波電力増幅器モジュールを設計しても良い。   Further, as is apparent from the above description, the present invention is based on the fact that the angle φ is not 0 ° as in the prior art. Therefore, the high frequency power amplifier module may be designed so that the angle φ is in the range of 72 to 180 ° and the stability factor of the two amplification stage transistors corresponding to the input / output bonding wires is 1 or more.

本発明の実施例１の２段電力増幅器モジュールを図１〜図４により説明する。図１は要部平面図、図２は等価回路図、図３は外観構成を示す平面図、図４は要部斜視図である。   A two-stage power amplifier module according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 is a plan view of an essential part, FIG. 2 is an equivalent circuit diagram, FIG. 3 is a plan view showing an external configuration, and FIG. 4 is a perspective view of the principal part.

図１に示されるように、初段と２段目のＭＯＳＦＥＴで構成されたトランジスタ１０２，１０３を一つのシリコンチップ１０１上に近接して形成する。初段トランジスタ１０２のゲート電極１０２ａからドレイン電極１０２ｂへの高周波信号の流れの向きと、２段目トランジスタ１０３のゲート電極１０３ａからドレイン電極１０３ｂへの高周波信号の流の向きが反対となるようにこれらのトランジスタは配置する。   As shown in FIG. 1, transistors 102 and 103 composed of first-stage and second-stage MOSFETs are formed on one silicon chip 101 in proximity to each other. The direction of the high-frequency signal flow from the gate electrode 102a to the drain electrode 102b of the first-stage transistor 102 is opposite to the direction of the high-frequency signal flow from the gate electrode 103a to the drain electrode 103b of the second-stage transistor 103. Transistors are arranged.

高周波入力端子であるゲート電極１０２ａは、１本の入力ボンディングワイヤ１０５により、配線基板１１３上の入力整合回路１２５の端部１２１に接続されている。高周波出力端子であるドレイン電極１０３ｂは、４本の出力ボンディングワイヤ１０８により、配線基板１１３上の出力整合回路１２７の端部１２４に接続されている。ゲート電極１０２ａはシリコンチップ１０１の左側の一辺に沿って配置し，ドレイン電極１０３ｂはシリコンチップ１０１の上側の一辺に沿って配置する。入力ボンディングワイヤ１０５と出力ボンディングワイヤ１０８のなす角度は約９０゜にする。ボンディングワイヤ１０６，１０７は、ドレイン電極１０２ｂ，ゲート電極１０３ａを、配線基板１１３上の段間整合回路１２６の両端部１２２および１２３に各々接続されている。初段トランジスタ１０２のゲート電極１０２ａ（ボンディング用入力電極）と２段目トランジスタ１０３のドレイン電極１０３ｂ（ボンディング用出力電極）のボンディング部の間隔ｄは約０．６ｍｍにする。   The gate electrode 102 a that is a high-frequency input terminal is connected to the end 121 of the input matching circuit 125 on the wiring board 113 by one input bonding wire 105. The drain electrode 103b, which is a high-frequency output terminal, is connected to the end 124 of the output matching circuit 127 on the wiring substrate 113 by four output bonding wires 108. The gate electrode 102a is disposed along the left side of the silicon chip 101, and the drain electrode 103b is disposed along the upper side of the silicon chip 101. The angle formed by the input bonding wire 105 and the output bonding wire 108 is about 90 °. Bonding wires 106 and 107 connect drain electrode 102b and gate electrode 103a to both ends 122 and 123 of interstage matching circuit 126 on wiring board 113, respectively. A distance d between bonding portions of the gate electrode 102a (bonding input electrode) of the first-stage transistor 102 and the drain electrode 103b (bonding output electrode) of the second-stage transistor 103 is set to about 0.6 mm.

シリコンチップ１０１は，配線基板１１３に形成されたキャビティ１０４の中に搭載する。シリコンチップ１０１の裏面には、初段トランジスタ１０２のソース電極および２段目トランジスタ１０３のソース電極として金属膜を被着し、キャビティ１０４内の配線を介して接地電位に接続する。配線基板１１３の材料としては、ガラスセラミックスやアルミナなどの誘電体基板を用いる。また、その配線には銅や銀，銀白金などを用いる。   The silicon chip 101 is mounted in the cavity 104 formed in the wiring substrate 113. On the back surface of the silicon chip 101, a metal film is deposited as a source electrode of the first-stage transistor 102 and a source electrode of the second-stage transistor 103, and connected to the ground potential via the wiring in the cavity 104. As a material for the wiring substrate 113, a dielectric substrate such as glass ceramics or alumina is used. Further, copper, silver, silver platinum or the like is used for the wiring.

図２および図３において、記号Ｐｉｎ，Ｐｏｕｔ，Ｖｇｇ，Ｖｄｄはそれぞれ高周波信号入力端子，高周波信号出力端子，ゲート電圧印加端子，ドレイン電圧印加端子であり、これらは電力増幅器モジュールの外部接続端子である。図３において、入力整合回路１２５、段間整合回路１２６および出力整合回路１２７の領域の境界を補助線で示す。また、図４にキャビティ１０４近辺の立体的様子を示す。   2 and 3, the symbols Pin, Pout, Vgg, and Vdd are a high-frequency signal input terminal, a high-frequency signal output terminal, a gate voltage application terminal, and a drain voltage application terminal, respectively, which are external connection terminals of the power amplifier module. . In FIG. 3, the boundaries of the areas of the input matching circuit 125, the interstage matching circuit 126, and the output matching circuit 127 are indicated by auxiliary lines. FIG. 4 shows a three-dimensional state near the cavity 104.

本実施例において、入力ボンディングワイヤ１０５と出力ボンディングワイヤ１０８のなす角度を約９０゜としたが、この角度は７２゜〜１８０゜の範囲で選ぶことができる。   In this embodiment, the angle formed by the input bonding wire 105 and the output bonding wire 108 is about 90 °, but this angle can be selected in the range of 72 ° to 180 °.

本発明の実施例２の３段電力増幅器モジュールを図８の要部平面図により説明する。初段，２段目，出力段のＭＯＳＦＥＴで構成されたトランジスタ１０２，１０３，１１４を一つのシリコンチップ１０１上に近接して形成する。初段トランジスタ１０２のゲート電極１０２ａからドレイン電極１０２ｂへの高周波信号の流れの向きと、２段目トランジスタ１０３のゲート電極１０３ａからドレイン電極１０３ｂへの高周波信号の流れの向きが反対となるようにこれらのトランジスタは配置する。また、出力段トランジスタ１１４を、そのゲート電極１１４ａからドレイン電極１１４ｂへの高周波信号の流れの向きが２段目トランジスタ１０３とは反対の向きとなるように配置する。   A three-stage power amplifier module according to the second embodiment of the present invention will be described with reference to a plan view of a main part of FIG. Transistors 102, 103, and 114 composed of first-stage, second-stage, and output-stage MOSFETs are formed close to one silicon chip 101. The direction of the high-frequency signal flow from the gate electrode 102a to the drain electrode 102b of the first-stage transistor 102 is opposite to the direction of the high-frequency signal flow from the gate electrode 103a to the drain electrode 103b of the second-stage transistor 103. Transistors are arranged. The output stage transistor 114 is arranged so that the direction of the flow of the high-frequency signal from the gate electrode 114 a to the drain electrode 114 b is opposite to that of the second stage transistor 103.

実施例１との違いは、初段トランジスタ１０２の入力ボンディングワイヤ１０５と２段目トランジスタ１０３の出力ボンディングワイヤ１０８とのなす角度を約１４０゜とした点、および出力段トランジスタ１１４を同一チップ上に設け、このトランジスタの出力ボンディングワイヤ１１０と２段目トランジスタ１０３の入力ボンディングワイヤ１０７とのなす角度を約９０゜、２段目トランジスタ１０３のゲート電極１０３ａ（ボンディング用入力電極）と出力段トランジスタ１１４のドレイン電極１１４ｂ（ボンディング用出力電極）のボンディング部の間隔ｄを約０．７ｍｍとし、ここにも本発明を適用した点にある。   The difference from the first embodiment is that the angle formed by the input bonding wire 105 of the first stage transistor 102 and the output bonding wire 108 of the second stage transistor 103 is about 140 °, and the output stage transistor 114 is provided on the same chip. The angle formed by the output bonding wire 110 of this transistor and the input bonding wire 107 of the second-stage transistor 103 is about 90 °, and the gate electrode 103a (bonding input electrode) of the second-stage transistor 103 and the drain of the output-stage transistor 114 The distance d between the bonding portions of the electrode 114b (bonding output electrode) is set to about 0.7 mm, and the present invention is also applied thereto.

本実施例によれば、図７に示すように、初段と２段目の入出力ボンディングワイヤ間の結合係数を最小にでき、アイソレーションをさらに改善できる。また，本発明を適用したので、２段目と出力段の入出力ボンディングワイヤ間も十分なアイソレーションを確保できる。したがって、半導体チップ面積の縮小の為に同一チップ上に３段のトランジスタを形成した本実施例の場合でも、これらトランジスタ間の距離が短くなるにもかかわらず、高周波特性を改善できる。   According to the present embodiment, as shown in FIG. 7, the coupling coefficient between the first and second input / output bonding wires can be minimized, and the isolation can be further improved. In addition, since the present invention is applied, sufficient isolation can be secured between the input / output bonding wires in the second stage and the output stage. Therefore, even in the case of the present embodiment in which three stages of transistors are formed on the same chip in order to reduce the area of the semiconductor chip, the high frequency characteristics can be improved in spite of a decrease in the distance between these transistors.

本発明の実施例３の３段電力増幅器モジュールを図９の要部平面図により説明する。実施例２との違いは、２段目トランジスタ１０３と出力段トランジスタ１１４との間に、従来技術であるシールド技術を応用して、シールド用ボンディングワイヤ２０１とシールド配線２０４を設け、これらの両端を配線基板上の電極２０２およびバイアホール２０３を介して接地電位に接続した点にある。   A three-stage power amplifier module according to Embodiment 3 of the present invention will be described with reference to a plan view of the main part of FIG. The difference from the second embodiment is that a shield bonding wire 201 and a shield wiring 204 are provided between the second-stage transistor 103 and the output-stage transistor 114 by applying a shield technique as a conventional technique. It is in the point connected to the ground potential through the electrode 202 and the via hole 203 on the wiring board.

本実施例では、初段と２段目の間に従来技術であるシールド技術を適用したが、これらのトランジスタ領域は元々面積が広く、高周波特性を改善できる。   In this embodiment, the shield technique which is a conventional technique is applied between the first stage and the second stage. However, these transistor regions originally have a wide area and can improve high frequency characteristics.

本発明の実施例４の２段電力増幅器モジュールを図１０の要部平面図により説明する。   A two-stage power amplifier module according to Embodiment 4 of the present invention will be described with reference to a plan view of the main part of FIG.

実施例１との違いは、初段トランジスタ１０２自体の方向を９０゜回転した点にある。   The difference from the first embodiment is that the direction of the first stage transistor 102 itself is rotated by 90 °.

本実施例は、初段と２段目との入出力ボンディングワイヤのボンディング部の位置をチップの辺の中央部に移動できるので、ボンディング部間隔をさらに広げることが可能となり（実施例１で０．６ｍｍだったものが０．７５ｍｍになる）、入出力間のアイソレーションをさらに改善できる。   In this embodiment, since the positions of the bonding portions of the input / output bonding wires in the first stage and the second stage can be moved to the center portion of the chip side, it is possible to further widen the bonding portion interval (0. The isolation between input and output can be further improved.

以上、本発明を実施例を基に説明したが、本発明は上記実施例に限定されるものではなく、トランジスタの電極数，ボンディングワイヤの本数等はその主旨を逸脱しない範囲において種々変更可能である。   The present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and the number of electrodes of transistors, the number of bonding wires, and the like can be variously changed without departing from the gist thereof. is there.

また、トランジスタはＭＯＳＦＥＴに限らず他の電界効果トランジスタ、ヘテロ接合バイポーラトランジスタ（ＨＢＴ）等のトランジスタを用いても良い。   Further, the transistor is not limited to the MOSFET, and other field effect transistors, heterojunction bipolar transistors (HBT), or other transistors may be used.

本発明の実施例１の２段電力増幅器モジュールの要部平面図である。It is a principal part top view of the two-stage power amplifier module of Example 1 of this invention. 本発明の実施例１の２段電力増幅器モジュールの等価回路図である。1 is an equivalent circuit diagram of a two-stage power amplifier module according to Embodiment 1 of the present invention. 本発明の実施例１の２段電力増幅器モジュールの外観構成を示す平面図である。It is a top view which shows the external appearance structure of the two-stage power amplifier module of Example 1 of this invention. 本発明の実施例１の２段電力増幅器モジュールの要部斜視図である。It is a principal part perspective view of the two-stage power amplifier module of Example 1 of this invention. 本発明および従来技術の入出力ボンディングワイヤ間の結合係数とボンディング部間隔の関係を示す図である。It is a figure which shows the relationship between the coupling coefficient between the input-output bonding wires of this invention and a prior art, and a bonding part space | interval. 入出力ボンディングワイヤ間の結合係数と増幅器の安定係数の関係を示す図である。It is a figure which shows the relationship between the coupling coefficient between input-output bonding wires, and the stability coefficient of an amplifier. 本発明の入出力ボンディングワイヤ間の結合係数と角度の関係を示す図である。It is a figure which shows the relationship between the coupling coefficient between the input-output bonding wires of this invention, and an angle. 本発明の実施例２の３段電力増幅器モジュールの要部平面図である。It is a principal part top view of the 3 step | paragraph power amplifier module of Example 2 of this invention. 本発明の実施例３の３段電力増幅器モジュールの要部平面図である。It is a principal part top view of the 3 step | paragraph power amplifier module of Example 3 of this invention. 本発明の実施例４の２段電力増幅器モジュールの要部平面図である。It is a principal part top view of the two-stage power amplifier module of Example 4 of this invention. 従来技術の２段電力増幅器モジュールの平面図である。It is a top view of the two-stage power amplifier module of a prior art. 従来技術の２段電力増幅器モジュールの斜視図である。1 is a perspective view of a conventional two-stage power amplifier module. FIG.

符号の説明Explanation of symbols

１…半導体チップ，２…初段トランジスタ，２ａ…トランジスタの本体部分，２ｂ…ボンディング用入力電極，２ｃ…ボンディング用出力電極，２ｄ…ソース電極，３…２段目トランジスタ，３ａ…トランジスタの本体部分，３ｂ…ボンディング用入力電極，３ｃ…ボンディング用出力電極，３ｄ…ソース電極，４…接地電極，６…配線基板，７ａ〜７ｄ…配線基板６のボンディング用電極 ，８ａ〜８ｄ…リード電極，９ａ…出力ボンディングワイヤ，９ｂ…入力ボンディングワイヤ，９ｃ…出力ボンディングワイヤ，９ｄ…入力ボンディングワイヤ，１０ａ，１０ｂ…ボンディング用電極，１２ａ，１２ｂ…ボンディング用電極，１３ａ，１３ｂ…シールド用ボンディングワイヤ，１０１…シリコンチップ，１０２…初段トランジスタ，１０２ａ…ゲート電極（入力電極），１０２ｂ…ドレイン電極（出力電極），１０３…２段目トランジスタ，１０３ａ…ゲート電極（入力電極），１０３ｂ…ドレイン電極（出力電極），１０４…キャビティ，１０５…入力ボンディングワイヤ，１０６…出力ボンディングワイヤ，１０７…入力ボンディングワイヤ，１０８…出力ボンディングワイヤ，１０９…入力ボンディングワイヤ，１１０…出力ボンディングワイヤ，１１３…配線基板，１１４…出力段トランジスタ，１１４ａ…ゲート電極（入力電極），１１４ｂ…ドレイン電極（出力電極），１２１…入力整合回路の端部，１２２…段間整合回路の端部，１２３…段間整合回路の端部，１２４…出力整合回路の端部，１２５…入力整合回路，１２６…段間整合回路，１２７…出力整合回路，Ｐｉｎ…高周波信号入力端子，Ｐｏｕｔ…高周波信号出力端子，Ｖｇｇ…ゲート電圧印加端子，Ｖｄｄ…ドレイン電圧印加端子，２０１…シールド用ボンディングワイヤ，２０２…電極，２０３…バイアホール，２０４…シールド配線。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... First stage transistor, 2a ... Transistor main part, 2b ... Bonding input electrode, 2c ... Bonding output electrode, 2d ... Source electrode, 3 ... Second stage transistor, 3a ... Transistor main part, 3b: Bonding input electrode, 3c: Bonding output electrode, 3d: Source electrode, 4 ... Ground electrode, 6 ... Wiring substrate, 7a-7d ... Bonding electrode of wiring substrate 6, 8a-8d ... Lead electrode, 9a ... Output bonding wire, 9b ... Input bonding wire, 9c ... Output bonding wire, 9d ... Input bonding wire, 10a, 10b ... Bonding electrode, 12a, 12b ... Bonding electrode, 13a, 13b ... Shielding bonding wire, 101 ... Silicon Chip 102, first stage transistor, 1 02a ... Gate electrode (input electrode), 102b ... Drain electrode (output electrode), 103 ... Second stage transistor, 103a ... Gate electrode (input electrode), 103b ... Drain electrode (output electrode), 104 ... Cavity, 105 ... Input Bonding wire 106 ... Output bonding wire 107 ... Input bonding wire 108 ... Output bonding wire 109 ... Input bonding wire 110 ... Output bonding wire 113 ... Wiring substrate 114 ... Output stage transistor 114a ... Gate electrode (input) Electrode), 114b ... drain electrode (output electrode), 121 ... end of input matching circuit, 122 ... end of interstage matching circuit, 123 ... end of interstage matching circuit, 124 ... end of output matching circuit, 125 ... Input matching circuit, 126 ... Interstage matching circuit, 127 ... Output matching Path, Pin ... high frequency signal input terminal, Pout ... high frequency signal output terminal, Vgg ... gate voltage application terminal, Vdd ... drain voltage application terminal, 201 ... shield bonding wire, 202 ... electrode, 203 ... via hole, 204 ... shield wiring .

Claims (10)

基板と、
前記基板の１つの面に配置される第１および第２の電極と、
入力端子および出力端子を有する第１ないし第３のトランジスタと、
前記第１の電極と前記第２のトランジスタの前記入力端子とを電気的に接続する第１の接続導体と、
前記第２の電極と前記第３のトランジスタの前記出力端子とを電気的に接続する第２の接続導体と
を具備して成り、
前記第１の接続導体が延在する方向と前記第２の接続導体が延在する方向との成す角は、前記基板の前記１つの面を平面図として見た場合に７２〜１８０度の範囲内であり、
前記第２のトランジスタの前記入力端子と前記第３のトランジスタの前記出力端子とのボンディング部間の距離は０．３ｍｍ以上である
ことを特徴とする高周波電力増幅器モジュール。 A substrate,
First and second electrodes disposed on one surface of the substrate;
First to third transistors having an input terminal and an output terminal;
A first connection conductor that electrically connects the first electrode and the input terminal of the second transistor;
A second connection conductor for electrically connecting the second electrode and the output terminal of the third transistor;
The angle formed between the direction in which the first connection conductor extends and the direction in which the second connection conductor extends is in a range of 72 to 180 degrees when the one surface of the substrate is viewed as a plan view. Within
A high-frequency power amplifier module, wherein a distance between bonding portions of the input terminal of the second transistor and the output terminal of the third transistor is 0.3 mm or more. 請求項１において、
前記基板の前記１つの面に配置される第３および第４の電極と、
前記第３の電極と前記第１のトランジスタの前記入力端子とを電気的に接続する第３の接続導体と、
前記第４の電極と前記第２のトランジスタの前記出力端子とを電気的に接続する第４の接続導体と
を更に具備して成り、
前記第３の接続導体は、前記第３の接続導体と半導体チップの第２の辺に対向する第３の辺とが互いに交差するように、前記第１のトランジスタの前記入力端子から前記第３の電極まで延在し、
前記第４の接続導体は、前記第４の接続導体と前記半導体チップの第１の辺に対向する第４の辺とが互いに交差するように、前記第２のトランジスタの前記出力端子から前記第４の電極まで延在する
ことを特徴とする高周波電力増幅器モジュール。 In claim 1,
Third and fourth electrodes disposed on the one surface of the substrate;
A third connection conductor for electrically connecting the third electrode and the input terminal of the first transistor;
A fourth connection conductor for electrically connecting the fourth electrode and the output terminal of the second transistor;
The third connection conductor extends from the input terminal of the first transistor so that the third connection conductor and a third side opposite to the second side of the semiconductor chip intersect each other. Extending to the electrodes
The fourth connection conductor extends from the output terminal of the second transistor so that the fourth connection conductor and a fourth side opposite to the first side of the semiconductor chip intersect each other. A high-frequency power amplifier module, which extends to four electrodes. 請求項２において、
前記半導体チップは、前記第２のトランジスタの前記入力端子と前記第１の電極とが対向し、前記第３のトランジスタの前記出力端子と前記第２の電極とが対向し、前記第１のトランジスタの前記入力端子と前記第３の電極とが対向し、前記第２のトランジスタの前記出力端子と前記第４の電極とが対向するように配置される
ことを特徴とする高周波電力増幅器モジュール。 In claim 2,
In the semiconductor chip, the input terminal of the second transistor faces the first electrode, the output terminal of the third transistor faces the second electrode, and the first transistor A high-frequency power amplifier module, wherein the input terminal of the second transistor and the third electrode are opposed to each other, and the output terminal of the second transistor and the fourth electrode are opposed to each other. 請求項３において、
前記半導体チップは、前記基板の前記１つの面に設けられたキャビティ内に配置される
ことを特徴とする高周波電力増幅器モジュール。 In claim 3,
The high-frequency power amplifier module, wherein the semiconductor chip is disposed in a cavity provided on the one surface of the substrate. 請求項１ないし４のいずれかにおいて、
前記第１のトランジスタの前記入力端子に入力された信号を電圧増幅し、前記第３のトランジスタの前記出力端子から、電圧増幅された前記信号を出力する
ことを特徴とする高周波電力増幅器モジュール。 In any of claims 1 to 4,
A high-frequency power amplifier module, wherein the signal input to the input terminal of the first transistor is voltage-amplified, and the voltage-amplified signal is output from the output terminal of the third transistor. 請求項１ないし４のいずれかにおいて、
前記第１のトランジスタの前記出力端子と前記第２のトランジスタの前記入力端子とは第１の整合回路を介して互いに接続され、
前記第２のトランジスタの前記出力端子と前記第３のトランジスタの前記入力端子とは第２の整合回路を介して互いに接続されている
ことを特徴とする高周波電力増幅器モジュール。 In any of claims 1 to 4,
The output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a first matching circuit;
The high-frequency power amplifier module, wherein the output terminal of the second transistor and the input terminal of the third transistor are connected to each other via a second matching circuit. 請求項６において、
前記第１および第２の整合回路は、前記基板の前記１つの面上に形成されている
ことを特徴とする高周波電力増幅器モジュール。 In claim 6,
The high frequency power amplifier module according to claim 1, wherein the first and second matching circuits are formed on the one surface of the substrate. 請求項１ないし４のいずれかにおいて、
前記第１ないし前記第３のトランジスタの各々は、ゲート、ソース、およびドレインを有する電界効果トランジスタを含んで成り、
前記第１のトランジスタの前記入力端子は、前記第１のトランジスタの前記電界効果トランジスタの前記ゲートであり、
前記第２のトランジスタの前記出力端子は、前記第２のトランジスタの前記電界効果トランジスタの前記ドレインであり、
前記第２のトランジスタの前記入力端子は、前記第２のトランジスタの前記電界効果トランジスタの前記ゲートであり、
前記第３のトランジスタの前記出力端子は、前記第３のトランジスタの前記電界効果トランジスタの前記ドレインである
ことを特徴とする高周波電力増幅器モジュール。 In any of claims 1 to 4,
Each of the first to third transistors comprises a field effect transistor having a gate, a source, and a drain;
The input terminal of the first transistor is the gate of the field effect transistor of the first transistor;
The output terminal of the second transistor is the drain of the field effect transistor of the second transistor;
The input terminal of the second transistor is the gate of the field effect transistor of the second transistor;
The high-frequency power amplifier module according to claim 3, wherein the output terminal of the third transistor is the drain of the field effect transistor of the third transistor. 請求項１ないし４のいずれかにおいて、
前記第１ないし前記第３のトランジスタの各々は、バイポーラトランジスタを含んで成る
ことを特徴とする高周波電力増幅器モジュール。 In any of claims 1 to 4,
Each of the first to third transistors includes a bipolar transistor. 請求項１ないし４のいずれかにおいて、
前記第２および前記第３のトランジスタの安定係数はそれぞれ１以上である
ことを特徴とする高周波電力増幅器モジュール。 In any of claims 1 to 4,
The high-frequency power amplifier module according to claim 1, wherein stability coefficients of the second and third transistors are each 1 or more.
JP2008136687A 2008-05-26 2008-05-26 High-frequency power amplifier module Pending JP2008228347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008136687A JP2008228347A (en) 2008-05-26 2008-05-26 High-frequency power amplifier module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008136687A JP2008228347A (en) 2008-05-26 2008-05-26 High-frequency power amplifier module

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2004150427A Division JP4153898B2 (en) 2004-05-20 2004-05-20 RF power amplifier module

Publications (1)

Publication Number Publication Date
JP2008228347A true JP2008228347A (en) 2008-09-25

Family

ID=39846321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008136687A Pending JP2008228347A (en) 2008-05-26 2008-05-26 High-frequency power amplifier module

Country Status (1)

Country Link
JP (1) JP2008228347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015139207A (en) * 2014-01-24 2015-07-30 住友電工デバイス・イノベーション株式会社 Amplification device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0219008A (en) * 1988-07-07 1990-01-23 Mitsubishi Electric Corp Microwave transistor
JPH02290308A (en) * 1989-02-17 1990-11-30 Toshiba Corp Oscillator
JPH04177903A (en) * 1990-11-09 1992-06-25 Nec Corp Monolithic ic for microwave power amplification
JPH07321130A (en) * 1994-05-24 1995-12-08 Japan Energy Corp Semiconductor device
JPH0927507A (en) * 1995-07-07 1997-01-28 Hitachi Ltd Semiconductor device
JPH09260412A (en) * 1996-03-22 1997-10-03 Nec Corp Semiconductor integrated circuit
JPH09326610A (en) * 1996-06-06 1997-12-16 Mitsubishi Electric Corp Microwave integrated circuit
JPH104325A (en) * 1996-06-17 1998-01-06 Matsushita Electric Ind Co Ltd High frequency amplifier, high frequency communication equipment, active semiconductor device, impedance matching device and lead frame

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0219008A (en) * 1988-07-07 1990-01-23 Mitsubishi Electric Corp Microwave transistor
JPH02290308A (en) * 1989-02-17 1990-11-30 Toshiba Corp Oscillator
JPH04177903A (en) * 1990-11-09 1992-06-25 Nec Corp Monolithic ic for microwave power amplification
JPH07321130A (en) * 1994-05-24 1995-12-08 Japan Energy Corp Semiconductor device
JPH0927507A (en) * 1995-07-07 1997-01-28 Hitachi Ltd Semiconductor device
JPH09260412A (en) * 1996-03-22 1997-10-03 Nec Corp Semiconductor integrated circuit
JPH09326610A (en) * 1996-06-06 1997-12-16 Mitsubishi Electric Corp Microwave integrated circuit
JPH104325A (en) * 1996-06-17 1998-01-06 Matsushita Electric Ind Co Ltd High frequency amplifier, high frequency communication equipment, active semiconductor device, impedance matching device and lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015139207A (en) * 2014-01-24 2015-07-30 住友電工デバイス・イノベーション株式会社 Amplification device

Similar Documents

Publication Publication Date Title
US6489680B2 (en) Semiconductor device
EP3337037B1 (en) Doherty amplifiers and amplifier modules with shunt inductance circuits that affect transmission line length between carrier and peaking amplifier outputs
US8295057B2 (en) Semiconductor device
US7952434B2 (en) Semiconductor device
JP5589428B2 (en) Transmission line, impedance converter, integrated circuit mounting device and communication device module
CN210246699U (en) Power amplifying module
JP2001094009A (en) Semiconductor device
JP5812158B2 (en) Transmission line, impedance converter, integrated circuit mounting device and communication device module
JP6265415B2 (en) Amplifier
JP4153898B2 (en) RF power amplifier module
JP2008228347A (en) High-frequency power amplifier module
JP2755250B2 (en) Semiconductor integrated circuit
JP3667136B2 (en) RF power amplifier module
JP2006086329A (en) Power amplifier module
KR101560522B1 (en) Electric apparatus having high frequency grounding structure and power amplifier
JPH11204728A (en) High frequency semiconductor device
JPWO2005093948A1 (en) amplifier
JP2005051062A (en) Semiconductor device
KR100562349B1 (en) Semiconductor device
JP4425755B2 (en) Differential amplifier circuit
JP2005295193A (en) Power amplifier
JP4918652B2 (en) Semiconductor device
JP2007074000A (en) Semiconductor device
JP2005064747A (en) High frequency amplifier
JP2007074001A (en) Semiconductor device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100528

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110524

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111011