JP4425755B2 - Differential amplifier circuit - Google Patents

Description

  The present invention relates to a high-frequency semiconductor integrated circuit used for satellite communication, terrestrial microwave communication, mobile communication, and the like, and more particularly to a differential amplifier circuit used for a high-frequency semiconductor integrated circuit.

  In general, in a semiconductor integrated circuit operating at a high frequency, in order to suppress a decrease in gain of an amplifying element due to an inductor component of an element such as a wire that connects a ground electrode and a ground plane of the amplifying element constituting the circuit. In some cases, a differential amplifier circuit configuration is used (see Non-Patent Document 1, for example).

  According to the above-described conventional differential amplifier circuit, a differential operation can be performed without losing balance by creating a symmetrical layout up to a point where a pair of transistors constituting the differential amplifier circuit are connected to each other. Is possible. As a result, it is possible to suppress the effect of a gain decrease due to an inductor component such as a wire attached to the emitter electrode, and a high gain can be realized.

2004 IEEE Radio Frequency Integrated Circuits Symposium "A Variable Gain Image-Reject Down-converter for 5-6 GHz WLAN Applications" p150, Fig. 3

  However, in the above-described conventional example, the line width from the emitter electrode to the point where they are connected to each other via the inductor is equal to the line width of the routing line from the connection point to the power source, and therefore, the line before connection and the connection after connection are routed. When the lines are likely to be coupled and the line before one connection and the line after the connection are coupled, the electrical lengths of the lines are different. As a result, there arises a problem that the differential balance is lost and the gain is lowered.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a differential amplifier circuit capable of realizing balanced differential operation by suppressing coupling between lines. .

A differential amplifier circuit according to the present invention includes a pair of transistors that amplify and output a difference between input voltages, and a collector or base terminal of each transistor is connected using at least a line, and a power supply terminal after being connected In a differential amplifier circuit that is connected up to at least using another line, the line width of the line until the collector or base terminal of each transistor is connected, the other line to the power supply terminal after being connected The line until the collector or base terminal of each transistor is connected is formed on at least the uppermost layer of the multilayer substrate, and the other lines up to the power supply terminal after being connected are formed on the multilayer substrate. It was formed in the lower layer of .

  According to this invention, the line width of the line until the collector or base terminal of each transistor is connected is made thicker than the line width of the other line up to the power supply terminal after being connected, Coupling is suppressed and a balanced differential operation can be realized.

Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a differential amplifier circuit according to Embodiment 1 of the present invention. The differential amplifier circuit shown in FIG. 1 includes a pair of npn transistors 53 and 54 that amplify the difference between input voltages input from the high-frequency differential input terminals 51 and 52 and output from the high-frequency differential output terminals 55 and 56. A power source 60 is connected to base electrodes of the pair of npn transistors 53 and 54 via base bias application resistors 57 and 58, and a virtual ground point 59 to which the base bias application resistors 57 and 58 are connected is a capacitor. The base bias circuit is configured by being grounded through 66.

The emitter electrodes of the pair of npn transistors 53 and 54 are grounded through a ground wire 65.
Further, high frequency differential output terminals 55 and 56 are connected to collector electrodes of the pair of npn transistors 53 and 54 via collector bias applying inductors 61 and 62, respectively, and a virtual ground point 63 of the collector bias applying inductors 61 and 62. Is connected to a power source 64 and grounded via a capacitor 67 to constitute a collector bias circuit.

  Next, the operation will be described. In FIG. 1, a high frequency differential signal is input to high frequency differential input terminals 51 and 52, amplified by npn transistors 53 and 54, and then output from high frequency output terminals 55 and 56. The base bias circuit includes application resistors 57 and 58, a capacitor 66, and a power supply 60. Since the pair of transistors operate in opposite phases, the signals cancel each other at the virtual ground point 59 and are grounded at a high frequency. The collector bias circuit includes application inductors 61 and 62, a capacitor 67 and a power source 64. Similarly, since the pair of transistors operate in opposite phases, the signals cancel each other at the virtual ground point 63 and are grounded at a high frequency.

  FIG. 2 is a diagram schematically showing the layout of the collector bias circuit section shown in FIG. 1, and the line width represents the line width. As shown in FIG. 2, the width of the line from the collector electrodes 71 and 72 of the pair of npn transistors 53 and 54 to the virtual ground point 63 connected to each other via the collector bias applying inductors 61 and 62 is The line width of the power supply line 68 from the virtual ground point 63 to the power supply 64 is larger than the line width, and the line width is twice or more. For this reason, the amount of coupling between the lines before being connected to each other and the line after being connected is small, and the amount of change in the electrical length of the lines due to the coupling is small.

  Further, by reducing the line width, the impedance of the line increases. Therefore, for example, when the bias applying inductors 61 and 62 are used as output matching circuit elements, it is not necessary to consider the impedance of the bias circuit.

  Similarly, FIG. 3 is a diagram schematically showing the layout of the collector bias circuit section shown in FIG. 1, and the line width represents the line width. As shown in FIG. 3, the width of the line from the base electrodes 81 and 82 of the pair of npn transistors 53 and 54 to the virtual ground point 59 connected to each other via the base bias applying resistors 57 and 58 is The line width of the power supply line 69 from the virtual ground point 59 to the power supply 60 is larger than the line width, and the line width is twice or more. For this reason, the amount of coupling between the lines before being connected to each other and the line after being connected is small, and the amount of change in the electrical length of the lines due to the coupling is small.

  Further, by reducing the line width, the impedance of the line increases. Therefore, for example, when the bias application resistors 57 and 58 are used as input matching circuit elements, it is not necessary to consider the impedance of the bias circuit.

  FIG. 4 is a circuit schematic diagram relating to the coupling of the transmission lines in section A in FIG. Here, the connected line, that is, the power supply line 68 from the virtual ground point 63 to the power source 64 is connected to the port 1 and the lines before connection, that is, the collector electrodes 71 and 72 to each other via the bias applying inductors 61 and 62. Assuming that the line to the virtual ground point 63 is port 2 and port 3, the line width of the line before connection is 10 μm, the line width after connection is 10 μm, and the line interval between port 1 and port 3 is 10 μm. Yes.

  5 and 6 show the electromagnetic field calculation results of the configuration shown in FIG. 4, FIG. 5 shows the pass loss calculation results, and FIG. 6 shows the pass phase calculation results. As shown in FIG. 5, for example, the value m1 indicating the passing loss dBS (31) between the port 1 and the port 3 at 6 GHz is smaller than the value m2 indicating the passing loss dBS (21) between the port 1 and the port 2. The lines are connected and the electrical length looks short. Further, as shown in FIG. 6, for example, a value m3 indicating the passing phase phase (31) between the port 1 and the port 3 at 6 GHz is greater than a value m4 indicating the passing phase phase (21) between the port 1 and the port 2. The phase difference is small, the lines are coupled, and the electrical length appears short. Thus, it can be seen from the calculation result that the line is coupled between the port 1 and the port 3 and the electric length of the line appears to be short.

  The line spacing between port 1 and port 3 is desired to be wide, but is limited in a limited space. From the results shown in FIG. 5 and FIG. 6, in order to reduce the coupling amount between the line before connection and the line after connection, the line after connection, that is, the power supply line 68 from the virtual ground point 63 to the power source 64, The line before connection, that is, the line from the collector electrodes 71 and 72 to the virtual ground point 63 connected to each other via the bias applying inductors 61 and 62 may be narrower, in other words, the line of the line before connection. It is only necessary to make the width thicker than the line after connection. The space between the port 1 and port 3 is widened in a limited space, and the amount of coupling between the line before connection and the line after connection becomes small. The amount of change in the electrical length of the line can be reduced, and the effect becomes significant by setting the line width of the line before connection to be twice or more that of the line after connection. 5 and 6 describe the collector bias circuit unit, the same applies to the base bias circuit unit.

  As described above, according to the first embodiment, by making the line width to the virtual ground point generated in the collector bias line or the base bias line thicker than the line width after grounding, the coupling between the lines is suppressed, and the line due to the coupling Therefore, a balanced differential operation can be performed.

  Furthermore, by narrowing the width of the line after connection, it becomes a high impedance line, and when the matching circuit is configured including the bias application element, it is not necessary to consider the impedance of the bias circuit. Accuracy can be increased.

  The amplifying elements constituting the differential amplifier circuit are not limited to npn transistors, and the bias applying elements are not limited to resistors and inductors.

Embodiment 2. FIG.
In the second embodiment, a laminated structure of a multilayer substrate of a differential amplifier circuit having the same circuit configuration as that of the differential amplifier circuit shown in FIG. 1 and used in a high-frequency semiconductor integrated circuit will be described. 7 is a diagram schematically showing the layout of the collector bias circuit section shown in FIG. 1, and FIG. 8 is a diagram schematically showing the cross-sectional structure taken along the line AB of FIG. In FIG. 7, a solid line represents a line including the uppermost layer, and a hatched line represents a lower layer line.

  The differential amplifier circuit according to the second embodiment of the present invention has the same circuit configuration as the differential amplifier circuit shown in FIG. 1, and a pair of npn transistors 53 and 54 as shown in FIGS. A line extending from the collector electrodes 71 and 72 to the virtual ground point 63 connected to each other via the collector bias applying inductors 61 and 62 is formed as the uppermost layer wiring 125 of the multilayer substrate. Up to the power supply line 68 is formed as the lower layer wiring 124. In FIG. 8, 121 denotes a substrate, 122 denotes a dielectric layer, and 123 denotes a passivation layer.

  For this reason, the distance between the line before connection and the line after connection is smaller than when using the lines on the same layer, so the amount of coupling is small.

  In general, the line width of the lower layer can be made smaller than that of the upper layer. Therefore, the line width can be further reduced by using the lower line.

  9 is a diagram schematically showing the layout of the base bias circuit section shown in FIG. 1, and FIG. 10 is a diagram schematically showing the cross-sectional structure taken along the line A′-B ′ of FIG. is there. In FIG. 9, the solid line represents the line including the uppermost layer, and the oblique line represents the lower layer line.

  As shown in FIGS. 9 and 10, a line from the base electrodes 81 and 82 of the pair of npn transistors 53 and 54 to the virtual ground point 59 connected to each other via the base bias applying resistors 57 and 58 is connected to the multilayer substrate. The uppermost layer wiring 135 is formed, and the power supply routing line 69 from the connected virtual ground point 59 to the power source 60 is formed as the lower layer wiring 134. In FIG. 10, 121 denotes a substrate, 122 denotes a dielectric layer, and 123 denotes a passivation layer.

  For this reason, the distance between the line before connection and the line after connection is smaller than when using the lines on the same layer, so the amount of coupling is small.

  In general, the line width of the lower layer can be made smaller than that of the upper layer. Therefore, the line width can be further reduced by using the lower line.

  Therefore, according to the second embodiment, the line up to the virtual ground point generated in the collector bias line or the base bias line is a line including the uppermost layer, and the line width after grounding is configured by the lower layer line so that they are connected to each other. Since the distance between the line before the connection and the line after the connection is reduced, the amount of coupling can be reduced, and a stable differential operation can be realized.

  In addition, by configuring the line after the virtual ground point in the lower layer, it becomes possible to realize a narrower line than allowed by the uppermost line, so that the coupling between the lines can be further suppressed. It becomes.

  Furthermore, by configuring the line after the virtual ground point as a lower layer, it becomes possible to realize a line having a narrower width than allowed by the uppermost layer line, and thus it is possible to realize downsizing.

1 is a circuit diagram showing a configuration of a differential amplifier circuit according to a first embodiment of the present invention. It is the figure which showed typically the layout of the collector bias circuit part shown in FIG. It is the figure which showed typically the layout of the collector bias circuit part shown in FIG. It is a circuit schematic diagram regarding the coupling | bonding of the transmission line of the A section in FIG. It is a figure which shows the passage loss calculation result of the structure shown in FIG. It is a figure which shows the passage phase calculation result of the structure shown in FIG. FIG. 6 is a diagram illustrating a stacked structure of a differential amplifier circuit according to a second embodiment of the present invention, and schematically showing a layout of a collector bias circuit unit shown in FIG. 1. FIG. 8 is a diagram for explaining a laminated structure of a differential amplifier circuit according to a second embodiment of the present invention, and schematically shows a cross-sectional structure taken along line AB in FIG. 7. FIG. 6 is a diagram for explaining a laminated structure of a differential amplifier circuit according to a second embodiment of the present invention, and schematically shows a layout of a base bias circuit unit shown in FIG. 1. FIG. 10 is a diagram for explaining a stacked structure of a differential amplifier circuit according to a second embodiment of the present invention, and schematically shows a cross-sectional structure taken along line A′-B ′ of FIG. 9.

Explanation of symbols

  51, 52 High frequency differential input terminal, 53, 54 A pair of npn transistors, 55, 56 High frequency differential output terminal, 57, 58 Base bias application resistance, 59 Virtual ground point, 60 Power supply, 61, 62 Collector bias application inductor , 63 Virtual ground point, 64 power source, 65 ground wire, 66, 67 capacitor, 68 power supply line for collector bias circuit section, 69 power supply line for base bias circuit section, 71, 72 collector electrode, 81, 82 base electrode, 124,134 Lower layer wiring, 125,135 Top layer wiring.

Claims (1)

It has a pair of transistors that amplify and output the difference in input voltage, and the collector or base terminal of each transistor is connected using at least a line, and the connected power supply terminal is connected using at least another line. In the differential amplifier circuit,
While making the line width of the line until the collector or base terminal of each transistor is connected larger than the line width of the other lines to the power supply terminal after being connected ,
A line until the collector or base terminal of each transistor is connected is formed in at least the uppermost layer of the multilayer substrate, and another line to the power supply terminal after being connected is formed in the lower layer of the multilayer substrate. Differential amplifier circuit.

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