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JP2007074001A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007074001A
JP2007074001A JP2006339318A JP2006339318A JP2007074001A JP 2007074001 A JP2007074001 A JP 2007074001A JP 2006339318 A JP2006339318 A JP 2006339318A JP 2006339318 A JP2006339318 A JP 2006339318A JP 2007074001 A JP2007074001 A JP 2007074001A
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Prior art keywords
electrode
semiconductor chip
substrate
wire
region
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JP2006339318A
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Inventor
Iwamichi Kamishiro
岩道 神代
Sakae Kikuchi
栄 菊池
Yasuhiro Nunokawa
康弘 布川
Shizuo Kondo
静雄 近藤
Tetsuaki Adachi
徹朗 安達
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Priority to JP2006339318A priority Critical patent/JP2007074001A/en
Publication of JP2007074001A publication Critical patent/JP2007074001A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be miniaturized. <P>SOLUTION: In the semiconductor device, a semiconductor chip 5 in which a plurality of amplification means are formed is mounted at one main surface of a wiring board 1, and the electrode of the semiconductor chip is electrically connected to that of the wiring board with a wire. In the semiconductor device, an electrode 2C for bonding at a substrate side to which a wire 7C fixed to reference potential is connected, is arranged at a position far remote from one side 5X of the semiconductor chip 5, as compared with an electrode 2B for outputting at the substrate side to which a wire 7B for outputting is connected. An electrode 2A for inputting at the substrate side to which a wire 7A for inputting is connected, is arranged at a position where distance from one side 5X of the semiconductor chip 5 becomes nearly identical to that of the electrode 2B for outputting at the substrate side, or at a position far remote from one side 5X of the semiconductor chip 5 as compared with the electrode 2C for bonding at the substrate side. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、多段式増幅回路構成の半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a multistage amplifier circuit configuration.

半導体装置として、ＰＤＣ（Ｐersonal Ｄigital Ｃellular）方式の自動車電話及び携帯電話、或いはＰＨＳ（Ｐersonal Ｈandyphone Ｓystem)方式の携帯電話等の携帯通信機器に組み込まれる高周波電力増幅器(高周波パワーモジュール)がある。この高周波電力増幅器は、複数の増幅手段を多段に接続した多段式増幅回路構成になっている。   As a semiconductor device, there is a high frequency power amplifier (high frequency power module) incorporated in a mobile communication device such as a PDC (Personal Digital Cellular) type mobile phone and a mobile phone, or a PHS (Personal Handyphone System) type mobile phone. This high-frequency power amplifier has a multistage amplifier circuit configuration in which a plurality of amplification means are connected in multiple stages.

前記高周波電力増幅器は、一主面に増幅手段が形成された半導体チップを配線基板の一主面側に搭載し、半導体チップの一主面に形成された電極と配線基板の一主面に形成された電極とを導電性のワイヤで電気的に接続している。増幅手段は、例えば複数の電界効果トランジスタの夫々を電気的に並列に接続した構成になっており、増幅手段のゲート端子(入力部)は半導体チップの一主面に形成されたチップ側入力用電極と電気的に接続され、増幅手段のドレイン端子(出力部)は半導体チップの一主面に形成されたチップ側出力用電極と電気的に接続されている。チップ側入力用電極は半導体チップの一辺側に配置され、チップ側出力用電極は半導体チップの一辺と対向する他の辺側に配置されている。増幅手段のソース端子は半導体チップの一主面と対向する他の面(裏面)に形成された裏面電極と電気的に接続され、この裏面電極は基準電位に電位固定される。チップ側入力用電極は、半導体チップの一辺と向かい合うようにして配線基板の一主面に形成された基板側入力用電極と入力用ワイヤを介して電気的に接続され、チップ側出力用電極は、半導体チップの他の辺と向かい合うにようにして配線基板の一主面に形成された基板側出力用電極と出力用ワイヤを介して電気的に接続されている。   The high-frequency power amplifier includes a semiconductor chip having an amplification unit formed on one main surface thereof mounted on one main surface side of the wiring board, and an electrode formed on one main surface of the semiconductor chip and formed on one main surface of the wiring board. The electrode is electrically connected with a conductive wire. The amplifying means has a configuration in which, for example, a plurality of field effect transistors are electrically connected in parallel, and the gate terminal (input unit) of the amplifying means is for chip side input formed on one main surface of the semiconductor chip. The drain terminal (output unit) of the amplifying means is electrically connected to a chip side output electrode formed on one main surface of the semiconductor chip. The chip-side input electrode is disposed on one side of the semiconductor chip, and the chip-side output electrode is disposed on the other side facing the one side of the semiconductor chip. The source terminal of the amplifying means is electrically connected to a back surface electrode formed on the other surface (back surface) facing one main surface of the semiconductor chip, and the back surface electrode is fixed at a reference potential. The chip-side input electrode is electrically connected to the substrate-side input electrode formed on one main surface of the wiring board so as to face one side of the semiconductor chip via the input wire, and the chip-side output electrode is The substrate-side output electrode formed on one main surface of the wiring board so as to face the other side of the semiconductor chip is electrically connected via an output wire.

ところで、前記高周波電力増幅器においては、小型化及び低価格化を図るため、一つの半導体チップに複数の増幅手段を形成する試みが成されているが、例えば、一つの半導体チップに二つの増幅手段を形成する場合、前段の増幅手段と後段の増幅手段との入出力が逆になるため、入力用ワイヤと出力用ワイヤとが近接し、このワイヤ間での相互誘導作用によって高周波特性が劣化する問題があった。この問題は、特に、流れる電力差が大きい前段の入力用ワイヤと後段の出力用ワイヤとの間において顕著となる。   By the way, in the high-frequency power amplifier, an attempt to form a plurality of amplifying means in one semiconductor chip is made in order to reduce the size and the price. For example, two amplifying means are provided in one semiconductor chip. In this case, the input and output of the amplifying means at the preceding stage and the amplifying means at the succeeding stage are reversed, so that the input wire and the output wire are close to each other, and the high-frequency characteristics deteriorate due to the mutual induction action between these wires There was a problem. This problem is particularly noticeable between the front-stage input wire and the rear-stage output wire having a large difference in flowing power.

そこで、ワイヤ間の相互誘導作用による高周波特性の劣化を防止する技術が、例えば特開平９−２６０４１２号公報に記載されている。この技術は、チップ側入力用電極とチップ側出力用電極との間にチップ側ボンディング用電極を形成し、基板側入力用電極と基板側出力用電極との間に基板側ボンディング用電極を形成し、このボンディング用電極間をワイヤで電気的に接続し、チップ側ボンディング用電極又は基板側ボンディング用電極を基準電位に電位固定することによって、入力用ワイヤと出力用ワイヤとの相互誘導作用による高周波特性の劣化を防止している。
特開平９−２６０４１２号公報 Therefore, a technique for preventing the deterioration of the high frequency characteristics due to the mutual induction action between the wires is described in, for example, Japanese Patent Application Laid-Open No. 9-260412. In this technology, a chip-side bonding electrode is formed between the chip-side input electrode and the chip-side output electrode, and a substrate-side bonding electrode is formed between the substrate-side input electrode and the substrate-side output electrode. By electrically connecting the bonding electrodes with wires and fixing the chip-side bonding electrodes or the substrate-side bonding electrodes to the reference potential, a mutual induction effect between the input wires and the output wires is obtained. Deterioration of high frequency characteristics is prevented.
JP-A-9-260412

しかしながら、本発明者等は前述の技術を検討した結果、以下の問題点を見出した。   However, as a result of studying the above-described technique, the present inventors have found the following problems.

基板側ボンディング用電極は、基板側入力用電極と基板側出力用電極との間に配置されている。即ち、基板側入力用電極、基板側ボンディング用電極、基板側出力用電極の夫々は、半導体チップの一辺に沿って一直線上に配置されている。   The substrate-side bonding electrode is disposed between the substrate-side input electrode and the substrate-side output electrode. That is, each of the substrate-side input electrode, the substrate-side bonding electrode, and the substrate-side output electrode is arranged on a straight line along one side of the semiconductor chip.

基板側電極は、一般的にスクリーン印刷法によって形成されるため、ホトリソグラフィ技術によって形成されるチップ側電極よりも占有面積が大きくなる。また、伝搬経路を短縮するために基板側電極の直下においてスルーホール配線が形成される。このスルーホール配線の平面方向の面積(外形サイズ)は低抵抗化を図るためにある程度大きくしなければならないので、基板側電極の占有面積が大きくなる。更に、スルーホールの加工精度自体も低いので、基板側電極の占有面積が大きくなる。従って、基板側入力用電極、基板側ボンディング用電極、基板側出力用電極の夫々を半導体チップの一辺に沿って一直線上に配置した場合、これらの電極配列長が長くなり、チップ側入力用電極と基板側入力用電極とが向かい合わなくなると共に、チップ側出力用電極と基板側出力用電極とが向かい合わなくなるので、入力用ワイヤ及び出力用ワイヤの長さが長くなる。入力用ワイヤ及び出力用ワイヤの長さが長くなると、インダクタンスが増加し、高周波特性が劣化するため、前段の増幅手段と後段の増幅手段との間隔を広げてワイヤ長を短くしなければならず、半導体チップの占有面積が増加し、高周波電力増幅器の小型化を阻害する要因となる。   Since the substrate side electrode is generally formed by a screen printing method, it occupies a larger area than the chip side electrode formed by the photolithography technique. Further, in order to shorten the propagation path, a through-hole wiring is formed immediately below the substrate side electrode. Since the area (outer size) in the planar direction of the through-hole wiring has to be increased to some extent in order to reduce the resistance, the area occupied by the substrate-side electrode increases. Furthermore, since the through hole processing accuracy itself is low, the area occupied by the substrate-side electrode is increased. Therefore, when the substrate-side input electrode, the substrate-side bonding electrode, and the substrate-side output electrode are arranged on a straight line along one side of the semiconductor chip, the electrode arrangement length becomes long, and the chip-side input electrode And the substrate-side input electrode do not face each other, and the chip-side output electrode and the substrate-side output electrode do not face each other, so that the lengths of the input wire and the output wire are increased. If the length of the input wire and the output wire is increased, the inductance increases and the high frequency characteristics deteriorate. Therefore, the wire length must be shortened by widening the distance between the preceding amplification means and the subsequent amplification means. As a result, the area occupied by the semiconductor chip increases and becomes a factor that hinders miniaturization of the high-frequency power amplifier.

本発明の目的は、半導体装置の小型化を図ることが可能な技術を提供することにある。   An object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

平面が方形状で形成された半導体チップと、一主面側に前記半導体チップが搭載された配線基板と、前記半導体チップの一主面の第１領域に形成され、前記半導体チップの一辺側に配置された第１電極と、前記半導体チップの一主面の第１領域に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、前記半導体チップの一主面の第２領域に形成され、前記半導体チップの一辺側に配置された第２電極と、前記半導体チップの一主面の第２領域に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、前記半導体チップの一主面の第１領域と第２領域との間の第３領域に形成された第３電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第４電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第５電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、基準電位に電位固定される第３ワイヤを介して前記第３電極と電気的に接続された第６電極とを有する半導体装置であって、前記第６電極は、前記第５電極よりも前記半導体チップの一辺から遠く離れた位置に配置されている。前記第４電極は、前記半導体チップの一辺からの距離が前記第５電極とほぼ同一となる位置、又は前記第６電極よりも前記半導体チップの一辺から遠く離れた位置に配置されている。   A semiconductor chip having a rectangular plane, a wiring board on which the semiconductor chip is mounted on one main surface side, a first region on one main surface of the semiconductor chip, and on one side of the semiconductor chip A first amplifying device disposed in a first region of one main surface of the semiconductor chip and having an input portion electrically connected to the first electrode; and one main surface of the semiconductor chip. A second electrode disposed on one side of the semiconductor chip and a second region on one main surface of the semiconductor chip, and an output portion electrically connected to the second electrode. The second amplifying means, the third electrode formed in the third region between the first region and the second region of one main surface of the semiconductor chip, and the one side of the semiconductor chip facing the one side Formed on one main surface of the wiring board, the first wire via the first wire; A fourth electrode electrically connected to the electrode; and formed on one main surface of the wiring board so as to face one side of the semiconductor chip, and electrically connected to the second electrode via a second wire. The fifth electrode is electrically connected to the third electrode through a third wire that is formed on one main surface of the wiring board so as to face one side of the semiconductor chip and is fixed at a reference potential. The sixth electrode is arranged at a position farther from one side of the semiconductor chip than the fifth electrode. The fourth electrode is disposed at a position where the distance from one side of the semiconductor chip is substantially the same as the fifth electrode, or at a position farther from one side of the semiconductor chip than the sixth electrode.

上述した手段によれば、第６電極の占有面積に相当する分、第４電極と第５電極との間隔を狭くすることができるので、半導体チップの第１領域と第２領域との間隔を狭くすることができる。この結果、半導体チップの占有面積を縮小することができるので、半導体装置の小型化を図ることができる。   According to the above-described means, the distance between the fourth electrode and the fifth electrode can be reduced by an amount corresponding to the area occupied by the sixth electrode, so the distance between the first region and the second region of the semiconductor chip can be reduced. It can be narrowed. As a result, the area occupied by the semiconductor chip can be reduced, so that the semiconductor device can be reduced in size.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
半導体装置の小型化を図ることができる。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
The semiconductor device can be reduced in size.

以下、本発明の構成について、自動車電話、携帯電話等の携帯通信機器に組み込まれる高周波電力増幅器(高周波パワーモジュール)に本発明を適用した実施の形態とともに説明する。なお、実施の形態を説明するための図面において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
（実施形態１）
図１は、本発明の実施形態１である高周波電力増幅器の外観構成を示す斜視図であり、図２は、前記高周波電力増幅器の等価回路図であり、図３は図２に示す一点鎖線で囲まれた部分と対応する配線基板の要部平面図であり、図４は図３の要部斜視図であり、図５は図３の要部拡大平面図であり、図６は前記高周波電力増幅器に組み込まれた半導体チップのトランジスタ形成領域における要部断面図であり、図７は、前記半導体チップのアイソレーション領域における要部断面図である。 Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a high-frequency power amplifier (high-frequency power module) incorporated in a mobile communication device such as an automobile phone or a mobile phone. Note that components having the same function are denoted by the same reference symbols in the drawings for describing the embodiments, and the repetitive description thereof is omitted.
(Embodiment 1)
1 is a perspective view showing an external configuration of a high-frequency power amplifier according to a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the high-frequency power amplifier, and FIG. 3 is an alternate long and short dash line shown in FIG. 4 is a plan view of the main part of the wiring board corresponding to the enclosed part, FIG. 4 is a perspective view of the main part of FIG. 3, FIG. 5 is an enlarged plan view of the main part of FIG. 3, and FIG. FIG. 7 is a cross-sectional view of a main part in a transistor formation region of a semiconductor chip incorporated in an amplifier, and FIG. 7 is a cross-sectional view of a main part in an isolation region of the semiconductor chip.

本実施形態の高周波電力増幅器は、図１に示すように、板状の配線基板１の一主面上にキャップ８が重ねられ、外観的には偏平な矩形体構造になっている。配線基板１は、平面が方形状(本実施形態においては長方形状)で形成され、多層配線構造のセラミックス基板で形成されている。キャップ８は、平面が方形状（本実施形態においては長方形状）で形成され、導電性の金属材料で形成されている。このキャップ８は、シールド効果を持たせるために基準電位(例えば０［Ｖ］)に電位固定される。   As shown in FIG. 1, the high-frequency power amplifier according to the present embodiment has a flat rectangular body structure in which a cap 8 is superimposed on one main surface of a plate-like wiring substrate 1. The wiring substrate 1 is formed of a ceramic substrate having a multi-layer wiring structure, and the plane is formed in a rectangular shape (in the present embodiment, a rectangular shape). The cap 8 is formed in a rectangular shape (in the present embodiment, a rectangular shape) on the plane, and is formed of a conductive metal material. The cap 8 is fixed at a reference potential (for example, 0 [V]) in order to provide a shielding effect.

前記高周波電力増幅器は、図２に示すように、多段式増幅回路で構成されている。この多段式増幅回路は、主に、容量素子Ｃ１〜Ｃ１１、抵抗素子Ｒ１〜Ｒ４、マイクロストリップ線路ＳＴＬ１〜ＳＴＬ３、増幅手段ＰＷ１〜増幅手段ＰＷ３等で構成されている。   As shown in FIG. 2, the high frequency power amplifier is composed of a multistage amplifier circuit. This multistage amplifier circuit mainly includes capacitive elements C1 to C11, resistance elements R1 to R4, microstrip lines STL1 to STL3, amplifying means PW1 to amplifying means PW3, and the like.

増幅手段ＰＷ１、ＰＷ２、ＰＷ３の夫々は、複数の電界効果トランジスタの夫々を電気的に並列に接続した構成になっている。増幅手段ＰＷ１は、ゲートの総延長が４０００［μｍ］程度で形成され、増幅手段ＰＷ２は、ゲートの総延長が３２００［μｍ］程度で形成され、増幅手段ＰＷ３は、ゲートの総延長が８０００［μｍ］程度で形成されている。   Each of the amplifying means PW1, PW2, and PW3 has a configuration in which a plurality of field effect transistors are electrically connected in parallel. The amplifying unit PW1 is formed with a total gate extension of about 4000 [μm], the amplifying unit PW2 is formed with a total gate extension of about 3200 [μm], and the amplifying unit PW3 has a total gate extension of about 8000 [μm]. μm] or so.

増幅手段ＰＷ１のゲート端子(入力部)は高周波電力(例えば１［ｍＷ］)が印加される入力用外部端子Ｐinと電気的に接続され、増幅手段ＰＷ１のドレイン端子(出力部)は後段の増幅手段ＰＷ２のゲート端子(入力部)及びマイクロストリップ線路ＳＴＬ１の一端側と電気的に接続されている。増幅手段ＰＷ２のドレイン端子(出力部)は後段の増幅手段ＰＷ３のゲート端子(入力部)及びマイクロストリップ線路ＳＴＬ２の一端側と電気的に接続されている。増幅手段ＰＷ３のドレイン端子(出力部)は出力用外部端子Ｐoutと電気的に接続されている。   The gate terminal (input unit) of the amplifying unit PW1 is electrically connected to the input external terminal Pin to which high-frequency power (for example, 1 [mW]) is applied, and the drain terminal (output unit) of the amplifying unit PW1 is amplified in the subsequent stage. The gate terminal (input part) of the means PW2 and one end side of the microstrip line STL1 are electrically connected. The drain terminal (output unit) of the amplifying unit PW2 is electrically connected to the gate terminal (input unit) of the subsequent amplifying unit PW3 and one end side of the microstrip line STL2. The drain terminal (output unit) of the amplifying means PW3 is electrically connected to the output external terminal Pout.

増幅手段ＰＷ１、ＰＷ２、ＰＷ３の夫々のソース端子は、基準電位（例えば０［Ｖ］）に電位固定される基準電位用外部端子と電気的に接続されている。マイクロストリップ線路ＳＴＬ１、ＳＴＬ２、ＳＴＬ３の夫々の他端側は、電源電位(例えば３．５［Ｖ］)が印加される電源電位用外部端子ＶＤＤと電気的に接続されている。なお、増幅手段ＰＷ１、ＰＷ２、ＰＷ３の夫々のゲート端子には外部端子ＶＧが電気的に接続され、この外部端子ＶＧには出力電力を調整するための電圧（ＡＰＣ信号，オートマチック・パワー・コントロール・シグナル）が印加される。 The source terminals of the amplifying means PW1, PW2, and PW3 are electrically connected to a reference potential external terminal that is fixed at a reference potential (for example, 0 [V]). The other end sides of the microstrip lines STL1, STL2, and STL3 are electrically connected to a power supply potential external terminal V DD to which a power supply potential (for example, 3.5 [V]) is applied. Incidentally, the amplifying means PW1, PW2, PW3 external terminal VG to respective gate terminals of which are electrically connected, the voltage (APC signal for adjusting the output power to the external terminal V G, Automatic Power Control・ Signal) is applied.

増幅手段ＰＷ１、ＰＷ２の夫々は、図３に示す半導体チップ５に形成され、増幅手段ＰＷ３は、図示していないが、半導体チップ５と異なる他の半導体チップに形成されている。半導体チップ５は配線基板１の一主面に形成された凹部１Ａ内に搭載され、他の半導体チップは配線基板１の一主面に形成された他の凹部内に搭載されている。即ち、増幅手段が形成された半導体チップは配線基板１の一主面側に搭載されている。半導体チップ５、他の半導体チップの夫々は、平面が方形状（本実施形態においては長方形状）で形成されている。なお、増幅手段ＰＷ３が形成された他の半導体チップについては以降の説明を省略する。   Each of the amplifying means PW1 and PW2 is formed on the semiconductor chip 5 shown in FIG. 3, and the amplifying means PW3 is formed on another semiconductor chip different from the semiconductor chip 5 although not shown. The semiconductor chip 5 is mounted in a recess 1 </ b> A formed on one main surface of the wiring substrate 1, and the other semiconductor chip is mounted in another recess formed on one main surface of the wiring substrate 1. That is, the semiconductor chip on which the amplifying means is formed is mounted on one main surface side of the wiring substrate 1. Each of the semiconductor chip 5 and the other semiconductor chips is formed in a rectangular shape (in the present embodiment, a rectangular shape). In addition, the following description is abbreviate | omitted about the other semiconductor chip in which amplification means PW3 was formed.

半導体チップ５が搭載された凹部１Ａの底面には、図４に示すように、導電プレート１Ｂが形成されている。導電プレート１Ｂは、その直下に形成されたスルーホール配線３を介して、配線基板１の一主面と対向する他の主面(裏面)に形成された基準電位用外部端子４と電気的に接続されている。この基準電位用外部端子４は例えば０［Ｖ］電位に電位固定される。なお、前述の入力用外部端子Ｐin、出力用外部端子Ｐout、電源電位用外部端子ＶＤＤ、外部端子ＶＧの夫々も配線基板１の裏面に形成されている。 As shown in FIG. 4, a conductive plate 1B is formed on the bottom surface of the recess 1A on which the semiconductor chip 5 is mounted. The conductive plate 1B is electrically connected to the reference potential external terminal 4 formed on the other main surface (back surface) opposite to one main surface of the wiring board 1 through the through-hole wiring 3 formed immediately below the conductive plate 1B. It is connected. The reference potential external terminal 4 is fixed at a potential of, for example, 0 [V]. The input external terminal Pin of the foregoing, the output external terminal Pout, the power supply potential external terminal V DD, are formed on the back surface each well of the wiring substrate 1 of the external terminal V G.

図５に示すように、増幅手段ＰＷ１は半導体チップ５の一主面の第１領域５Ａに形成されている。増幅手段ＰＷ１のゲート端子は、半導体チップ５の一主面の第１領域５Ａに形成され、半導体チップ５の一辺５Ｘ側（本実施形態においては一長辺側）に配置されたチップ側入力用電極６Ａと電気的に接続されている。また、増幅手段ＰＷ１のドレイン端子は、半導体チップ５の一主面の第１領域５Ａに形成され、半導体チップ５の一辺５Ｘと対向する他の辺５Ｙ側（本実施形態においては他の長辺側）に配置されたチップ側出力用電極６Ｄと電気的に接続されている。   As shown in FIG. 5, the amplifying unit PW1 is formed in the first region 5A on one main surface of the semiconductor chip 5. The gate terminal of the amplifying means PW1 is formed in the first region 5A of one main surface of the semiconductor chip 5, and is for chip side input arranged on one side 5X side (one long side in this embodiment) of the semiconductor chip 5. It is electrically connected to the electrode 6A. Further, the drain terminal of the amplifying means PW1 is formed in the first region 5A of one main surface of the semiconductor chip 5, and is on the other side 5Y side facing the one side 5X of the semiconductor chip 5 (in this embodiment, other long sides). The chip side output electrode 6D is electrically connected to the chip side output electrode 6D.

増幅手段ＰＷ２は半導体チップ５の一主面の第２領域５Ｂに形成されている。増幅手段ＰＷ２のドレイン端子は、半導体チップ５の一主面の第２領域５Ｂに形成され、半導体チップ５の一辺５Ｘ側に配置されたチップ側出力用電極６Ｂと電気的に接続されている。また、増幅手段ＰＷ２のゲート端子は、半導体チップ５の一主面の第２領域５Ｂに形成され、半導体チップ５の他の辺５Ｙ側に配置されたチップ側入力用電極６Ｅと電気的に接続されている。   The amplifying means PW2 is formed in the second region 5B on one main surface of the semiconductor chip 5. The drain terminal of the amplifying unit PW2 is formed in the second region 5B on one main surface of the semiconductor chip 5, and is electrically connected to the chip-side output electrode 6B disposed on the one side 5X side of the semiconductor chip 5. Further, the gate terminal of the amplifying unit PW2 is formed in the second region 5B on one main surface of the semiconductor chip 5, and is electrically connected to the chip-side input electrode 6E disposed on the other side 5Y side of the semiconductor chip 5. Has been.

増幅手段ＰＷ１、ＰＷ２の夫々のソース端子は、後で詳細に説明するが、半導体チップ５の一主面と対向する他の主面（裏面）に形成された裏面電極と電気的に接続されている。   As will be described in detail later, the source terminals of the amplifying means PW1 and PW2 are electrically connected to the back electrode formed on the other main surface (back surface) opposite to the main surface of the semiconductor chip 5. Yes.

半導体チップ５の一主面の第１領域５Ａと第２領域５Ｂとの間にはこれらの領域間を電気的に分離するための第３領域(アイソレーション領域)５Ｃが形成されている。この第３領域５Ｃには、半導体チップ５の一辺５Ｘ側に配置されたチップ側ボンディング用電極６Ｃ及び半導体チップ５の他の辺５Ｙ側に配置されたチップ側ボンディング用電極６Ｆが形成されている。   Between the first region 5A and the second region 5B on one main surface of the semiconductor chip 5, a third region (isolation region) 5C for electrically separating these regions is formed. In the third region 5C, a chip-side bonding electrode 6C disposed on one side 5X side of the semiconductor chip 5 and a chip-side bonding electrode 6F disposed on the other side 5Y side of the semiconductor chip 5 are formed. .

チップ側入力用電極６Ａは、半導体チップ５の一辺５Ｘと向かい合うようにして配線基板１の一主面に形成された基板側入力用電極２Ａと入力用ワイヤ７Ａを介して電気的に接続されている。基板側入力用電極２Ａは、その直下に形成されたスルーホール配線３及び内部配線を介して、配線基板１の裏面に形成された入力用外部端子(Ｐin)と電気的に接続されている。   The chip-side input electrode 6A is electrically connected to the substrate-side input electrode 2A formed on one main surface of the wiring substrate 1 so as to face one side 5X of the semiconductor chip 5 via the input wire 7A. Yes. The substrate-side input electrode 2A is electrically connected to an input external terminal (Pin) formed on the back surface of the wiring substrate 1 through a through-hole wiring 3 and an internal wiring formed immediately below the substrate-side input electrode 2A.

チップ側出力用電極６Ｂは、半導体チップ５の一辺５Ｘと向かい合うようにして配線基板１の一主面に形成された基板側出力用電極２Ｂと出力用ワイヤ７Ｂを介して電気的に接続されている。基板側出力用電極２Ｂは、その直下に形成されたスルーホール配線３及び内部配線を介して、増幅手段ＰＷ３が形成された他の半導体チップの一辺と向かい合うようにして配線基板１の一主面に形成された基板入力用電極と電気的に接続されている。   The chip-side output electrode 6B is electrically connected to the substrate-side output electrode 2B formed on one main surface of the wiring substrate 1 so as to face one side 5X of the semiconductor chip 5 via the output wire 7B. Yes. The substrate-side output electrode 2B is provided on one main surface of the wiring substrate 1 so as to face one side of the other semiconductor chip on which the amplification means PW3 is formed via the through-hole wiring 3 and the internal wiring formed immediately below the substrate-side output electrode 2B. Are electrically connected to the substrate input electrodes formed on the substrate.

チップ側ボンディング用電極６Ｃは、半導体チップ５の一辺５Ｘと向かい合うようにして配線基板１の一主面に形成された基板側ボンディング用電極２Ｃとワイヤ７Ｃを介して電気的に接続されている。基板側ボンディング用電極２Ｃは、その直下に形成されたスルーホール配線３及び内部配線を介して、配線基板１の裏面に形成された基準電位用外部端子４と電気的に接続されている。即ち、ワイヤ７Ｃは基準電位に電位固定される。   The chip-side bonding electrode 6C is electrically connected to a substrate-side bonding electrode 2C formed on one main surface of the wiring substrate 1 so as to face one side 5X of the semiconductor chip 5 via a wire 7C. The substrate-side bonding electrode 2C is electrically connected to a reference potential external terminal 4 formed on the back surface of the wiring substrate 1 through a through-hole wiring 3 and an internal wiring formed immediately below the substrate-side bonding electrode 2C. That is, the wire 7C is fixed at the reference potential.

チップ側出力用電極６Ｄは、半導体チップ５の他の辺５Ｙと向かい合うようにして配線基板１の一主面に形成された基板側出力用電極２Ｄと出力用ワイヤ７Ｄを介して電気的に接続されている。基板側出力用電極２Ｄは、その直下にスルーホール配線３が形成されている。   The chip-side output electrode 6D is electrically connected to the substrate-side output electrode 2D formed on one main surface of the wiring substrate 1 so as to face the other side 5Y of the semiconductor chip 5 via the output wire 7D. Has been. The through-hole wiring 3 is formed immediately below the substrate-side output electrode 2D.

チップ側入力用電極６Ｅは、半導体チップ５の他の辺５Ｙと向かい合うようにして配線基板１の一主面に形成された基板側入力用電極２Ｅと入力用ワイヤ７Ｅを介して電気的に接続されている。基板側入力用電極２Ｅは、スルーホール配線３及び内部配線を介して、基板側出力用電極２Ｄと電気的に接続されている。   The chip-side input electrode 6E is electrically connected to the substrate-side input electrode 2E formed on one main surface of the wiring substrate 1 so as to face the other side 5Y of the semiconductor chip 5 through the input wire 7E. Has been. The substrate side input electrode 2E is electrically connected to the substrate side output electrode 2D through the through-hole wiring 3 and the internal wiring.

チップ側ボンディング用電極６Ｆは、半導体チップ５の他の辺５Ｙと向かい合うようにして配線基板１の一主面に形成された基板側ボンディング用電極２Ｆとワイヤ７Ｆを介して電気的に接続されている。基板側ボンディング用電極２Ｆは、その直下に形成されたスルーホール配線３及び内部配線を介して、配線基板１の裏面に形成された基準電位用外部端子４と電気的に接続されている。即ち、ワイヤ７Ｆは基準電位に電位固定される。   The chip-side bonding electrode 6F is electrically connected via a wire 7F to a substrate-side bonding electrode 2F formed on one main surface of the wiring board 1 so as to face the other side 5Y of the semiconductor chip 5. Yes. The substrate-side bonding electrode 2F is electrically connected to a reference potential external terminal 4 formed on the back surface of the wiring substrate 1 through a through-hole wiring 3 and an internal wiring formed immediately below the substrate-side bonding electrode 2F. That is, the wire 7F is fixed at the reference potential.

チップ側出力用電極６Ｄと半導体チップ５の他の辺５Ｙとの距離は、チップ側入力用電極６Ａと半導体チップ５の一辺５Ｘとの距離よりも短くなっている。また、チップ側出力用電極６Ｂと半導体チップ５の一辺５Ｘとの距離は、チップ側入力用電極６Ｅと半導体チップ５の他の辺５Ｙとの距離よりも短くなっている。これは、出力用ワイヤの長さを短くし、出力抵抗を低くしている。   The distance between the chip-side output electrode 6D and the other side 5Y of the semiconductor chip 5 is shorter than the distance between the chip-side input electrode 6A and one side 5X of the semiconductor chip 5. The distance between the chip-side output electrode 6B and one side 5X of the semiconductor chip 5 is shorter than the distance between the chip-side input electrode 6E and the other side 5Y of the semiconductor chip 5. This shortens the length of the output wire and lowers the output resistance.

半導体チップ５の一主面の第１領域５Ａには、増幅手段ＰＷ１のソース端子と電気的に接続されたソース電極６Ｓが形成されている。このソース電極６Ｓは、チップ側入力用電極６Ａよりも半導体チップ５の一辺５Ｘ側に配置されている。また、半導体チップ５の一主面の第２領域５Ｂには、増幅手段ＰＷ２のソース端子と電気的に接続されたソース電極６Ｓが配置されている。これらのソース電極６Ｓはプローブ検査時に使用される。   A source electrode 6S electrically connected to the source terminal of the amplifying unit PW1 is formed in the first region 5A on one main surface of the semiconductor chip 5. The source electrode 6S is disposed on the side 5X side of the semiconductor chip 5 relative to the chip-side input electrode 6A. A source electrode 6S electrically connected to the source terminal of the amplifying unit PW2 is disposed in the second region 5B on one main surface of the semiconductor chip 5. These source electrodes 6S are used during probe inspection.

本実施形態の高周波電力増幅器において、入力用ワイヤ７Ａは出力用ワイヤ７Ｂと近接して配置されている。入力ワイヤ７Ａは前段の増幅手段ＰＷ１のゲート端子（入力部）に電気的に接続され、出力用ワイヤ７Ｂは後段の増幅手段ＰＷ２のドレイン端子（出力部）に電気的に接続されているので、入力用ワイヤ７Ａを流れる電力と出力用ワイヤ７Ｂを流れる電力との差は大きいが、基準電位に電位固定されるワイヤ７Ｃが入力用ワイヤ７Ａと出力用ワイヤ７Ｂとの間に配置されているので、入力用ワイヤ７Ａと出力用ワイヤ７Ｂとの相互誘導作用による高周波特性の劣化を防止することができる。   In the high-frequency power amplifier according to the present embodiment, the input wire 7A is disposed close to the output wire 7B. Since the input wire 7A is electrically connected to the gate terminal (input part) of the preceding amplification means PW1, and the output wire 7B is electrically connected to the drain terminal (output part) of the latter amplification means PW2, Although the difference between the power flowing through the input wire 7A and the power flowing through the output wire 7B is large, the wire 7C whose potential is fixed to the reference potential is disposed between the input wire 7A and the output wire 7B. The deterioration of the high frequency characteristics due to the mutual induction action between the input wire 7A and the output wire 7B can be prevented.

また、出力用ワイヤ７Ｄは入力用ワイヤ７Ｅと近接して配置されている。出力用ワイヤ７Ｄは前段の増幅手段ＰＷ１のドレイン端子（出力部）と電気的に接続され、入力用ワイヤ７Ｅは後段の増幅手段ＰＷ２のゲート端子（入力部）と電気的に接続されているので、出力用ワイヤ７Ｄを流れる電力と入力用ワイヤ７Ｅを流れる電力とはほぼ同一であり、このワイヤ間での相互誘導作用による高周波特性の劣化は小さいが、基準電位に電位固定されるワイヤ７Ｆが出力用ワイヤ７Ｄと入力用ワイヤ７Ｅとの間に配置されているので、出力用ワイヤ７Ｄと入力用ワイヤ７Ｅとの相互誘導作用による高周波特性の劣化を防止することができる。   Further, the output wire 7D is disposed close to the input wire 7E. Since the output wire 7D is electrically connected to the drain terminal (output unit) of the preceding amplification means PW1, and the input wire 7E is electrically connected to the gate terminal (input part) of the subsequent amplification means PW2. The power flowing through the output wire 7D and the power flowing through the input wire 7E are almost the same, and the deterioration of the high frequency characteristics due to the mutual induction action between these wires is small, but the wire 7F whose potential is fixed to the reference potential is Since it is disposed between the output wire 7D and the input wire 7E, it is possible to prevent deterioration of the high frequency characteristics due to the mutual induction action between the output wire 7D and the input wire 7E.

基板側ボンディング用電極２Ｃは、基板側出力用電極２Ｂよりも半導体チップ５の一辺５Ｘから遠く離れた位置に配置されている。基板側入力用電極２Ａは、半導体チップ５の一辺５Ｘからの距離が基板側出力用電極２Ｂとほぼ同一となる位置に配置されている。即ち、基板側ボンディング用電極２Ｃは、基板側入力用電極２Ａと基板側出力用電極２Ｂとの間に配置されておらず、基板側入力用電極２Ａ及び基板側出力用電極２Ｂよりも半導体チップ５の一辺５Ｘから遠く離れた位置に配置されている。従って、基板側ボンディング用電極２Ｃの占有面積に相当する分、基板側入力用電極２Ａと基板側出力用電極２Ｂとの間隔を狭くすることができ、これに伴って半導体チップ５の第１領域５Ａと第２領域５Ｂとの間隔も狭くすることができるので、半導体チップ５の占有面積を縮小することができる。   The substrate-side bonding electrode 2C is disposed at a position farther from one side 5X of the semiconductor chip 5 than the substrate-side output electrode 2B. The substrate-side input electrode 2A is disposed at a position where the distance from one side 5X of the semiconductor chip 5 is substantially the same as the substrate-side output electrode 2B. That is, the substrate-side bonding electrode 2C is not disposed between the substrate-side input electrode 2A and the substrate-side output electrode 2B, and is more semiconductor than the substrate-side input electrode 2A and the substrate-side output electrode 2B. 5 is arranged at a position far from one side 5X. Accordingly, the distance between the substrate-side input electrode 2A and the substrate-side output electrode 2B can be reduced by an amount corresponding to the area occupied by the substrate-side bonding electrode 2C, and accordingly, the first region of the semiconductor chip 5 Since the distance between 5A and the second region 5B can also be reduced, the occupation area of the semiconductor chip 5 can be reduced.

基板側ボンディング用電極２Ｆは、基板側出力用電極２Ｄよりも半導体チップ５の他の辺５Ｙから遠く離れた位置に配置されている。基板側入力用電極２Ｅは、半導体チップ５の他の辺５Ｙからの距離が基板側出力用電極２Ｄとほぼ同一となる位置に配置されている。即ち、基板側ボンディング用電極２Ｆは、基板側入力用電極２Ｅと基板側出力用電極２Ｄとの間に配置されておらず、基板側入力用電極２Ｅ及び基板側出力用電極２Ｄよりも半導体チップ５の他の辺５Ｙから遠く離れた位置に配置されている。従って、基板側ボンディング用電極２Ｆの占有面積に相当する分、基板側入力用電極２Ｅと基板側出力用電極２Ｄとの間隔を狭くすることができ、これに伴って半導体チップ５の第１領域５Ａと第２領域５Ｂとの間隔も狭くすることができるので、半導体チップ５の占有面積を縮小することができる。   The substrate-side bonding electrode 2F is arranged at a position farther from the other side 5Y of the semiconductor chip 5 than the substrate-side output electrode 2D. The substrate-side input electrode 2E is disposed at a position where the distance from the other side 5Y of the semiconductor chip 5 is substantially the same as the substrate-side output electrode 2D. That is, the substrate-side bonding electrode 2F is not disposed between the substrate-side input electrode 2E and the substrate-side output electrode 2D, and is more semiconductor than the substrate-side input electrode 2E and the substrate-side output electrode 2D. 5 is arranged at a position far from the other side 5Y. Accordingly, the distance between the substrate-side input electrode 2E and the substrate-side output electrode 2D can be reduced by an amount corresponding to the area occupied by the substrate-side bonding electrode 2F, and accordingly, the first region of the semiconductor chip 5 can be reduced. Since the distance between 5A and the second region 5B can also be reduced, the occupation area of the semiconductor chip 5 can be reduced.

半導体チップ５は、図６に示すように、例えば、単結晶珪素からなるp+型半導体基板１０Ａの一主面上にp-型エピタキシャル層１０Ｂが形成された半導体基体１０を主体とする構成になっている。   As shown in FIG. 6, the semiconductor chip 5 has a configuration mainly composed of a semiconductor substrate 10 in which a p − type epitaxial layer 10B is formed on one main surface of a p + type semiconductor substrate 10A made of single crystal silicon, for example. ing.

増幅手段ＰＷ１及びＰＷ２を構成する電界効果トランジスタは、半導体基体１０の一主面のトランジスタ形成領域に形成されている。この電界効果トランジスタは、主に、チャネル形成領域であるｐ型ウエル領域１２、ゲート絶縁膜１４、ゲート電極１５、ソース領域及びドレイン領域である一対のn-型半導体領域１６及び一対のn+型半導体領域１７で構成されている。   The field effect transistors constituting the amplifying means PW1 and PW2 are formed in a transistor formation region on one main surface of the semiconductor substrate 10. This field effect transistor mainly includes a p-type well region 12, which is a channel formation region, a gate insulating film 14, a gate electrode 15, a pair of n− type semiconductor regions 16 which are a source region and a drain region, and a pair of n + type semiconductors. The area 17 is configured.

ドレイン領域であるn+型半導体領域１７には、層間絶縁膜１８に形成された接続孔を通して、第１層目の配線層に形成された配線１９Ａが電気的に接続されている。ソース領域であるn+型半導体領域１７には、層間絶縁膜１８に形成された接続孔を通して、第１層目の配線層に形成された配線１９Ｂが電気的に接続されている。配線１９Ｂは、層間絶縁膜１８に形成された接続孔を通して、p-型エピタキシャル層１３に形成されたp+型半導体領域１３に電気的に接続されている。p+型半導体領域１３はp+型半導体基板１０Ａに電気的に接続されている。ゲート電極１５には、詳細に図示していないが、層間絶縁膜１８に形成された接続孔を通して、第１層目の配線層に形成された配線１９Ｃが電気的に接続されている。   A wiring 19 </ b> A formed in the first wiring layer is electrically connected to the n + -type semiconductor region 17 that is a drain region through a connection hole formed in the interlayer insulating film 18. A wiring 19B formed in the first wiring layer is electrically connected to the n + type semiconductor region 17 which is a source region through a connection hole formed in the interlayer insulating film 18. The wiring 19B is electrically connected to the p + type semiconductor region 13 formed in the p − type epitaxial layer 13 through a connection hole formed in the interlayer insulating film 18. The p + type semiconductor region 13 is electrically connected to the p + type semiconductor substrate 10A. Although not shown in detail, the gate electrode 15 is electrically connected to a wiring 19 </ b> C formed in the first wiring layer through a connection hole formed in the interlayer insulating film 18.

配線１９Ａには、層間絶縁膜２０に形成された接続孔を通して、第２層目の配線層に形成された配線２１Ａが電気的に接続されている。この配線２１Ａの一部でチップ側出力用電極６Ｄ及びチップ側出力用電極６Ｂが形成されている。配線１９Ｂには、層間絶縁膜２０に形成された接続孔を通して、第２層目の配線層に形成された配線２１Ｂが電気的に接続されている。この配線２１Ｂの一部でプローブ検査用の電極が形成されている。配線１９Ｃには、図示していないが、層間絶縁膜２０に形成された接続孔を通して、第２層目の配線層に形成された配線が電気的に接続されている。この配線の一部でチップ側入力用電極６Ａ及びチップ側入力用電極６Ｅが形成されている。   A wiring 21A formed in the second wiring layer is electrically connected to the wiring 19A through a connection hole formed in the interlayer insulating film 20. A chip-side output electrode 6D and a chip-side output electrode 6B are formed in a part of the wiring 21A. A wiring 21B formed in the second wiring layer is electrically connected to the wiring 19B through a connection hole formed in the interlayer insulating film 20. An electrode for probe inspection is formed in a part of the wiring 21B. Although not shown, the wiring formed in the second wiring layer is electrically connected to the wiring 19C through a connection hole formed in the interlayer insulating film 20. A chip-side input electrode 6A and a chip-side input electrode 6E are formed by a part of the wiring.

半導体チップ５の第３領域５Ｃにおいて、図７に示すように、フィールド絶縁膜１１上には、第１層目の配線層に形成された配線１９Ｄが形成されている。この配線１９Ｄは、半導体チップ５の一辺５Ｘと直行する方向に向かって延在している。配線１９Ｄには、層間絶縁膜２０に形成された接続孔を通して、第２層目の配線層に形成された配線２１Ｄが形成されている。この配線２１Ｄは、配線１９Ｄと同様に、半導体チップ５の一辺５Ｘと直行する方向に向かって延在している。この配線２１Ｄの一部でチップ側ボンディング用電極６Ｃ及び６Ｆが形成されている。   In the third region 5 </ b> C of the semiconductor chip 5, as shown in FIG. 7, the wiring 19 </ b> D formed in the first wiring layer is formed on the field insulating film 11. The wiring 19 </ b> D extends in a direction perpendicular to the side 5 </ b> X of the semiconductor chip 5. In the wiring 19D, a wiring 21D formed in the second wiring layer is formed through a connection hole formed in the interlayer insulating film 20. Similar to the wiring 19D, the wiring 21D extends in a direction perpendicular to the one side 5X of the semiconductor chip 5. Chip-side bonding electrodes 6C and 6F are formed in a part of the wiring 21D.

半導体基体１０の一主面と対向する他の主面（裏面）には裏面電極２１が形成されている。この裏面電極２１は、導電性の接着材を介在して、配線基板１の凹部１Ａの底面に形成された導電プレート１Ｂと電気的にかつ機械的に接続されている。即ち、増幅手段ＰＷ１、ＰＷ２の夫々のソース端子は基準電位に電位固定される。   A back electrode 21 is formed on the other main surface (back surface) opposite to one main surface of the semiconductor substrate 10. The back electrode 21 is electrically and mechanically connected to a conductive plate 1B formed on the bottom surface of the recess 1A of the wiring board 1 with a conductive adhesive interposed therebetween. That is, the source terminals of the amplifying means PW1 and PW2 are fixed to the reference potential.

本実施形態の高周波電力増幅器において、半導体チップ５の第１領域５Ａと第２領域５Ｂとの間の第３領域（アイソレーション領域）５Ｃには、基準電位に電位固定される配線１９Ｄ及び配線２１Ｄが半導体チップ５の一辺５Ｘと直行する方向に向って延在している。また、第３領域５Ｃには、基準電位に電位固定されるp+型半導体領域１３が半導体チップ５の一辺５Ｘと直行する方向に向って延在し、しかも半導体基体１０が基準電位に電位固定される。従って、半導体チップ５においては磁束の干渉を抑える構成になっているので、高周波特性が劣化することはない。   In the high-frequency power amplifier according to the present embodiment, the third region (isolation region) 5C between the first region 5A and the second region 5B of the semiconductor chip 5 has a wiring 19D and a wiring 21D that are fixed to the reference potential. Extends in a direction perpendicular to one side 5X of the semiconductor chip 5. Further, in the third region 5C, a p + type semiconductor region 13 whose potential is fixed to the reference potential extends in a direction perpendicular to the one side 5X of the semiconductor chip 5, and the potential of the semiconductor substrate 10 is fixed to the reference potential. The Accordingly, since the semiconductor chip 5 is configured to suppress the interference of magnetic flux, the high frequency characteristics are not deteriorated.

このように、本実施形態によれば、以下の効果が得られる。
（１）基板側ボンディング用電極２Ｃは、基板側入力用電極２Ａ及び基板側出力用電極２Ｂよりも半導体チップ５の一辺５Ｘから遠く離れた位置に配置され、基板側ボンディング用電極２Ｆは、基板側入力用電極２Ｅ及び基板側出力用電極２Ｄよりも半導体チップ５の他の辺５Ｙから遠く離れた位置に配置されていることから、基板側ボンディング用電極２Ｃの占有面積に相当する分、基板側入力用電極２Ａと基板側出力用電極２Ｂとの間隔を狭くすることができ、また、基板側ボンディング用電極２Ｆの占有面積に相当する分、基板側入力用電極２Ｅと基板側出力用電極２Ｄとの間隔を狭くすることができるので、半導体チップ５の第１領域５Ａと第２領域５Ｂとの間隔を狭くすることができる。この結果、半導体チップ５の占有面積を縮小することができるので、高周波電力増幅器の小型化を図ることができる。 Thus, according to this embodiment, the following effects can be obtained.
(1) The substrate-side bonding electrode 2C is disposed at a position farther from one side 5X of the semiconductor chip 5 than the substrate-side input electrode 2A and the substrate-side output electrode 2B. Since it is arranged at a position farther from the other side 5Y of the semiconductor chip 5 than the side input electrode 2E and the substrate side output electrode 2D, it corresponds to the area occupied by the substrate side bonding electrode 2C. The distance between the side input electrode 2A and the substrate side output electrode 2B can be reduced, and the substrate side input electrode 2E and the substrate side output electrode are equivalent to the occupied area of the substrate side bonding electrode 2F. Since the distance to 2D can be narrowed, the distance between the first region 5A and the second region 5B of the semiconductor chip 5 can be narrowed. As a result, since the area occupied by the semiconductor chip 5 can be reduced, the high-frequency power amplifier can be miniaturized.

（２）基板側入力用電極２Ａは半導体チップ５の一辺５Ｘからの距離が基板側出力用電極２Ｂとほぼ同一となる位置に配置され、基板側ボンディング用電極２Ｃは基板側入力用電極２Ａ及び基板側出力用電極２Ｂよりも半導体チップ５の一辺５Ｘから遠く離れた位置に配置されていることから、基準電位に電位固定されるワイヤ７Ｃが基板側入力用電極２Ａと基板側出力用電極２Ｂとの間を横切るので、基板側入力用電極２Ａと基板側出力用電極２Ｂとの間に基板側ボンディング用電極２Ｃを配置した場合に比べて、磁束の干渉を更に抑制することができる。 (2) The substrate-side input electrode 2A is disposed at a position where the distance from one side 5X of the semiconductor chip 5 is substantially the same as the substrate-side output electrode 2B, and the substrate-side bonding electrode 2C is the substrate-side input electrode 2A and Since the substrate 7 is disposed at a position farther from one side 5X of the semiconductor chip 5 than the substrate-side output electrode 2B, the wire 7C that is fixed at the reference potential is connected to the substrate-side input electrode 2A and the substrate-side output electrode 2B. Therefore, the interference of magnetic flux can be further suppressed as compared with the case where the substrate-side bonding electrode 2C is disposed between the substrate-side input electrode 2A and the substrate-side output electrode 2B.

なお、本実施形態では、基準電位に電位固定されるワイヤ７Ｃ及びワイヤ７Ｆを配置した例について説明したが、入力用ワイヤ７Ｅを流れる電力と出力用ワイヤ７Ｄを流れる電力とはほぼ同一なので、前段の増幅手段ＰＷ１のドレイン端子（出力部）に接続された出力用ワイヤ７Ｄと後段の増幅手段ＰＷ２のゲート端子（入力部）に接続された入力用ワイヤ７Ｅとの間に、基準電位に電位固定されるワイヤを特に配置しなくてもよい。この場合、チップ側ボンディング用電極６Ｆ及び基板側ボンディング用電極２Ｆは不要になる。   In the present embodiment, the example in which the wires 7C and 7F that are fixed to the reference potential are arranged has been described. However, since the power flowing through the input wire 7E and the power flowing through the output wire 7D are substantially the same, The potential is fixed at the reference potential between the output wire 7D connected to the drain terminal (output unit) of the amplifying unit PW1 and the input wire 7E connected to the gate terminal (input unit) of the subsequent amplifying unit PW2. There is no need to arrange the wire to be used. In this case, the chip-side bonding electrode 6F and the substrate-side bonding electrode 2F are not necessary.

また、本実施形態では、基板側入力用電極２Ａを、半導体チップ５の一辺５Ｘからの距離が基板側出力用電極２Ｂとほぼ同一となる位置に配置した例について説明したが、基板側入力用電極２Ａは基板側ボンディング用電極２Ｃよりも半導体チップ５の一辺５Ｘから遠く離れた位置に配置してもよい。この場合においても、前述の実施形態と同様の効果が得られるが、入力用ワイヤ７Ａの長さが長くなるので、高周波特性が若干劣化する。   In this embodiment, the substrate side input electrode 2A has been described as being disposed at a position where the distance from the side 5X of the semiconductor chip 5 is substantially the same as the substrate side output electrode 2B. The electrode 2A may be arranged at a position farther from one side 5X of the semiconductor chip 5 than the substrate-side bonding electrode 2C. Even in this case, the same effect as that of the above-described embodiment can be obtained, but the length of the input wire 7A becomes long, so that the high frequency characteristics are slightly deteriorated.

（実施形態２）
図８は、本発明の実施形態２である高周波電力増幅器の配線基板の要部平面図である。 (Embodiment 2)
FIG. 8 is a plan view of an essential part of the wiring board of the high frequency power amplifier according to the second embodiment of the present invention.

本実施形態の高周波電力増幅器は、前述の実施形態１と基本的に同様の構成になっており、以下の構成が異なっている。   The high-frequency power amplifier according to the present embodiment has basically the same configuration as that of the first embodiment described above, and the following configuration is different.

即ち、図８に示すように、基板側ボンディング用電極２Ｃに半導体チップ５の第３領域５Ｃ上を延在するワイヤ７Ｇの一端側が電気的にかつ機械的に接続され、基板側ボンディング用電極２Ｆにワイヤ７Ｇの他端側が電気的にかつ機械的に接続されている。基板側ボンディング用電極２Ｃ及び基板側ボンディング用電極２Ｆは基準電位用外部端子４と電気的に接続されているので、ワイヤ７Ｇは基準電位に電位固定される。   That is, as shown in FIG. 8, one end side of the wire 7G extending on the third region 5C of the semiconductor chip 5 is electrically and mechanically connected to the substrate-side bonding electrode 2C, and the substrate-side bonding electrode 2F The other end of the wire 7G is electrically and mechanically connected. Since the substrate-side bonding electrode 2C and the substrate-side bonding electrode 2F are electrically connected to the reference potential external terminal 4, the wire 7G is fixed at the reference potential.

このように、基板側ボンディング用電極２Ｃにワイヤ７の一端側を接続し、基板側ボンディング用電極２Ｆにワイヤ７Ｇの他端側を接続することにより、入力用ワイヤ７Ａと出力用ワイヤ７Ｂとの相互誘導作用による高周波特性の劣化、及び出力用ワイヤ７Ｄと入力用ワイヤ７Ｅとの相互誘導作用による高周波特性の劣化を防止することができる。   Thus, by connecting one end side of the wire 7 to the substrate-side bonding electrode 2C and connecting the other end side of the wire 7G to the substrate-side bonding electrode 2F, the input wire 7A and the output wire 7B are connected. It is possible to prevent the deterioration of the high frequency characteristics due to the mutual induction action and the deterioration of the high frequency characteristics due to the mutual induction action between the output wire 7D and the input wire 7E.

（実施形態３）
図９は、本発明の実施形態３である高周波電力増幅器の配線基板の要部平面図である。 (Embodiment 3)
FIG. 9 is a plan view of an essential part of the wiring board of the high frequency power amplifier according to the third embodiment of the present invention.

本実施形態の高周波電極増幅器は、前述の実施形態１と基本的に同様の構成になっており、以下の構成が異なっている。   The high-frequency electrode amplifier of the present embodiment has basically the same configuration as that of the first embodiment described above, and the following configuration is different.

即ち、図９に示すように、増幅手段ＰＷ１、ＰＷ２及びＰＷ３が一つの半導体チップ５に形成されている。ＰＷ３は半導体チップ５の一主面の第４領域５Ｄに形成されている。   That is, as shown in FIG. 9, amplifying means PW1, PW2, and PW3 are formed on one semiconductor chip 5. PW3 is formed in the fourth region 5D on one main surface of the semiconductor chip 5.

増幅手段ＰＷ３のゲート端子（入力部）は、半導体チップ５の一主面の第４領域５Ｄに形成され、半導体チップ５の一辺５Ｘ側（本実施形態においては一長辺側）に配置されたチップ側入力用電極６Ｈと電気的に接続されている。また、増幅手段ＰＷ３のドレイン端子（出力部）は、半導体チップ５の一主面の第４領域５Ｄに形成され、半導体チップ５の一辺５Ｘと対向する他の辺５Ｙ側（本実施形態においては他の長辺側）に配置されたチップ側出力用電極６Ｋと電気的に接続されている。また、増幅手段ＰＷ３のソース端子は、増幅手段ＰＷ１と同様に、半導体チップ５の裏面に形成された裏面電極２１と電気的に接続されている。   The gate terminal (input part) of the amplifying unit PW3 is formed in the fourth region 5D on one main surface of the semiconductor chip 5, and is arranged on one side 5X side (one long side side in the present embodiment) of the semiconductor chip 5. It is electrically connected to the chip side input electrode 6H. Further, the drain terminal (output portion) of the amplifying unit PW3 is formed in the fourth region 5D on one main surface of the semiconductor chip 5, and is on the other side 5Y side (in this embodiment) facing the one side 5X of the semiconductor chip 5. It is electrically connected to the chip-side output electrode 6K disposed on the other long side. Further, the source terminal of the amplifying unit PW3 is electrically connected to the back surface electrode 21 formed on the back surface of the semiconductor chip 5, similarly to the amplifying unit PW1.

半導体チップ５の一主面の第２領域５Ｂと第４領域５Ｄとの間には、これらの領域間を電気的に分離するための第５領域（アイソレーション領域）５Ｅが形成されている。   Between the second region 5B and the fourth region 5D on one main surface of the semiconductor chip 5, a fifth region (isolation region) 5E for electrically separating these regions is formed.

チップ側入力用電極６Ｈは、半導体チップ５の一辺５Ｘと向かい合うようにして配線基板１の一主面に形成された基板側入力用電極２Ｈと入力用ワイヤ７Ｈを介して電気的に接続されている。基板側入力用電極２Ｈは、その直下に形成されたスルーホール配線３及び内部配線を介して、基板側出力用電極２Ｂと電気的に接続されている。   The chip-side input electrode 6H is electrically connected to the substrate-side input electrode 2H formed on one main surface of the wiring substrate 1 so as to face one side 5X of the semiconductor chip 5 via the input wire 7H. Yes. The substrate-side input electrode 2H is electrically connected to the substrate-side output electrode 2B via a through-hole wiring 3 and an internal wiring formed immediately below the substrate-side input electrode 2H.

チップ側出力用電極６Ｋは、半導体チップ５の他の辺５Ｙと向かい合うようにして配線基板１の一主面に形成された基板側出力用電極２Ｋと出力用ワイヤ７Ｋを介して電気的に接続されている。基板側出力用電極２Ｋは、その直下に形成されたスルーホール配線３及び内部配線を介して、配線基板１の裏面に形成された出力用外部端子と電気的に接続されている。   The chip-side output electrode 6K is electrically connected to the substrate-side output electrode 2K formed on one main surface of the wiring substrate 1 so as to face the other side 5Y of the semiconductor chip 5 via the output wire 7K. Has been. The substrate-side output electrode 2K is electrically connected to an output external terminal formed on the back surface of the wiring substrate 1 through a through-hole wiring 3 and an internal wiring formed immediately below the electrode.

配線基板１の一主面には、半導体チップ５の一辺５Ｘと向かい合うようにして基板側ボンディング用電極２Ｊが形成され、半導体チップ５の他の辺５Ｙと向かい合うようにして基板側ボンディング用電極２Ｌが形成されている。基板側ボンディング用電極２Ｊ及び２Ｌは、基板側ボンディング用電極２Ｃと同様に、配線基板１の裏面に形成された基準電位用端子４と電気的に接続されている。   A substrate-side bonding electrode 2J is formed on one main surface of the wiring substrate 1 so as to face one side 5X of the semiconductor chip 5, and a substrate-side bonding electrode 2L so as to face the other side 5Y of the semiconductor chip 5. Is formed. The substrate-side bonding electrodes 2J and 2L are electrically connected to a reference potential terminal 4 formed on the back surface of the wiring substrate 1, similarly to the substrate-side bonding electrode 2C.

基板側ボンディング用電極２Ｊは、半導体チップ５の一辺５Ｘからの距離が基板側ボンディング用電極２Ｃとほぼ同一となる位置に配置され、基板側ボンディング用電極２Ｌは、半導体チップ５の他の辺５Ｙからの距離が基板側ボンディング用電極２Ｆとほぼ同一となる位置に配置されている。   The substrate-side bonding electrode 2J is disposed at a position where the distance from one side 5X of the semiconductor chip 5 is substantially the same as the substrate-side bonding electrode 2C, and the substrate-side bonding electrode 2L is the other side 5Y of the semiconductor chip 5. Is disposed at a position where the distance from is substantially the same as the substrate-side bonding electrode 2F.

基板側ボンディング用電極２Ｊには半導体チップ５の第５領域５Ｅ上を延在するワイヤ７Ｌの一端側が電気的にかつ機械的に接続され、基板側ボンディング用電極２Ｌにはワイヤ７Ｌの他端側が電気的にかつ機械的に接続されている。   One end of a wire 7L extending over the fifth region 5E of the semiconductor chip 5 is electrically and mechanically connected to the substrate-side bonding electrode 2J, and the other end of the wire 7L is connected to the substrate-side bonding electrode 2L. Electrically and mechanically connected.

本実施形態の高周波電力増幅器において、ワイヤ７Ｌは２本配置されている。入力用ワイヤ７Ｅを流れる電力と出力用ワイヤ７Ｋを流れる電力との差は、入力用ワイヤ７Ａを流れる電力と出力用ワイヤ７Ｂを流れる電力との差よりも大きい。従って、本実施形態のように、電力差に応じて基準電位に電位固定されるワイヤの本数を増加することにより、入力用ワイヤと出力用ワイヤとの相互誘導作用による高周波特性の劣化をより安定した状態で防止することができる。   In the high frequency power amplifier according to this embodiment, two wires 7L are arranged. The difference between the power flowing through the input wire 7E and the power flowing through the output wire 7K is larger than the difference between the power flowing through the input wire 7A and the power flowing through the output wire 7B. Therefore, as in this embodiment, by increasing the number of wires whose potential is fixed to the reference potential according to the power difference, the deterioration of the high frequency characteristics due to the mutual induction action between the input wire and the output wire is more stable. Can be prevented.

（実施形態４）
図１０は、本発明の実施形態４である高周波電力増幅器の配線基板の要部平面図である。 (Embodiment 4)
FIG. 10 is a plan view of the main part of the wiring board of the high-frequency power amplifier according to Embodiment 4 of the present invention.

本実施形態の高周波電力増幅器は、前述の実施形態１と基本的に同様の構成になっており、以下の構成が異なっている。   The high-frequency power amplifier according to the present embodiment has basically the same configuration as that of the first embodiment described above, and the following configuration is different.

即ち、図１０に示すように、基板側出力用電極２Ｂが半導体チップ５の一辺５Ｘと向かい合う位置に配置され、基板側入力用電極２Ａが半導体チップ５の一辺５Ｘに対して交わる他の辺５Ｐと向い合う位置に配置されている。   That is, as shown in FIG. 10, the substrate-side output electrode 2B is disposed at a position facing the one side 5X of the semiconductor chip 5, and the other side 5P where the substrate-side input electrode 2A intersects the one side 5X of the semiconductor chip 5 is provided. It is arranged at the position facing.

このように、基板側出力用電極２Ｂを半導体チップ５の一辺５Ｘと向かい合う位置に配置し、基板側入力用電極２Ａが半導体チップ５の一辺５Ｘに対して交わる他の辺５Ｐと向い合う位置に配置することにより、入力用ワイヤ７Ａと出力用ワイヤ７Ｂとの磁束が直交する状態になるので、このワイヤ間における相互誘導作用を抑制することができる。   In this way, the substrate-side output electrode 2B is disposed at a position facing the one side 5X of the semiconductor chip 5, and the substrate-side input electrode 2A is disposed at a position facing the other side 5P intersecting the one side 5X of the semiconductor chip 5. By arranging, the magnetic fluxes of the input wire 7A and the output wire 7B are orthogonal to each other, so that the mutual induction action between the wires can be suppressed.

また、基準電位に電位固定されるワイヤを接続するための基板側ボンディング用電極を設ける必要がないので、半導体チップ５の第１領域５Ａと第２領域５Ｂとの間隔を狭くすることができ、半導体チップ５の占有面積を縮小することができる。この結果、高周波電力増幅器の小型化を図ることができる。   In addition, since it is not necessary to provide a substrate-side bonding electrode for connecting a wire whose potential is fixed to the reference potential, the interval between the first region 5A and the second region 5B of the semiconductor chip 5 can be reduced, The occupied area of the semiconductor chip 5 can be reduced. As a result, the high-frequency power amplifier can be reduced in size.

以上、本発明者によってなされた発明を、前記実施形態に基づき具体的に説明したが、本発明は、前記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の実施形態１である高周波電力増幅器の外観構成を示す斜視図である。1 is a perspective view showing an external configuration of a high-frequency power amplifier that is Embodiment 1 of the present invention. 前記高周波電力増幅器の等価回路図である。It is an equivalent circuit diagram of the high frequency power amplifier. 図２に示す一点鎖線で囲まれた部分と対応する配線基板の要部平面図である。It is a principal part top view of the wiring board corresponding to the part enclosed with the dashed-dotted line shown in FIG. 図３の要部斜視図である。It is a principal part perspective view of FIG. 図３の要部拡大平面図である。It is a principal part enlarged plan view of FIG. 前記高周波電力増幅器に組み込まれた半導体チップのトランジスタ形成領域における要部断面図である。It is principal part sectional drawing in the transistor formation area of the semiconductor chip integrated in the said high frequency power amplifier. 前記半導体チップのアイソレーション領域における要部断面図である。It is principal part sectional drawing in the isolation area | region of the said semiconductor chip. 本発明の実施形態２である高周波電力増幅器の配線基板の要部平面図である。It is a principal part top view of the wiring board of the high frequency power amplifier which is Embodiment 2 of this invention. 本発明の実施形態３である高周波電力増幅器の配線基板の要部平面図である。It is a principal part top view of the wiring board of the high frequency power amplifier which is Embodiment 3 of this invention. 本発明の実施形態４である高周波電力増幅器の配線基板の要部平面図である。It is a principal part top view of the wiring board of the high frequency power amplifier which is Embodiment 4 of this invention.

符号の説明Explanation of symbols

１…配線基板、１Ａ…凹部、１Ｂ…導電プレート、２Ａ，２Ｄ…基板側入力用電極、２Ｂ，２Ｅ…基板側出力用電極、２Ｃ，２Ｆ…基板側ボンディング用電極、３…スルーホール配線、４…基準電位用外部端子、５…半導体チップ、５Ａ…第１領域、５Ｂ…第２領域、５Ｃ…第３領域（アイソレーション領域）、６Ａ，６Ｅ…チップ側入力用電極、６Ｂ，６Ｄ…チップ側出力用電極、６Ｃ，６Ｆ…チップ側ボンディング用電極、７Ａ，７Ｅ…入力用ワイヤ、７Ｂ，７Ｄ…出力用ワイヤ、７Ｃ，７Ｆ…ワイヤ、Ｃ１〜Ｃ１１…容量素子、Ｒ１〜Ｒ４…抵抗素子、ＳＴＬ１〜ＳＴＬ３…マイクロストリップ線路、ＰＷ１，ＰＷ２，ＰＷ３…増幅手段。   DESCRIPTION OF SYMBOLS 1 ... Wiring board, 1A ... Concave, 1B ... Conductive plate, 2A, 2D ... Substrate side input electrode, 2B, 2E ... Substrate side output electrode, 2C, 2F ... Substrate side bonding electrode, 3 ... Through-hole wiring, 4 ... external terminal for reference potential, 5 ... semiconductor chip, 5A ... first region, 5B ... second region, 5C ... third region (isolation region), 6A, 6E ... chip side input electrodes, 6B, 6D ... Chip side output electrode, 6C, 6F ... Chip side bonding electrode, 7A, 7E ... Input wire, 7B, 7D ... Output wire, 7C, 7F ... Wire, C1-C11 ... Capacitance element, R1-R4 ... Resistance Elements, STL1 to STL3, microstrip lines, PW1, PW2, PW3, amplifying means.

Claims (5)

平面が四辺形状で形成された半導体チップと、
第１面と前記第１面に対向する第２面とを有し、前記第１面側に前記半導体チップが搭載された基板と、
前記半導体チップの第１面の第１領域に形成され、前記半導体チップの一辺側に配置された第１電極と、
前記第１領域に形成され、入力部が前記第１電極と電気的に接続された第１増幅手段と、
前記半導体チップの前記第１面の前記第１領域とは異なる第２領域に形成され、前記半導体チップの前記一辺側に配置された第２電極と、
前記第２領域に形成され、出力部が前記第２電極と電気的に接続された第２増幅手段と、
前記半導体チップの前記第１面の前記第１領域と前記第２領域との間の第３領域に形成された第３電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、第１ワイヤを介して前記第１電極と電気的に接続された第４電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、第２ワイヤを介して前記第２電極と電気的に接続された第５電極と、
前記半導体チップの前記一辺と向かい合うようにして前記基板の前記第１面に形成され、基準電位に電位固定される第３ワイヤを介して前記第３電極と電気的に接続された第６電極とを有し、
前記第６電極と前記半導体チップの前記一辺との間の距離は、前記第５電極と前記半導体チップの前記一辺との間の距離よりも大きいことを特徴とする半導体装置。 A semiconductor chip whose plane is formed in a quadrilateral shape;
A substrate having a first surface and a second surface opposite to the first surface, wherein the semiconductor chip is mounted on the first surface side;
A first electrode formed in a first region of the first surface of the semiconductor chip and disposed on one side of the semiconductor chip;
A first amplifying means formed in the first region and having an input portion electrically connected to the first electrode;
A second electrode formed in a second region different from the first region of the first surface of the semiconductor chip and disposed on the one side of the semiconductor chip;
A second amplifying means formed in the second region and having an output part electrically connected to the second electrode;
A third electrode formed in a third region between the first region and the second region of the first surface of the semiconductor chip;
A fourth electrode formed on the first surface of the substrate so as to face the one side of the semiconductor chip and electrically connected to the first electrode via a first wire;
A fifth electrode formed on the first surface of the substrate so as to face the one side of the semiconductor chip and electrically connected to the second electrode through a second wire;
A sixth electrode formed on the first surface of the substrate so as to face the one side of the semiconductor chip and electrically connected to the third electrode via a third wire fixed at a reference potential; Have
A distance between the sixth electrode and the one side of the semiconductor chip is larger than a distance between the fifth electrode and the one side of the semiconductor chip. 請求項１に記載の半導体装置において、
前記第４電極は、前記半導体チップの前記一辺からの距離が前記第５電極とほぼ同一となる位置に配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the fourth electrode is disposed at a position where the distance from the one side of the semiconductor chip is substantially the same as the fifth electrode. 請求項１に記載の半導体装置において、
前記第４電極と前記半導体チップの前記一辺との間の距離は、前記第６電極と前記半導体チップの前記一辺との間の距離よりも大きいことを特徴とする半導体装置。 The semiconductor device according to claim 1,
A distance between the fourth electrode and the one side of the semiconductor chip is larger than a distance between the sixth electrode and the one side of the semiconductor chip. 請求項１乃至請求項３のうち何れか１項に記載の半導体装置において、
前記第２増幅手段の入力部は、前記第１増幅手段の出力部と電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein:
The semiconductor device according to claim 1, wherein an input section of the second amplifying means is electrically connected to an output section of the first amplifying means. 請求項１乃至請求項４のうち何れか１項に記載の半導体装置において、
前記第４電極に入力された信号は、前記第１及び前記第２増幅手段を介して増幅され、前記第５電極から出力されることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 4,
A signal input to the fourth electrode is amplified through the first and second amplifying means and output from the fifth electrode.
JP2006339318A 2006-12-18 2006-12-18 Semiconductor device Pending JP2007074001A (en)

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