JP2008227221A - Heterojunction bipolar transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction bipolar transistor capable of providing a base electrode having a satisfactory contact characteristic in a good reproducible manner, and to provide its manufacturing method. <P>SOLUTION: The heterojunction bipolar transistor of this invention comprises an n<SP>-</SP>-type InGaAs/InAlGaAs/InP collector layer 3, a p<SP>+</SP>-type InGaAs base layer 4, and an n-type InP emitter layer 5 sequentially deposited on a semi-insulating InP substrate 1. Furhter, The n-type InP emitter layer 5 comprises an InP ledge layer structure 7, a base electrode 10 comprises an internal base electrode 12 and an external base electrode 13. The internal base electrode 12 regulates the outer circumferential part of a collector mesa region in a self-alignment manner to contact with the InP ledge structure 7. A part of the external base electrode 13 is formed on the internal base electrode 12, and the remaing part of the external base electrode 13 is formed on an embedded layer 14 formed out of the collector mesa region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a heterojunction bipolar transistor (hereinafter referred to as HBT) that is useful in realizing an ultrahigh-speed integrated circuit.

  In order to improve the high-frequency performance of the HBT, it is important to reduce the base resistance and the collector capacitance. Conventionally, as one technique for reducing the collector capacitance, a technique has been proposed in which a part of the collector layer under the base electrode is replaced with an insulating material having a low dielectric constant. As the simplest method for realizing this, there is a method in which side etching is performed at the time of forming the collector mesa region and an undercut structure is formed under the base electrode.

FIG. 12 is a cross-sectional view of a conventional HBT. FIG. 12 shows an example of an HBT manufactured using the above-described technique for forming an undercut structure. In FIG. 12, 1 is a semi-insulating InP substrate, 2 is an N ⁺ type InGaAs / InP subcollector layer formed from InGaAs and InP, and 3 is an N ⁻ type InGaAs / InAlGaAs / InP formed from InGaAs, InAlGaAs, and InP. The collector layer, 4 is a P ⁺ -type InGaAs base layer, 5 is an N-type InP emitter layer, 6 is a P ⁻ -type InGaAs emitter cap layer, 9 is a collector electrode, 10 is a base electrode, and 11 is an emitter electrode. Reference numeral 7 denotes an InP ledge layer structure for suppressing a recombination current in the peripheral portion of the emitter mesa structure, and reference numeral 8 denotes an insulating protective film for protecting the surface of the InP ledge layer structure 7. As the insulating protective film 8, a silicon nitride film, a silicon oxide film, or the like is used. Further, reference numeral 15 denotes an insulating protective film for protecting the entire HBT, and BCB (benzocyclobutylene), polyimide, or the like is used.

  In the conventional HBT shown in FIG. 12, after forming the emitter electrode 11, forming the emitter mesa structure, forming the base electrode 10, forming the collector mesa region, forming the collector electrode 9, and forming the inter-element isolation mesa, This is realized by spin-coating the insulating protective film 15. If side etching is performed when forming the collector mesa region, the undercut structure 16 is formed, and the insulating protective film 15 having a low dielectric constant is embedded in the undercut structure 16, thereby reducing the collector capacitance.

It can be said that the above-described method of reducing the collector capacity by forming the undercut structure 16 can be implemented relatively easily. However, since the amount of side etching cannot be monitored during the process, it has a drawback that it is difficult to realize the undercut structure 16 having an intended dimension with high accuracy. For example, if the side etching amount becomes larger than intended, the contact area between the surface of the P ⁺ -type InGaAs base layer 4 and the base electrode 10 is remarkably reduced. The electrode 10 itself may even peel off. For this reason, the amount of side etching cannot be increased unnecessarily, and it is difficult to significantly reduce the collector capacity.

Therefore, as a technique for overcoming the above drawbacks, a technique has been proposed in which the collector mesa region is formed, the outside of the collector mesa region is filled with an insulator having a low dielectric constant, and then the base electrode is formed (see Non-Patent Document 1). . Since the base electrode is formed over the semiconductor base layer and the embedded insulator, there is no need to worry about mechanical strength. Basically, the collector capacitance depends on the pattern size of the etching mask used when forming the collector mesa region, and is not affected by the size of the base electrode or the formation process. FIG. 13 is a cross-sectional view of another conventional HBT. FIG. 13 shows an example of an HBT manufactured using a technique of embedding with an insulator outside the collector mesa region. In addition, the same number is attached | subjected to the structure similar to HBT shown in FIG. 12, and description is abbreviate | omitted. In FIG. 13, reference numeral 14 denotes a buried layer which is an insulator buried outside the collector mesa region. The buried layer 14 is made of an insulating material such as silicon oxide, BCB, or polyimide. As can be seen from FIG. 13, the base electrode 10 is formed on the P ⁺ -type InGaAs base layer 4 and the buried layer 14, and basically the collector mesa region area depends on the size and shape of the base electrode 10. Absent.

14 to 21 are cross-sectional views showing manufacturing steps for realizing the HBT shown in FIG. Hereinafter, an example of a manufacturing process for manufacturing the HBT shown in FIG. 13 will be described. First, as shown in FIG. 14, a metal such as W is deposited on the HBT epitaxial substrate by sputtering to form the emitter electrode 11. Next, as shown in FIG. 15, a photoresist mask for forming the emitter mesa structure is formed, and N-type is used by inductively coupled plasma reactive ion etching (hereinafter referred to as ICP-RIE). Etching is performed halfway through the InP emitter layer 5, and then the photoresist mask is removed. Here, the reason for leaving a part of the N-type InP emitter layer 5 is to protect the base layer interface until just before the base electrode 10 is formed by not exposing the surface of the P ⁺ -type InGaAs base layer 4. Another reason is that the remaining N-type InP emitter layer 5 is used to form an InP ledge layer structure 7 to suppress recombination current in the periphery of the emitter mesa structure. Next, as shown in FIG. 16, a photoresist mask 18 is formed in order to form a collector mesa region, and the remaining N-type InP emitter layer 5, P ⁺ -type InGaAs base layer 4 and ICP-RIE method are formed. The N ⁻ type InGaAs / InAlGaAs / InP collector layer 3 is continuously removed. (By the way, Non-Patent Document 1 employs a technique in which a thick side wall (Sidewall) made of a silicon oxide film is formed in the emitter mesa structure and used as an etching mask.)
Next, as shown in FIG. 17, after the collector mesa region is formed, a buried layer 14 such as silicon oxide having a dielectric constant lower than that of the semiconductor is buried outside the collector mesa region. As a technique for realizing this, there is a technique in which the buried layer 14 is deposited by the sputtering method with the photoresist mask 18 shown in FIG. 16 left, and then the photoresist mask 18 is lifted off. As another technique, there is a technique in which the buried layer 14 is deposited after removing the photoresist mask 18 shown in FIG. 16, and only the buried layer 14 corresponding to the collector mesa region is selectively etched away. Alternatively, there is a method of cueing the collector mesa region by depositing the buried layer 14 thick and planarizing it, and then etching back the entire wafer surface. After that, if the base electrode 10 is formed after embedding the buried layer 14 such as silicon oxide, a desired mesa structure can be obtained. Before that, electrical insulation between the emitter mesa structure and the base electrode 10 is ensured. In order to do so, an insulating protective film 8 is formed. Note that a silicon nitride film, a silicon oxide film, or the like is used as the insulating protective film 8, but which insulating material is used depends on a method of forming the base electrode 10 and the like. Then, a photoresist mask 17 is formed so as to include the emitter mesa structure, and the insulating protective film 8 is selectively removed by a reactive ion etching (hereinafter referred to as RIE) method. (In Non-Patent Document 1, electrical insulation from the base electrode 10 is ensured by forming a thin sidewall made of a silicon oxide film in the emitter mesa structure.)
Then, as shown in FIG. 18, by using the remaining insulating protective film 8 as a mask, the N-type InP emitter layer 5 is removed and the surface of the P ⁺ -type InGaAs base layer 4 is exposed. Can be formed. Incidentally, the insulating protective film 8 also plays a role of protecting and stabilizing the surface of the InP ledge layer structure 7. Next, as shown in FIG. 19, the photoresist mask 17 is removed, and the base electrode 10 made of Pt / W or Ti / W is deposited by vapor deposition or sputtering. Here, Pt and Ti are used for improving the contact characteristics with the P ⁺ -type InGaAs base layer 4 and may be a thin film of about several nm. On the other hand, the W metal is used to lower the resistance value of the base electrode 10 itself, and needs to be deposited relatively thickly on the order of several hundred nm. Next, as shown in FIG. 20, unnecessary Pt / W or Ti / W on the emitter mesa structure or the like is removed by the RIE method. Then, as shown in FIG. 21, the insulating protective film 8 and the buried layer 14 are opened, and the collector electrode 9 is formed on the N ⁺ type InGaAs / InP subcollector layer 2. Further, if the element isolation mesa is formed and the insulating protective film 15 such as BCB or polyimide is spin-coated, the HBT shown in FIG. 13 can be realized.
T.Oka, K.Hirata, K.Ouchi, H.Uchiyama, K.Mochizuki and T.Nakamura, “Small-Scaled InGaP / GaAs HBT'swith WSi / Ti Base Electrode and Buried SiO2,” IEEE Transactions on Electron Devices, Volume 45, Number 11 November, 1998, pp.2276-2282

  However, by using another conventional HBT manufacturing method described above, the collector mesa region can be formed independently of the formation of the base electrode 10, and the collector mesa region can be further miniaturized. Although the collector capacity can be expected to be greatly reduced, the above manufacturing method requires a base electrode 10 to be formed after a complicated process step, so that a good and uniform base contact characteristic is reproducible. There was a problem that it was difficult to realize well. As a result, there has been a problem that it cannot be denied that there is a risk of difficulty in miniaturizing elements and increasing the scale of integrated circuits.

Hereinafter, the above problem will be described in detail. First, in the above manufacturing method, it is necessary to remove the N-type InP emitter layer 5 by selective wet etching in order to expose the surface of the P ⁺ -type InGaAs base layer 4, but it is determined whether or not the etching is completed. It is very difficult to do. This is because, as can be seen from FIG. 17, the N-type InP emitter layer 5 region to be etched has a dimension of a micron unit. In general, in an InP / InGaAs-based semiconductor, the interference color of a semiconductor film changes depending on the material (in the visible light region), so that the end point determination of selective wet etching can be visually confirmed. However, in the other conventional HBT shown in FIG. 13, it is impossible to visually determine the end point because the etching region has only a micron size. Therefore, it is necessary to obtain the etching rate using a thick film in advance and to perform wet etching after setting an appropriate etching time. However, in fine and complex structures, the etching rate often differs from the value previously determined. For example, the surface of the N-type InP emitter layer 5 may be significantly modified when the insulating protective film 8 is deposited or when the insulating protective film 8 is removed by RIE or the like, and the wet etching rate is high. May change. If attention is paid to the boundary between the collector mesa region and the buried layer 14, damage to the N-type InP emitter layer 5 is unavoidable even when the buried layer 14 is formed, which may change the etching characteristics. Furthermore, in practice, the vicinity of the boundary between the collector mesa region and the buried layer 14 is not flat and has a certain level of difference, which is also a negative factor for the realization of stable wet etching. If the etching rate is lower than expected, there is a risk that a part of the N-type InP emitter layer 5 remains and the contact characteristics of the base electrode 10 are significantly impaired. Conversely, if the etching time is longer than necessary to completely remove the N-type InP emitter layer 5, side etching also enters the InP ledge layer structure 7 under the insulating protective film 8, and the InP ledge layer structure 7 The width will be reduced. In this case, the function of the InP ledge layer structure 7 is deteriorated, and the recombination current in the peripheral portion of the emitter mesa structure cannot be sufficiently suppressed, resulting in deterioration of current gain. If the width of the InP ledge layer structure 7 is set to be wide in advance, the ledge function can be prevented from remarkably deteriorating even if side etching is excessive. However, this enlarges the collector mesa area, and this has a negative effect on the original purpose of reducing the collector capacity. Further, there is a risk that excessive etching may erode the boundary between the collector mesa region and the buried layer 14. From the above, in the other conventional HBT shown in FIG. 13, it is difficult to expose the surface of the P ⁺ -type InGaAs base layer 4 with good controllability, and good base contact characteristics can be realized with good reproducibility. It becomes difficult.

  Further, as can be seen by comparing FIG. 19 and FIG. 20, it is necessary to remove the base electrode 10 on the emitter mesa structure. However, it is expected that the etching conditions for the cueing of the emitter mesa structure will become stricter as the emitter becomes finer. In the other conventional HBT shown in FIG. 13, it is necessary to determine conditions with higher accuracy, and there is a concern that the process difficulty level rapidly increases with the miniaturization of elements. As a result, there has been a problem that it cannot be denied that there is a risk of difficulty in miniaturizing elements and increasing the scale of integrated circuits.

  The present invention has been made in view of these problems, and an object thereof is to provide a heterojunction bipolar transistor capable of realizing a base electrode having good contact characteristics with good reproducibility and a method for manufacturing the same.

  To achieve the above object, in the heterojunction bipolar transistor according to the present invention, in the heterojunction bipolar transistor in which a collector layer, a base layer, and an emitter layer are sequentially stacked on a semiconductor substrate, the emitter layer has a ledge layer structure. The base electrode is composed of a first base electrode and a second base electrode, and the first base electrode is in contact with the ledge layer structure while defining the outer periphery of the collector mesa region in a self-aligning manner. And a part of the second base electrode is formed on the first base electrode, and a remaining part of the second base electrode is formed on the insulator formed outside the collector mesa region. It is characterized by being formed.

  According to a second aspect of the present invention, in the heterojunction bipolar transistor according to the first aspect of the present invention, the material forming the emitter layer is any one of InP, InAlP, InGaP, InGaAsP, InAlAs, and InAlGaAs. It is characterized by being.

  According to a third aspect of the present invention, in the heterojunction bipolar transistor according to the first or second aspect of the present invention, the material forming the base layer is InGaAs, InGaAsP, InAlGaAs, GaAsSb, InGaAsSb. Or AlGaAsSb.

  Further, as described in claim 4, in the heterojunction bipolar transistor according to the present invention described in any one of claims 1 to 3, the material forming the insulator is silicon oxide, BCB (benzocycle), It is characterized by being one of polyimides.

  Further, in the heterojunction bipolar transistor according to the present invention as set forth in claim 5, the material forming the first base electrode forms the base layer. It includes a first metal that forms an ohmic contact with the material, and a second metal that forms a Schottky contact with the material forming the emitter layer.

  According to a sixth aspect of the present invention, in the heterojunction bipolar transistor according to the fifth aspect of the present invention, the first metal does not contact the emitter layer.

  According to a seventh aspect of the present invention, in the heterojunction bipolar transistor according to the fifth or sixth aspect of the present invention, the second metal is in contact with the emitter layer.

  In addition, as described in claim 8, in the heterojunction bipolar transistor according to any of claims 5 to 7, the second metal is W or WSi.

  According to a ninth aspect of the present invention, in the method of manufacturing a heterojunction bipolar transistor according to the first aspect of the present invention, the emitter mesa structure formed by etching partway through the emitter layer is provided. Depositing an insulating protective film on the insulating protective film; forming a first etching mask including the emitter mesa structure on the insulating protective film; and selectively etching the insulating protective film; Using the insulating protective film as an etching mask, the emitter layer is etched away to form a ledge layer structure and exposing the surface of the base layer, and the first etching mask remains Then, the material for forming the first base electrode is deposited by vapor deposition or sputtering, and thereafter, the material is formed by using the lift-off method. Removing the first etching mask to leave a material for forming the first base electrode in contact with the side wall of the ledge layer on the surface of the base layer; and a second etching mask including the emitter mesa structure Forming the collector mesa region in a self-aligned manner with respect to the first base electrode by sequentially etching the material forming the first base electrode, the base layer, and the collector layer using A step of forming the insulator outside the collector mesa region so as to be in contact with a side wall of the collector mesa region, and a step of forming the second base electrode on the first base electrode and the insulator. It is characterized by including.

  In the heterojunction bipolar transistor according to the present invention, the base electrode is formed outside the collector mesa region and the first base electrode that contacts the ledge layer structure of the emitter layer while defining the outer peripheral portion of the collector mesa region in a self-aligned manner. Since the second base electrode is formed on the insulator and the first base electrode, a base electrode having good contact characteristics can be realized with good reproducibility.

A heterojunction bipolar transistor (hereinafter referred to as HBT) according to an embodiment of the present invention and a manufacturing method thereof will be described below with reference to FIGS. FIG. 1 is a sectional view of an NPN InP / InGaAs HBT according to an embodiment of the present invention. In FIG. 1, 1 is a semi-insulating InP substrate which is a semiconductor substrate, 2 is an N ⁺ type InGaAs / InP subcollector layer formed of N type high concentration (hereinafter referred to as N ⁺ type) InGaAs and InP, 3 is an N ⁻ type InGaAs / InAlGaAs / InP collector layer formed of N type low concentration (hereinafter referred to as N ⁻ type) InGaAs, InAlGaAs and InP, and 4 is a P type high concentration (hereinafter referred to as P ⁺ type). P ⁺ type InGaAs base layer formed from InGaAs, 5 is an N type InP emitter layer formed from N type InP, and 6 is a P type low concentration (hereinafter referred to as P ⁻ type) InGaAs. P ^- type InGaAs emitter cap layer to be formed, 9 is a collector electrode, and 11 is an emitter electrode. Reference numeral 7 denotes an InP ledge layer structure for suppressing a recombination current in the peripheral portion of the mesa-type N-type InP emitter layer 5 (hereinafter referred to as emitter mesa), and 8 denotes a surface protecting the InP ledge layer structure 7. Insulating protective film. As the insulating protective film 8, a silicon nitride film, a silicon oxide film, or the like is used. Reference numeral 14 denotes a buried layer which is an insulator buried outside the region of the mesa type N ⁻ -type InGaAs / InAlGaAs / InP collector layer 3 (hereinafter referred to as collector mesa). The buried layer 14 is made of silicon oxide. Reference numeral 15 denotes an insulating protective film for protecting the entire HBT according to the present invention, and BCB (benzocyclobutylene), polyimide, or the like is used.

Here, in the HBT according to the present invention, the base electrode is composed of the internal base electrode 12 that is the first base electrode and the external base electrode 13 that is the second base electrode. The internal base electrode 12 is in contact with the InP ledge layer structure 7 while defining the outer peripheral portion of the collector mesa region in a self-aligning manner. A part of the external base electrode 13 is formed on the internal base electrode 12. On the other hand, the remaining portion of the external base electrode 13 is formed on the buried layer 14. As a result, electrical connection from the wiring to the internal base electrode 12 is performed by the external base electrode 13, and electrical connection from the external base electrode 13 to the P ⁺ -type InGaAs base layer 4 is performed by the internal base electrode 12.

2 to 10 are cross-sectional views showing manufacturing steps for realizing the HBT shown in FIG. Hereinafter, a manufacturing process for realizing the HBT shown in FIG. 1 will be described in detail. First, as shown in FIG. 2, an N ⁺ type InGaAs / InP subcollector layer 2, an N ⁻ type InGaAs / InAlGaAs / InP collector layer 3, a P ⁺ type InGaAs base layer 4, N After depositing the type InP emitter layer 5 and the P ⁻ type InGaAs emitter cap layer 6, a metal such as tungsten (hereinafter referred to as W) is further deposited by sputtering to form the emitter electrode 11. Next, as shown in FIG. 3, a photoresist mask for an emitter mesa structure is formed, and an N-type InP emitter layer is formed using an inductively coupled plasma reactive ion etching (hereinafter referred to as ICP-RIE) method. After etching halfway through 5, the photoresist mask is removed.

Next, as shown in FIG. 4, an insulating protective film 8 such as a silicon nitride film is deposited to a thickness of 150 nm, and then a photoresist serving as a first etching mask is formed on the insulating protective film 8 so as to include the emitter mesa structure. -The mask 17 is formed. Then, the insulating protective film 8 is selectively etched using the photoresist mask 17, and then the N-type InP emitter layer 5 is selectively etched by selective wet etching using the remaining insulating protective film 8 as a mask. To remove. In addition, since the side etching is also included when the insulating protective film 8 is etched, an undercut structure suitable for forming the internal base electrode 12 described later is formed. By performing the above steps, the surface of the P ⁺ -type InGaAs base layer 4 is exposed and the InP ledge layer structure 7 is formed at the same time. Since the selective wet etching region of the N-type InP emitter layer 5 extends over the entire wafer surface, it is possible to visually check the surface of the P ⁺ -type InGaAs base layer 4, and the etching residue and excessive over-etching can be prevented. It is easy to avoid.

Next, with the photoresist mask 17 left, Pt (or Ti), which is the first metal for forming the internal base electrode 12, is deposited by about 5 nm by electron beam evaporation to form the internal base electrode 12. The second metal W is deposited to a thickness of about 20 nm by sputtering. Then, as shown in FIG. 5, the photoresist mask 17 is removed using a lift-off method. As a result, a metal Pt (or Ti) / W layer 19 is left on the surface of the P ⁺ -type InGaAs base layer 4 which is a material for forming the internal base electrode 12 in contact with the ledge layer side wall. Further, since the metal Pt (or Ti) / W forming the internal base electrode 12 is deposited before the P ⁺ -type InGaAs base layer 4 and the N ⁻ -type InGaAs / InAlGaAs / InP collector layer 3 are processed, the P ⁺ -type The surface of the InGaAs base layer 4 is flat at the atomic level, and it is easy to realize ideal contact characteristics. Further, since the Pt (or Ti) / W film thickness is as small as 25 nm as compared with the thickness 150 nm of the insulating protective film 8, the photoresist mask 17 can be easily lifted off.

Here, Pt (or Ti) is used to form an ohmic contact between the internal base electrode 12 and the P ⁺ -type InGaAs base layer 4, that is, to reduce contact resistance. Therefore, the thickness of Pt (or Ti) does not need to be more than a value necessary for improving contact characteristics. On the other hand, W is used to lower the resistance of the internal base electrode 12 itself, and is deposited relatively thick. When the sheet resistance ρ _{S of} W was actually obtained for a prototype HBT by a four-probe measurement method, it was about 16Ω / □. As will be described in detail later, the resistance of the internal base electrode 12 calculated from this value is sufficiently smaller than the total base resistance. Incidentally, the reason why W is used as the material of the internal base electrode 12 is that the resistivity is low and the etching process by the reactive ion etching (hereinafter referred to as RIE) method is easy. Further, since Pt (or Ti) is deposited by an electron beam vapor deposition method with excellent directivity, it does not adhere to the ledge layer side wall due to the undercut structure under the photoresist mask 17. Therefore, an electrical short circuit does not occur between Pt (or Ti) and the InP ledge layer structure 7. On the other hand, when W is deposited by sputtering, W adheres to the side wall portion of the ledge layer, unlike the electron beam evaporation method. However, W forms a Schottky contact with the InP ledge layer structure 7 (not high in doping concentration). Therefore, an electrical short circuit is not caused between the internal base electrode 12 and the InP ledge layer structure 7. Rather, as a result of the Fermi level being pinned, the surface of the ledge layer side wall is electrically stabilized.

Next, as shown in FIG. 6, a photoresist mask 18 which is a second etching mask including an emitter mesa structure is formed to form a collector mesa region, and a metal Pt (or an inner base electrode 12) is formed. The Ti) / W layer 19, the P ⁺ -type InGaAs base layer 4 and the N ⁻ -type InGaAs / InAlGaAs / InP collector layer 3 are partially removed. Here, the second metal W forming the internal base electrode 12 is etched by the RIE method using SF ₆ gas, and the first metal Pt (or Ti), P ⁺ -type InGaAs base layer 4 and N ^The -type InGaAs / InAlGaAs / InP collector layer 3 is etched by an ICP-RIE method using Cl ₂ gas. The remaining N ⁻ -type InGaAs / InAlGaAs / InP collector layer 3 is removed by selective wet etching to expose the surface of the N ⁺ -type InGaAs / InP subcollector layer 2. Through the above steps, the internal base electrode 12 is formed, and at the same time, the collector mesa region is formed in a self-aligned manner with respect to the internal base electrode 12.

Next, as shown in FIG. 7, a buried layer 14 that is an insulator is buried so as to be in contact with the sidewall of the collector mesa region. There are several methods for embedding the buried layer 14 of silicon oxide outside the collector mesa region. Here, the lift-off method actually performed will be described. First, with the photoresist mask 18 left, silicon oxide is deposited to the same height as the internal base electrode 12 by sputtering. Thereafter, the silicon oxide having a weak adhesive force deposited on the sidewall of the photoresist mask 18 is removed by dipping in a hydrogen fluoride (HF) solution diluted with ammonium fluoride (NH ₄ F). Thereafter, as shown in FIG. 8, the photoresist mask 18 is lifted off. Thereby, the embedding of the embedding layer 14 is completed.

Next, as shown in FIG. 9, an external base electrode 13 made of Ti / Pt / Au is deposited in a non-self-aligned manner so as to be in contact with the internal base electrode 12 and the buried layer 14 and lift-off is formed. Here, the thickness of Ti is 30 nm, the thickness of Pt is 20 nm, and the thickness of Au is 300 nm. Since the contact resistance between metals is extremely small, highly accurate alignment is not required for positioning of the external base electrode 13. Here, it should be noted that the external base electrode 13 plays a role of electrical connection from the wiring to the internal base electrode 12. Therefore, unlike the internal base electrode 12, the external base electrode 13 itself is disposed over a relatively long distance. Therefore, in order to reduce the resistance of the external base electrode 13, it is necessary to make the electrode layer thickness sufficiently large, such as about several hundred nm, and to make the sheet resistance of the external base electrode 13 as close to zero as possible. Next, as shown in FIG. 10, after forming the external base electrode 13, the insulating protective film 8 and the buried layer 14 are opened, and the collector electrode 9 is formed on the N ⁺ -type InGaAs / InP subcollector layer 2. If the insulating protective film 15 such as BCB is spin-coated after the element isolation mesa is formed, the HBT according to the present invention shown in FIG. 1 can be realized. Furthermore, if a via hole is formed on the emitter electrode 11, the external base electrode 13 and the collector electrode 9 and a wiring electrode is formed, the HBT element is completed.

The HBT according to the present invention shown in FIG. 1 and the conventional HBT shown in FIG. 12 were prototyped and the high-frequency characteristics were compared using S-parameter measurement. Here, the reason why the conventional HBT shown in FIG. 12 is compared is that the advantage of the buried insulator structure is not lost (for unexpected reasons) even if the manufacturing process according to the present invention is used. This is to confirm that it can be reduced to a minimum. Further, the manufacturing process of the HBT shown in FIG. 12 is simple, and ideal contact characteristics can be easily obtained with respect to the base electrode 10 alone. Therefore, one of the reasons is that it is easy to compare and determine how ideal contact characteristics are obtained in the HBT according to the present invention. The thicknesses of the prototype HBT N-type InP emitter layer 5, P ⁺ -type InGaAs base layer 4 and N ⁻ -type InGaAs / InAlGaAs / InP collector layer 3 are 60 nm, 25 nm, and 80 nm, respectively. The dimensions of the N-type InP emitter layer 5 are a width W _{E of} 0.5 μm, a length L _{E of} 3 μm, and a ledge width W _Ledge of the InP ledge layer structure 7 of 0.2 μm. The internal base electrode 12 has a Pt (or Ti) thickness of 5 nm and a W thickness of 20 nm. Further, the width W _{C of the} collector mesa region is 1.6 μm for the HBT according to the present invention and 2.1 μm for the conventional HBT. Here, the reason why the width W _C of the collector mesa region of the conventional HBT is large is that the side etching amount cannot be increased unnecessarily. In the HBT according to the present invention, the distance _{WBM, in} from the external base electrode 13 to the InP ledge layer structure 7 is about 0.2 μm. Further, as described above, the sheet resistance ρ _S of W of the internal base electrode 12 was 16Ω / □. Therefore, the resistance of the internal base electrode 12 of the HBT according to the present invention is approximately:
_{ρ S × (W BM, in} / L E) × (1/2) = 16 × (0.2 / 3) × (1/2) = 0.5Ω (1)
Calculated as a degree. On the other hand, from the high frequency analysis, a value of about 60Ω is estimated as the total base resistance. From the above results, it can be understood that a sufficiently small electrode resistance can be obtained even with a thin W metal of about 20 nm. Incidentally, the reason why the factor (1/2) exists in the equation (1) is that the internal base electrodes 12 are arranged on both sides of the emitter mesa structure.

FIG. 11 shows high-frequency characteristics of the HBT shown in FIG. 12 and the HBT of the present invention shown in FIG. Top view of FIG. 11 shows a collector current density J _c dependency of current gain cutoff frequency f _t and the maximum oscillation frequency f _max. Also, below shows the collector current density J _c dependence of the total collector capacitance C _bc. The HBT according to the present invention clearly has a smaller total collector capacity _Cbc than the conventional HBT. This is because the effect of reducing the width W _C of the collector mesa region appears, and it can be said that the advantage of the insulator embedded structure is reflected. Further, reduction of the total collector capacitance C _bc, it is seen from the figure that worked to improve the current gain cutoff frequency f _t. Further, regarding the maximum oscillation frequency f _max , the value of the HBT according to the present invention is nearly 30% higher than that of the conventional HBT. This result basically directly suggests that the base resistance of the HBT according to the present invention is equal to or less than the base resistance of the conventional HBT. Incidentally, the total base resistance estimated from the high frequency analysis was about 60Ω for the HBT according to the present invention and about 70Ω for the conventional HBT. The above results demonstrate that by using the present invention, a significant reduction in collector capacitance, which is an advantage of the buried insulator structure, is achieved, and at the same time, extremely good base contact characteristics can be obtained.

As described above, in the manufacturing process of the HBT according to the embodiment of the present invention, the photoresist mask 17 including the emitter mesa structure is formed on the insulating protective film 8, and the insulating protective film 8 is selectively etched and left. Using the insulating protective film 8 as an etching mask, the N-type InP emitter layer 5 is etched away to form an InP ledge layer structure 7 and the surface of the P ⁺ -type InGaAs base layer 4 is exposed. Therefore, the region where the selective wet etching of the N-type InP emitter layer 5 is performed extends over the entire surface of the wafer, so that the surface of the P ⁺ -type InGaAs base layer 4 can be visually confirmed. From this, it is possible to easily avoid etching residue and excessive over-etching. Also, with the photoresist mask 17 left, the first metal Pt (or Ti) forming the internal base electrode 12 is deposited by electron beam evaporation, and the second metal W is deposited by sputtering. Pt (or Ti) forms an ohmic contact with the P ⁺ -type InGaAs base layer 4, and W forms a Schottky contact with the InP ledge layer structure 7, so that the internal base electrode 12 and the InP ledge layer structure 7 It is possible to reduce the resistance of the internal base electrode 12 while preventing an electrical short circuit between them. Rather, as a result of the Fermi level being pinned, the surface of the ledge layer sidewall can be electrically stabilized. Further, since the metal Pt (or Ti) / W forming the internal base electrode 12 is deposited before the P ⁺ type InGaAs base layer 4 and the N ⁻ type InGaAs / InAlGaAs / InP collector layer 3 are processed, the P ⁺ type is deposited. The surface of the InGaAs base layer 4 is flat at the atomic level over the entire wafer surface, and good contact characteristics can be realized. Therefore, a base electrode having good contact characteristics can be realized with good reproducibility.

Further, using a photoresist mask 18 including an emitter mesa structure, the metal Pt (or Ti) / W layer 19, the P ⁺ type InGaAs base layer 4 and the N ⁻ type InGaAs / InAlGaAs / Since the InP collector layer 3 is sequentially etched, the collector mesa region can be formed in a self-aligned manner with respect to the internal base electrode 12. Thereafter, since the buried layer 14 that is an insulator is formed outside the collector mesa region so as to be in contact with the sidewall of the collector mesa region, a significant reduction in collector capacitance, which is an advantage of the insulator buried structure, can be achieved. Furthermore, since the external base electrode 13 is formed on the internal base electrode 12 and the buried layer 14, it is possible to prevent the external base electrode 13 itself from being peeled off due to the stress inherent in the external base electrode 13.

  Furthermore, since the resistance of the internal base electrode 12 itself of the HBT according to the present invention is determined by a very short distance from the external base electrode 13 to the InP ledge layer structure 7, that is, a submicron distance, the internal base electrode Even if the thickness of 12 is reduced to about several tens of nanometers, the resistance of the internal base electrode 12 can be kept sufficiently small. Therefore, the metal Pt (or Ti) / W for forming the internal base electrode 12 can be deposited by using either the vapor deposition method or the sputtering method, and can be easily formed by a simple lift-off method. is there. This feature is useful for simplifying the process steps, and makes it possible to facilitate element miniaturization and circuit enlargement. Furthermore, since both the base resistance and the collector capacitance are determined by the processing accuracy (lithographic exposure accuracy) of the internal base electrode 12 or the collector mesa region, there is also an aspect that the manufacturing process management becomes simple.

  Further, in the HBT of the present invention, since the internal base electrode 12 and the external base electrode 13 are not formed on the emitter mesa structure, it is not necessary to perform etching for the cueing of the emitter mesa structure even when the emitter is miniaturized. It is possible to prevent the process difficulty from rapidly increasing with the miniaturization of elements. From this viewpoint, it is possible to facilitate the miniaturization of elements and the enlargement of integrated circuits.

  The embodiment described above is an example of the implementation of the present invention, and the scope of the present invention is not limited thereto, and other various embodiments are within the scope described in the claims. It is applicable to. For example, the heterojunction bipolar transistor according to the embodiment of the present invention and the method for manufacturing the heterojunction bipolar transistor are applied to an NPN type InP / InGaAs HBT that is promising for realizing a high-speed circuit. However, the present invention is not limited to this. In addition, the present invention can also be applied to an HBT using a GaAsSb-based material, which is a narrow band gap material, for the base layer. Similarly, it can be applied to SiGe-based HBTs. Furthermore, the present invention can also be applied to a PNP type HBT.

  In the HBT according to the present embodiment, the thickness of the first metal Pt (or Ti) of the internal base electrode 12 is 5 nm. However, the thickness is not limited to this, and other thicknesses may be used. However, if the film thickness of Pt (or Ti) is less than 1 nm, good film quality may not be obtained, and it is difficult to control the film thickness. Further, when the film thickness of Pt (or Ti) is thicker than 10 nm, alloying by sintering becomes difficult. Therefore, the film thickness of Pt (or Ti) is desirably 1 nm or more and 10 nm or less.

  In the HBT according to the present embodiment, the thickness of the second metal W of the internal base electrode 12 is 20 nm. However, the thickness is not particularly limited to this, and other thicknesses may be used. However, if the film thickness of W is less than 10 nm, the resistance value increases. Further, when the film thickness of W is greater than 100 nm, lift-off becomes difficult. Therefore, the film thickness of W is desirably 10 nm or more and 100 nm or less.

  In the HBT according to the present embodiment, Pt (or Ti) is used as the first metal of the internal base electrode 12, but the present invention is not particularly limited thereto, and palladium may be used. Similarly, although W is used as the second metal, the present invention is not particularly limited thereto, and WSi may be used.

  In the HBT according to the present embodiment, when the first metal Pt (or Ti) forming the internal base electrode 12 is deposited with the photoresist mask 17 left, a directional electron beam evaporation method is used. However, the present invention is not limited to this, and other methods such as sputtering may be used. In this case, Pt (or Ti) may adhere to the side wall of the ledge layer, which may cause a leakage current during the HBT operation, but Pt (or Ti) adheres to the side of the ledge layer. However, the HBT operation is possible as long as the deposited Pt (or Ti) film is thin and the leakage current does not increase. However, as shown in the HBT according to this embodiment, it is desirable that Pt (or Ti) does not adhere to the ledge layer side wall.

  In the HBT according to the present embodiment, the emitter layer is formed of InP. However, the emitter layer is not particularly limited thereto, and may be formed using a semiconductor such as InAlP, InGaP, InGaAsP, InAlAs, or InAlGaAs. good. Similarly, the base layer is made of InGaAs, but is not particularly limited thereto, and may be formed using a semiconductor such as InGaAsP, InAlGaAs, GaAsSb, InGaAsSb, or AlGaAsSb.

  In the HBT according to the present embodiment, silicon oxide is used as the material of the buried layer 14 formed outside the collector mesa region. However, the material is not limited to this, and other insulators such as BCB and polyimide are used. Materials may be used.

It is sectional drawing of the NPN type InP / InGaAs type | system | group HBT which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing process which implement | achieves HBT shown in FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. 13 shows high-frequency characteristics of the HBT shown in FIG. 12 and the HBT of the present invention shown in FIG. It is sectional drawing of the conventional HBT. It is sectional drawing of other conventional HBT. It is sectional drawing which shows the manufacturing process which implement | achieves HBT shown in FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG. It is sectional drawing following FIG.

Explanation of symbols

1 semi-insulating InP substrate, 2 N ⁺ type InGaAs / InP subcollector layer,
3 N ⁻ type InGaAs / InAlGaAs / InP collector layer,
4 P ⁺ type InGaAs base layer, 5 N type InP emitter layer,
6 P ⁻ -type InGaAs emitter cap layer, 7 InP ledge layer structure,
8 Insulating protective film, 9 collector electrode, 10 base electrode, 11 emitter electrode,
12 internal base electrode, 13 external base electrode, 14 buried layer,
15 Insulating protective film, 16 Undercut structure,
17 photoresist mask, 18 photoresist mask,
19 Pt (or Ti) / W layer

Claims (9)

In a heterojunction bipolar transistor in which a collector layer, a base layer, and an emitter layer are sequentially stacked on a semiconductor substrate,
The emitter layer has a ledge layer structure,
The base electrode is composed of a first base electrode and a second base electrode,
The first base electrode is in contact with the ledge layer structure while defining the outer periphery of the collector mesa region in a self-aligning manner,
A part of the second base electrode is formed on the first base electrode, and the remaining part of the second base electrode is formed on an insulator formed outside the collector mesa region. A heterojunction bipolar transistor characterized by comprising:   2. The heterojunction bipolar transistor according to claim 1, wherein a material for forming the emitter layer is any one of InP, InAlP, InGaP, InGaAsP, InAlAs, and InAlGaAs.   3. The heterojunction bipolar transistor according to claim 1, wherein the material forming the base layer is any one of InGaAs, InGaAsP, InAlGaAs, GaAsSb, InGaAsSb, and AlGaAsSb.   The heterojunction bipolar transistor according to any one of claims 1 to 3, wherein the material forming the insulator is any one of silicon oxide, BCB (benzocyclobutene), and polyimide.   The material forming the first base electrode is a first metal that forms an ohmic contact with the material that forms the base layer, and a second metal that forms a Schottky contact with the material that forms the emitter layer. The heterojunction bipolar transistor according to claim 1, comprising:   The heterojunction bipolar transistor according to claim 5, wherein the first metal does not contact the emitter layer.   The heterojunction bipolar transistor according to claim 5 or 6, wherein the second metal is in contact with the emitter layer.   The heterojunction bipolar transistor according to any one of claims 5 to 7, wherein the second metal is W or WSi. In the manufacturing method of the heterojunction bipolar transistor according to any one of claims 1 to 8,
Depositing an insulating protective film on an emitter mesa structure formed by etching partway through the emitter layer;
Forming a first etching mask including the emitter mesa structure on the insulating protective film, and then selectively etching the insulating protective film;
Forming the ledge layer structure by etching away the emitter layer using the remaining insulating protective film as an etching mask, and exposing the base layer surface;
The base layer is formed by depositing a material for forming the first base electrode while leaving the first etching mask, and then removing the first etching mask using a lift-off method. Leaving a material for forming the first base electrode in contact with the ledge layer side wall on the surface;
Using the second etching mask including the emitter mesa structure, the material for forming the first base electrode, the base layer, and the collector layer are sequentially etched to thereby form the collector mesa region in the first base. Forming in a self-aligned manner with respect to the electrodes;
Forming the insulator outside the collector mesa region so as to be in contact with a side wall of the collector mesa region;
Forming the second base electrode on the first base electrode and the insulator, and a method for manufacturing a heterojunction bipolar transistor.

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