KR100352375B1 - Method Manufacturing the Heterojunction Bipolar Transistor - Google Patents

Abstract

The present invention relates to a method of fabricating a heterojunction bipolar transistor (Heterojunction Bipolar Transistor: HBT) composed of a compound semiconductor of aluminum gallium arsenide (AlGaAs) / gallium arsenide (GaAs), which inhibits the inherent ultrafast characteristics of HBT. This is to control the recombination current generation at the surface of the extrinsic base.

Such a method for manufacturing a heterojunction dipole transistor according to the present invention includes a first step of manufacturing an HBT epitaxial substrate; Defining a emitter and a base region of the HBT epitaxial substrate; Forming a photoresist film and a dielectric thin film grown at low temperature on the HBT epitaxial substrate and performing plasma etching twice to fabricate a surface protruding portion for lift-off of the ohmic metal; A fourth step of forming a heat-resistant ohmic electrode composed of a metal multilayer of tungsten nitride / tungsten having a composition gradient of tungsten nitride / nitrogen on the surface of the emitter and the base region; Re-growing an aluminum gallium arsenide (AlGaAs) depletion layer on the surface of the base region using the ohmic electrode as a mask layer; And a sixth step of forming a collector electrode on the result of the above steps and performing unit-to-device separation to produce a unit HBT.

Description

Method for manufacturing heterojunction dipole transistor {Method Manufacturing the Heterojunction Bipolar Transistor}

The present invention relates to a method of fabricating a heterojunction bipolar transistor (Heterojunction Bipolar Transistor: HBT) composed of a compound semiconductor of aluminum gallium arsenide (AlGaAs) / gallium arsenide (GaAs), which inhibits the inherent ultrafast characteristics of HBT. A method of manufacturing a heterojunction dipole transistor to control recombination current generation on an extrinsic base surface.

AlGaAs / GaAs HBTs, which use aluminum gallium arsenide as the emitter and gallium arsenide as the base, are being actively applied to ultra-high speed digital and microwave analog circuits. Emitter-based self-alignment techniques are indispensable. However, the biggest technical problem in circuit applications is the reduction of the emitter-base junction size, resulting in the so-called emitter size effect of reduced current gain. The emitter size effect is known to be mainly due to the surface recombination current in the outer base region exposed between the emitter and the base. This is described in "Y. Hiraoka and J. Yoshida, Two-dimensional analysis of emitter-size effect on current gain for AlGaAs / GaAs HBTs, IEEE Trans. Electron Devices, vol. ED-34, p. 721, 1987." Presented in the paper.

Several methods have been proposed to solve this problem of recombination currents. The representative method is the use of a sloped base. This method is described in "O. Nakajima et al., Suppression of emitter size effect on current gain in AlGaAs / GaAs HBTs, Japan. J. Appl. Phys., Vol. 24, p. 1368, 1985." Presented in the paper.

Another method is to protect the area around the emitter-base. For this purpose, an AlGaAs depletion layer is applied between the emitter and the base, or a sulfur-based surface treatment is performed. The method of applying AlGaAs depletion layer is presented in the following four papers. The first paper, "H. H. Liu and S. C. Lee, Super-gain AlGaAs / GaAs heterojunction bipolar transistors using an emitter edge-thinning design, Appl. Phys. Lett., Vol. 47, p. 839, 1985." And a second paper, "W. S. Lee et al., Effect of emitter-base spacing on the current gain of AlGaAs / GaAsheterojunction bipolar transistor, IEEE Electron Device Lett., Vol. 10, p. 200, 1989." And the third paper, "N. Hayama and K. Honjo, Emitter size effect on the current gain in fully self-aligned AlGaAs / GaAs HBTs with AlGaAs surface passivation layer, IEEE Electron Device Lett., Vol. 11, p. 388 , 1990. " And a fourth paper, "M. T. Fresina et al., Selective self-aligned emitter ledge formation for heterojunction bipolar transistor, IEEE Electron Device Lett., Vol. 17, p. 555, 1996." to be.

Sulfur-based surface treatment is described in "CJ Sandroff et al., Dramatic enhancement in the gain of GaAs / AlGaAs heterojunction bipolar transistor by surface chemical passivation, Appl. Phys. Lett., Vol. 51, p. 33, 1987 . " Presented in the paper.

The most commonly used technique to date is to retain a portion of the AlGaAs emitter layer and use it as a depletion layer. 2A to 2D are diagrams illustrating a manufacturing process of a heterojunction dipole transistor according to the prior art.

First, as shown in (A), the semi-insulating gallium arsenide substrate 21, the buffer layer 22, the subcollector layer 23, the collector layer 24, the base layer 25, the emitter layer 26, and the emi The emitter electrode 32 is formed on the HBT epi substrate made of the ter cap layer 27. Next, as shown in (B), the emitter cap layer 27 and the emitter layer 26 are etched, and the AlGaAs emitter layer 26 will remain on the surface of the base layer 25 by a thickness of about 40 to 50 nm. When the etching stops. At this time, it is difficult to control the remaining thickness of the AlGaAs emitter layer 26 accurately, and there is a disadvantage that the plasma etching may cause radiation damage to the surface of the base layer 25.

Next, as shown in (C), a certain distance (approximately 1 um) is dropped around the emitter layer, and the remaining AlGaAs emitter layer 26 is etched and removed to prevent recombination currents on the outer base layer surface. 34) is formed, and the base electrode 33 is deposited next to it. Thereafter, as shown in (D), the device is separated from the collector electrode 35, and the fabrication of the HBT unit device to which the ledge is applied is completed.

The Au-Ge system, which has been intensively researched by ohmic contact with gallium arsenide (GaAs) as a conventional technique, deposits an alloy thin film having an eutectic composition (88wt% Au-12wt% Ge) in high vacuum and undergoes heat treatment. A method of forming ohmic contact through the substrate, in which thermal stability is poor and surface and metal-semiconductor interface shapes are poor, which may cause reliability and reproducibility problems in the manufacturing process of GaAs devices having high device integration. In order to improve the performance, a method of alloying heat treatment after inserting quasi-noble metals such as nickel (Ni) and palladium (Pd) into the diffusion barrier layer has been developed. In addition, since the mid-1980s, research on high temperature ohmic contact systems using heat-resistant metals such as tungsten (W), titanium (Ti), and molybdenum (Mo) has been conducted at the IBM TJWatson Research Center. The stabilization temperature range of most ohmic contact systems is estimated to be within approximately 450 ^° C. Looking only at tungsten, which has excellent thermal stability, W / Ni / InAs, W / Ni / InAs / Ni, NiInW, Au / WSiN / (Au, Ge, Ni), MoGe (As) W, NiInW, W / Ni / In / Ni, WN / Ni, Au / Pt / Ti, W / Ti, W / Al, NiGe (Au) W, Au / WN / Ge / Ni, Au / WN / Ni / Ge / Ni, Au / WN / Ni / Ge, W-In-Si, Ni / Au / Ge / ZrB ₂ , W / InAs / Ni, W / AuGeNi, W / AuZn, Au / Pt / Ti / WSiN / Au / Ge / Ni, Au / WN / AuGeNi, Au / W / Mo / Ge, MoGeInW, GeInW, NiSiW, Au / WSi ₂ / Ge, Au / WSi / Ni / Ge, Au / WSi / Ge, Au / W ₆₀ N ₄₀ / Ge / Ni, W- In, Au / W / Pd / Ge, WInTe, TiWSi _x , Au / Cr / Au / Ge, AuGe / Nb, Au / LaB ₆ / Mo / Ge, Au / LaB ₆ / Ni / Ge .

On the other hand, as the ohmic contact to the p-type GaAs base layer, in addition to the most commonly used AuZn, AuBe, Ag / WN / Pt, Au / Cr, Au / Ti / TiN / Pt, Au / Mo / Ti, Au / Ag / Ti, W / Pd / In / Pd, W, Ti / W, Ti / WSi, Al-Sn-Ni, Al-Ni-Sn, Au / Pd, etc. are used, and Pt / is an ohmic contact to the p-type InGaAs base layer. Ti, Pt / Pd, Pt, Pt / Ti, Au / Ti, Au / Pt / Ti, Au / Pt / Ti / W, Au / Pt / Ti, Ni / AuZn / Ni, Al / Ti / Ge / Pd, TiWN / Al / Zn / Ni, W, W (Zn), Ge / Pd, Au / LaB ₆ / Au / Pd, AuGe / Pd, Au / ZrB ₂ / Pt / Zn / Pt, Au / Cr There is a bar.

As described above, more than hundreds of studies on ohmic contact with compound semiconductors have been made for over 30 years, but as in the present invention, an n-type compound composed of WN _x / WN _{x → 0} / W is formed on a compound semiconductor HBT substrate. There have been no published research papers or patents on emitter and collector ohmic electrodes and p-type base ohmic electrodes.

In summary, as the world changes rapidly from industrial society to information society, the necessity for distributing a large amount of multimedia information in real time is urgent, and the ultra-high speed of core electronic components mounted in information communication system and system for this is needed. Tue and ultra-high frequency are inevitable. HBT devices using compound semiconductors such as gallium arsenide are actively applied as core devices for communication because they have advantages such as high speed and high frequency characteristics, high current driving capability, high breakdown voltage, signal linearity, and uniform operating voltage. In order to take advantage of the inherent advantages of the HBT device, various parasitic elements involved in the manufacturing process, for example, parasitic resistance, parasitic capacitance, or surface recombination current generation in an external base, must be eliminated.

Accordingly, the present invention has been made to solve the problems of the prior art, a method of manufacturing a heterojunction dipole transistor that effectively copes with the problem of generation of surface recombination current in the outer base region, which significantly affects the electrical characteristics of the HBT device. It is to provide.

In addition, the emitter electrode and the base electrode are formed on the epi substrate at the same time by using a sputter deposition method and a lift-off method together while forming a metal material to have stability at high temperature and low resistance. The present invention provides a method of manufacturing a heterojunction dipole transistor that improves the efficiency of an HBT fabrication process by regrowing a gallium arsenide depletion layer on a substrate.

1A to 1K are process diagrams illustrating a manufacturing process of a heterojunction dipole transistor according to an embodiment of the present invention;

2 is a process chart showing a manufacturing process of a heterojunction dipole transistor according to the prior art.

※ Explanation of code about main part of drawing ※

1: Semi-insulating GaAs Substrate

2: Buffer Layer

3: Subcollector Layer

4: Collector Layer

5: Base Layer

6: emitter layer

7: Emitter Cap Layer

8: Polymeric Photoresist

9: dielectric film deposited at room temperature

10: Photoresist as the Masking Layer

11: Tungsten Metal Layers (WNx / WN _{x → 0} / W)

12 Emitter Electrode

13: Base Electrode

14: AlGaAs Depletion Layer

15: Collector Electrode

16: Isolation Area

In order to achieve the above object, a method of manufacturing a heterojunction dipole transistor according to the present invention is a method of manufacturing a compound semiconductor heterojunction dipole transistor (HBT) consisting of GaAs and AlGaAs, the first step of manufacturing an HBT epitaxial substrate Wow; Defining a emitter and a base region of the HBT epitaxial substrate; Forming a photoresist film and a dielectric thin film grown at low temperature on the HBT epitaxial substrate and performing plasma etching twice to fabricate a surface protruding portion for lift-off of the ohmic metal; A fourth step of forming a heat-resistant ohmic electrode composed of a metal multilayer of tungsten nitride / tungsten having a composition gradient of tungsten nitride / nitrogen on the surface of the emitter and the base region; Re-growing an aluminum gallium arsenide (AlGaAs) depletion layer on the surface of the base region using the ohmic electrode as a mask layer; And a sixth step of forming a collector electrode on the resultant of the above steps and performing separation between devices to produce a unit HBT.

Preferably, the third step includes applying a photoresist layer to a first layer on the surface of the emitter and base region and growing a thin dielectric layer on the second layer at room temperature, and forming an anisotropic pattern on the dielectric layer. And isotropically etching the photoresist layer to form a surface protrusion in the region where the ohmic electrode is to be formed.

Preferably, the fourth step includes depositing a tungsten nitride metal having a composition gradient of nitrogen in a first layer on the HBT epitaxial substrate, a nitrogen in a second layer, and a pure tungsten metal in a third layer; Including a step of inducing a short circuit of the metal wiring by the surface protruding portion formed on the dielectric layer, characterized in that to form the emitter electrode and the base electrode having a low ohmic contact resistance and high temperature stability.

More preferably, in the fifth step, the aluminum gallium arsenide depletion layer having a silicon (Si) doping concentration of 2 to 3 x 10 ¹⁶ cm ^-3 is 50 to 3 using the tungsten-based ohmic electrode of the triple layer as a mask layer. It is characterized by growing to a thickness of 60 nm.

Hereinafter, a method of manufacturing a heterojunction dipole transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1K are flowcharts illustrating a manufacturing process of a heterojunction bipolar transistor (HBT) according to an embodiment of the present invention.

FIG. 1A is a cross-sectional view showing the epi structure of a conventional HBT element formed on a compound semiconductor substrate 1 composed of Groups III-5, Gallium Arsenide (GaAs) on the periodic table, which is electrically semi-insulating. . The HBT epitaxial substrate may be manufactured through various growth methods such as molecular beam epitaxy (MBE) or metal-organic chemical beam epitaxy (MOCVD). In the present invention, the epitaxial structure is grown by the same method as the general HBT structure. That is, first, a gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) buffer layer 2 is grown on the substrate 1, and then the sub-collector layer 3, the collector layer 4, and the base layer 5 by GaAs are grown. ) Is sequentially stacked and then grown in order toward the surface according to the order of the AlGaAs emitter layer 6 and the GaAs or InGaAs (indium gallium arsenide) emitter cap layer (7).

Subsequently, as illustrated in FIG. 1B, the emitter cap layer 7 and the emitter layer 6 are removed by a general mesa etching method such as wet chemical or plasma etching. Allow the surface to be exposed. Next, as shown in FIG. 1C, a conventional polymeric photoresist 8 is first applied to the entire portion of the emitter and the base region to a thickness of about 0.6 to 0.8 um, and the solvent is removed by curing heat treatment. . As a method for subsequent low temperature deposition, a dielectric thin film 9 such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ) is 0.2 using an electron cyclotron (ECR) plasma CVD or a laser-applied CVD method. Deposit at room temperature with a thickness of about 0.3 um.

Subsequently, as shown in FIG. 1D, the photoresist film 10 is applied as a mask for pattern formation, and is coated on the entire surface of the epi substrate with a thickness of about 1.1 to 1.2 um, and the region where the emitter and the base electrode are to be formed by using lithography technology. Define. In FIG. 1E, the above dielectric thin film layer 9 is selectively removed by primary plasma etching so that anisotropic is large by using CF-based Freon gas. An important process condition here is to maintain the etching process only in the vertical direction without being wider than the width of the photoresist pattern originally defined during the dielectric film etching. An anisotropic etched state completed in this state is shown in FIG. 1E. If the lower photoresist film 8 is slightly removed or laterally widened by the over etching after the dielectric film etching, it does not have any influence.

Continuing to removing the photoresist layer (10) previously used as a mask for the dielectric layer etch as shown in Figure 1f, and by using the dielectric film 9 as a mask, performing a second plasma etching process, O _2, N ₂ O Unlike when the dielectric film is etched by using an oxygen-based gas plasma, such as O ₃ , the isotropic etching (that is, the etching may be performed in the horizontal direction by the vertical direction) is performed, as shown in FIG. 1F. The shape in which the surface inlet protrudes from the lower photosensitive film 8 below is achieved. In this process, the oxygen plasma does not damage the dielectric film unless the energy is increased particularly. This surface protrusion serves advantageously for liftoff in forming ohmic electrodes by sputtering with high energy vertical directivity for tungsten based metal deposition in subsequent process steps. In the conventional lift-off method, the surface protruding structure using only the photoresist film has a disadvantage in that it is difficult to achieve a fine and uniform pattern because it is damaged by a high energy beam during sputtering. In addition, when a tungsten electrode metal is deposited on the front surface of a substrate by a sputtering method and a pattern is formed by plasma etching, it is difficult to obtain a clean semiconductor surface due to overetching or radiation damage.

Then, as shown in FIG. 1G, as an ohmic electrode for the emitter and the base, tungsten nitride having a composition gradient of tungsten nitride (WN _x ) metal 13 in the first layer and nitrogen in the second layer ( The WN _{x → 0} ) metal 14 is deposited on the front surface of the wafer by reactive sputtering with a tungsten (W) metal 15 on the third layer. Here, the tungsten nitride metal layer used as the base metal is not only excellent in heat resistance and high temperature stability, but also has a small stress on the substrate as compared to pure tungsten, and the composition of nitrogen is then ordered from the first x to the third layer. The use of tungsten nitride having an inclined structure that changes to zero of tungsten is used in the middle to facilitate the movement of electrons from the pure tungsten of the uppermost layer with very low electrical resistance.

Finally, the deposition of pure tungsten causes a short circuit of the triple metal layer 11 at the surface protrusion of the dielectric layer 9, followed by removal of the lower photoresist film 8 using an acetone solution. In addition to the electrode, even the unnecessary metal layer is removed together, so that the emitter electrode 12 and the base electrode 13 are simultaneously formed as shown in FIG. 1H. Therefore, the emitter and base ohmic electrode of the HBT can be achieved with high quality by one metal deposition, thereby reducing the manufacturing cost and improving the reproducibility of the manufacturing process.

Ohmic contact according to the present invention, the conventional high-performance HBT maintaining a high doping concentration on the respective active region, so up to about 500 ^O C degree in the case, but to obtain a low contact resistance, the heat treatment according to the special purposes required without the need for special heat treatment In case of rapid thermal alloying (RTA) at high temperature, low contact resistivity of less than 10 ^-6 Ω-cm ² can be achieved without increasing resistance.

Thereafter, as shown in FIG. 1I, the aluminum gallium arsenide depletion layer 14 is regrown on the HBT substrate using the tungsten-based ohmic electrode as a mask layer. At this time, the silicon (Si) doping concentration of the aluminum gallium arsenide depletion layer is about 2 to 3 x 10 ¹⁶ cm ^-3 , and lower than the concentration of 2 to 5 x 10 ¹⁷ cm ^-3 , which is usually used as an emitter, Good depletion effect, thickness grows 50 ~ 60 nm. When the residual AlGaAs layer on the base layer is used as a depletion layer by etching the conventional emitter layer, it is difficult to precisely control the thickness by etching, and when the dry etching method is used, damage to the substrate is caused. The method of suppressing the base surface recombination current generation by the self-aligned regrowth depletion layer by utilizing the ohmic electrode stable at high temperature in can be very effective.

Thereafter, as shown in FIG. 1J, the collector electrode 15 is formed after etching the base mesa as shown in FIG. 1J, and electrical isolation between devices is performed by using mesa etching or ion implantation as shown in FIG. 1K. When the region 16 is formed, fabrication of the heterojunction dipole transistor using the new ohmic electrode and the regrowth depletion layer manufacturing method is completed.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, according to the present invention, the parasitic effect between the active area, that is, the emitter and the base, which plays a decisive role in the performance of the HBT device can be removed in advance, and a technical contribution can be made to implement the ultra-high speed characteristics. Compared to the method, the manufacturing cost can be reduced by reducing the process steps.

Claims (4)

In the method of manufacturing a compound semiconductor heterojunction dipole transistor (HBT) consisting of GaAs and AlGaAs, A first step of fabricating the HBT epi substrate; Defining a emitter and a base region of the HBT epitaxial substrate; Forming a photoresist film and a dielectric thin film grown at low temperature on the HBT epitaxial substrate and performing plasma etching twice to fabricate a surface protruding portion for lift-off of the ohmic metal; A fourth step of forming a heat-resistant ohmic electrode composed of a metal multilayer of tungsten nitride / tungsten having a composition gradient of tungsten nitride / nitrogen on the surface of the emitter and the base region; Re-growing an aluminum gallium arsenide (AlGaAs) depletion layer on the surface of the base region using the ohmic electrode as a mask layer; And And forming a collector electrode on the resultant of the above steps and performing separation between devices to produce a unit HBT. The method of claim 1, wherein the third step comprises applying a photoresist layer to a first layer on the surface of the emitter and the base region and growing a thin dielectric layer on the second layer at room temperature, and forming an anisotropic pattern on the dielectric layer. And forming a surface protrusion in an area in which an ohmic electrode is to be formed by isotropically etching the photoresist layer. The method of claim 1, wherein the fourth step is Depositing tungsten nitride metal having a composition gradient of nitrogen in the first layer on the HBT epitaxial substrate, pure tungsten metal in the third layer, and depositing pure tungsten metal on the third layer; A method of manufacturing a heterojunction dipole transistor, comprising: forming an emitter electrode and a base electrode having low ohmic contact resistance and high temperature stability, including inducing a short circuit and then lifting off the wiring. The method of claim 3, wherein the fifth step is The aluminum gallium arsenide depletion layer having a silicon (Si) doping concentration of about 2 to 3 x 10 ¹⁶ cm ^-3 is grown to a thickness of 50 to 60 nm using the triple tungsten-based ohmic electrode as a mask layer. Method of manufacturing a heterojunction dipole transistor.