JP2006344884A - Heterojunction semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance properties such as high-frequency properties by reducing both base-collector capacitance and base contact resistance. <P>SOLUTION: A heterojunction bipolar transistor 24a has a laminate that consists of at least a collector layer 3, a base layer 4, and an emitter layer 5. In the heterojunction bipolar transistor 24a; an emitter cap layer 6, the emitter layer 5, and the collector layer 3 form an undercut shape. Each undercut portion is filled with an organic insulating film 9A or 9B, and a base electrode 12 is formed in a section from the side surface to a portion of the top surface of the base layer 4 that is self-alignedly formed relative to an emitter electrode 7 by means of a liftoff process performed after an omnidirectional vapor deposition process. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a heterojunction semiconductor device suitable for, for example, an ultrahigh-speed digital integrated circuit, a microwave analog integrated circuit, an optical signal amplification device, and the like, and a method for manufacturing the same.

  Conventionally, a heterojunction bipolar transistor (hereinafter sometimes referred to as HBT (Hetero junction Bipolar Transistor)) using a wide gap semiconductor for the emitter layer has a high emitter injection efficiency and a high current gain. Since the base resistance can be reduced while maintaining the current gain, it is promising as an ultrahigh-speed device.

  In addition, the HBT is capable of single power supply operation and has features such as low power consumption, high linearity, and high power density, and thus has been widely used as an element for a power amplifier of a mobile phone. Furthermore, it is used as an element for a digital IC for high-speed optical communication because of its high-speed operation. In these applications, the device is required to have high reliability as well as high performance.

  An example of an HBT 74a will be described with reference to FIG. 16A (see Patent Document 1 described later).

In this heterojunction bipolar transistor 74a, on a semi-insulating GaAs substrate (not shown), an n ⁺ -type GaAs subcollector layer (not shown), an n-type GaAs collector layer 53, a p-type GaAs base layer 54, The n-type AlGaAs emitter layer 55, the n ⁺ -type GaAs emitter contact layer 55b, the base electrode 65, and the emitter electrode 66 are stacked, and the side surfaces of the emitter layer 55, the emitter contact layer 55b, and the emitter electrode 66 are covered with the insulating film 70. ing.

An intrinsic base region 54b to which carbon having a concentration of 1 × 10 ²⁰ cm ⁻³ is added is formed in the base layer on the collector layer 53. Since this carbon is passivated by hydrogen, the hole concentration is 5 × 10 ¹⁹ cm ⁻³ .

Further, an external base region (base contact region) 54c to which carbon having a concentration of 1 × 10 ²⁰ cm ⁻³ is added is formed on the surface portion around the base layer. This carbon is almost 100% activated. Therefore, the hole concentration is 1 × 10 ²⁰ cm ⁻³ . The emitter layer 55 is formed by hetero-coupling on the intrinsic base region 54b, and the base electrode 65 is formed in ohmic contact on the external base region 54c.

  FIG. 16B shows another example 74b of a heterojunction bipolar transistor (see Patent Document 2 described later).

  The heterojunction bipolar transistor 74b includes a sub-collector layer 52, a GaAs collector layer 53, a p-type AlGaAs base layer 54, an n-type AlGaAs emitter layer 55, and an n-type InGaAs emitter cap stacked on a semi-insulating GaAs substrate 51. A layer 76, an emitter contact layer 55b, a collector electrode 67, a base electrode 65, and an emitter electrode 66 are formed.

  Then, an emitter electrode 66 made of a non-alloy type electrode material is formed in the first stage of the manufacturing process of the HBT 74b, and an emitter mesa and a base electrode 65 are formed in a self-aligned (self-aligned) manner with respect to the emitter electrode 66, Further, a base and a collector mesa are formed in a self-aligned manner with respect to the base electrode 65.

  FIG. 17A shows an emitter ledge type heterojunction bipolar transistor 74c similar to this structure.

  In the heterojunction bipolar transistor 74c, a lower portion of the emitter layer 55 is extended, a base electrode 65 is formed on the extended portion, and a Pt diffusion region (base contact) 73 is formed on the lower portion. Has substantially the same structure as the heterojunction bipolar transistor 74b.

  FIG. 17B shows another heterojunction bipolar transistor 74d.

  The heterojunction bipolar transistor 74d includes a subcollector layer 52, a collector layer 53, a base layer 54, and a base electrode 65 (metal layer) deposited on the base layer 54. The base electrode 65 extends toward the contact pad 63 by a metal air bridge 61 formed on a recessed space 62 formed by etching a lower semiconductor layer.

  In order to fabricate the metal air bridge portion 61, a first local etching step of selectively etching the subcollector layer 52 in the lower region of the metal air bridge portion 61, and at least a collector in the lower region of the metal air bridge portion 61. A space 62 is formed by a second local etching step that selectively etches layer 53.

JP-A-7-2111729 (page 5, left column, line 17 to page 5, right column, line 6, line 1) JP-A-5-136159 (page 4, right column, line 17 to page 6, left column, line 9, line 1) JP 2001-308321 A (5th page, left column, 5th line to 5th page, left column, 15th line, FIG. 5)

  In the HBT 74a shown in FIG. 16A and the HBT 74b shown in FIG. 16B, the length of the base layer 54 from the emitter layer 55 to the base electrode 65 is minimized, and the external base that is the internal resistance of the base layer 54 is used. In order to reduce resistance, a base electrode 65 self-aligned with the emitter electrode 66 is formed.

  However, in this case, since the base electrode 65 is formed on the base layer 54, the area of the base layer 54 must be increased by the area of the base electrode 65, and thereby the base layer 54 and the collector layer 53. As a result, the base-collector capacitance is increased and the high-frequency characteristics are likely to deteriorate.

  In the HBT 74c having the emitter ledge structure shown in FIG. 17A, the base layer 54 and the base electrode 65 are electrically connected through the Pt diffusion region 73 formed by alloying the base metal. However, the base contact resistance tends to increase or become unstable.

  In any HBT, a base wiring contact portion (base lead-out portion or base electrode lead-out portion) is provided on the base layer 54. Since an area is required to secure the wiring pad portion, the base-collector capacitance is increased. Further increase. In order to prevent this, a mesa structure is provided under the contact pad 63, which is the base electrode lead-out portion, as shown in "Science Technical Report ED99-262, MW99-186, ICD99-237: P23-28" and FIG. However, there is a problem in that the formation process of the metal air bridge portion 61 accompanied with the formation of the space 62 is complicated and control in the process is difficult. is there.

  The present invention has been made in view of such circumstances, and an object of the present invention is to reduce both the base-collector capacitance and the emitter-base electrode external base resistance, and to improve characteristics such as high-frequency characteristics. It is an object of the present invention to provide a heterojunction semiconductor device and a method for manufacturing the same.

  That is, the present invention is characterized in that, in a heterojunction bipolar semiconductor device having a laminate composed of at least a collector layer, a base layer, and an emitter layer, a base electrode is formed on at least a side surface of the base layer. The present invention relates to heterojunction semiconductor devices, particularly HBTs (hereinafter the same).

The present invention also provides a method of manufacturing a heterojunction semiconductor device having a laminate including at least a collector layer, a base layer, and an emitter layer.
Laminating at least a collector layer constituent material layer, a base layer constituent material layer, and an emitter layer constituent material layer;
Processing the base layer constituent material layer to form the base layer;
And a step of forming a base electrode on at least a side surface of the base layer. The present invention relates to a method for manufacturing a heterojunction semiconductor device.

  According to the present invention, since the base electrode is formed on at least the side surface of the base layer, the area of the base layer can be reduced as compared with the case where the base electrode is formed on the base layer. The capacitance between the base and the collector due to the bonding with the layer can be reduced, and further the device size (chip size) can be reduced.

  In addition, the base contact resistance can be kept small because of the balance between the distance between the emitter layer and the base electrode and the area size of the side surface of the base layer for the base contact. There is virtually no junction between the base layer and the collector layer under the subordinate, and the base-collector capacitance is further reduced, thus improving the high frequency characteristics (improvement of gain, cutoff frequency, operating efficiency, etc.) Can do.

  In addition, since the base electrode does not exist on the base layer (that is, on the collector layer), no distortion occurs in the collector layer when the base electrode material is alloyed, and no leak occurs between the base and the collector.

  In the present invention, in order to reduce the external base resistance by shortening the distance from the junction surface between the emitter layer and the base layer to the side surface of the base layer (the contact surface between the base layer and the base electrode). Preferably, the base layer is formed in the same pattern and size as the emitter electrode in a self-aligning manner.

  Further, in order to prevent an electrical short circuit or current leakage between the emitter cap layer and the emitter layer and the base electrode, the emitter cap layer and the emitter layer immediately below the emitter electrode are connected to the emitter electrode. On the other hand, it has an undercut shape, further reduces the junction capacitance between the base layer and the collector layer, prevents electrical short circuit or current leakage between the collector layer and the base electrode, In order to prevent the collector layer from being distorted when forming the base electrode and eliminate the leakage current between the base and the collector, the collector layer immediately below the base layer has an undercut shape with respect to the base layer, It is desirable that each undercut portion is filled with an insulator.

  In this case, it is desirable that the insulator is made of an organic insulating film having a good dielectric property (coverage) and low parasitic capacitance and a low dielectric constant, for example, benzocyclobutene (BCB).

  Similarly, the sub-collector layer and the collector layer immediately below the collector electrode have an undercut shape with respect to the collector electrode, and the emitter layer immediately below the base layer has an undercut shape with respect to the base layer. Also, it is desirable that each of the undercut portions is filled with the insulator.

  Further, in order to increase the contact area between the base layer and the base electrode to further reduce the base contact resistance, the surface of the base layer on the emitter electrode side is partially exposed around the insulator, The base electrode can be formed from the exposed surface to the side surface.

  Furthermore, in order to take out the base electrode to the wiring without causing a base-collector junction capacitance, the base electrode is formed in contact with the insulator, and the base electrode is formed on the base on the insulator. It is desirable to extend to the electrode lead-out part (base lead-out part).

  In order to satisfactorily achieve lattice matching between the constituent layers of the HBT, it is desirable that at least each constituent layer of the stacked body is made of a semiconductor that lattice matches with indium phosphide.

  In order to facilitate the formation of the above-described undercut shape by side etching, it is desirable that the orientation of the side of the emitter layer or the collector layer is parallel to a direction equivalent to the <010> direction.

  In addition, when the laminate has an emitter ledge structure, the surface of the base layer is not exposed, so that characteristic deterioration due to recombination can be prevented. Even in such an emitter ledge structure, since the base electrode contacts with the side surface of the base layer, alloying of the base electrode material through the emitter layer is unnecessary, and the base contact can be stably and reliably taken. .

Moreover, when it has the above-mentioned undercut shape,
Processing the emitter cap layer directly below the emitter electrode and the emitter layer into the undercut shape;
Protecting this undercut with a resist,
After forming the base layer, processing the collector layer immediately below the undercut shape;
After removing the resist, applying an insulator over the entire surface;
Etching back and etching until at least the side surface of the base layer is exposed;
Applying isotropic etching to the insulator filled in the side surface of the emitter layer so as to prevent the semiconductor layer from being exposed;
It is desirable to include a step of forming the base electrode by applying a base electrode constituent material and then lifting off in a self-aligned manner.

Or
Processing the sub-collector layer and the collector layer immediately below the collector electrode into the undercut shape;
Protecting this undercut with a resist,
After forming the base layer, processing the emitter layer immediately below the undercut shape;
After removing the resist, applying an insulator over the entire surface;
Etching back and etching until at least the side surface of the base layer is exposed;
Applying a side etch to the insulator filled in the side surface of the collector layer by isotropic etching to such an extent that the semiconductor layer is not exposed;
It is desirable to include a step of forming the base electrode by applying a base electrode constituent material and then lifting off in a self-aligned manner.

  Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

First Embodiment FIGS. 1 to 12 show a first embodiment of the present invention.

  First, referring to FIG. 1A, which is a cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. 1B, which is a cross-sectional view taken along the line BB ′ of FIG. The structure of (HBT) 24a will be described.

For example, an n ⁺ -type InGaAs subcollector layer 2 having a film thickness of 300 nm and an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ on a semi-insulating InP substrate (substrate) 1 and a sufficient film thickness for increasing the withstand voltage. An n-type InP collector layer 3 having a thickness of 300 nm and an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ , a p ⁺ -type InGaAs base layer 4 having a thickness of 50 nm and an impurity concentration of 3 × 10 ¹⁹ cm ⁻³ , a thickness of 100 nm and an impurity concentration of 1 An n-type InP emitter layer 5 of × 10 ¹⁸ cm ⁻³ and an n ⁺ -type InGaAs emitter cap (contact) layer 6 having a film thickness of 50 nm and an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ are sequentially stacked, and each semiconductor layer On top of this, a collector electrode 17, an emitter electrode 7, and a base electrode 12 are provided. Each constituent layer of this structure is made of a semiconductor lattice-matched to indium phosphide.

  The emitter mesa portion composed of the emitter cap layer 6 and the emitter layer 5 is formed in an undercut shape with respect to the emitter electrode 7. The base mesa portion formed of the base layer 4 is formed in the same pattern and size as the emitter electrode 7 in a self-aligned manner (that is, in the same position and the same size in the vertical direction). The collector layer 3 is formed in an undercut shape under the base layer 4.

  Further, undercut portions of the emitter cap layer 6, the emitter layer 5 and the collector layer 3 are filled with, for example, benzocyclobutene (BCB) which is organic insulating films 9A and 9B having a low dielectric constant. The organic insulating film 9A filled in the side portion of the emitter section composed of the emitter cap layer 6 and the emitter layer 5 is slightly side-etched, and at the edge (end in the planar direction) of the base layer 4, a part of the side surface and the upper surface is formed. The base electrode 12 is deposited on the exposed portion from the side surface of the base layer 4 to a part of the upper surface and the organic insulating film 9B. A collector electrode 17 is formed by opening a window in the organic insulating film 9B left on the subcollector layer 2.

  Further, as shown in the plan view of FIG. 2, the base electrode 12 is provided so as to surround the emitter electrode 7, but it is not always necessary to surround all of them. Further, the base electrode 12 is formed in contact with the organic insulating film 9B and extends to the base leading portion 23 on the organic insulating film 9B. Further, for each wiring, the base electrode 12 is formed on the base leading portion 23. A base contact (plug) 21B is formed, a collector contact (plug) 21C is formed on the collector electrode 17, and an emitter contact (plug) 21E is formed on the emitter electrode 7.

  According to the present embodiment, the base electrode 12 is formed on at least the side surface of the base layer 4 formed so as to be self-aligned (self-aligned) with the emitter electrode 7, that is, from the side surface to a part of the upper surface. Therefore, the area of the base layer 4 can be reduced compared with the case where the base electrode 12 is formed on the base layer 4, and the base-collector capacitance due to the junction between the base layer 4 and the collector layer 3 is reduced. Furthermore, the element size (chip size) can be reduced. Further, since the base electrode 12 is formed from the side surface of the base layer 4 to a part of the upper surface, the base contact resistance can be reduced. In addition, since the base layer 4 is formed in a self-aligned manner, the length of the base layer 4 between the emitter layer 5 and the base electrode 12 can be minimized, and the resistance between the emitter layer and the base electrode (external base resistance). ) Can be minimized.

  Further, the base contact resistance can be kept small and the base electrode 12 can be secured from the balance between the distance between the emitter layer 5 and the base electrode 12 and the area size of the side surface of the base layer 4 for the base contact. There is substantially no junction between the base layer 4 and the collector layer 3 under the base and the base lead-out portion 23, and the base-collector capacitance is further reduced. Therefore, the high frequency characteristics are improved (gain, ft (cutoff frequency: improvement in operation efficiency such as cutoff frequency and emitter efficiency) can be realized.

  In addition, since the base electrode 12 does not exist on the base layer 4 (that is, on the collector layer 3), no distortion occurs in the collector layer 3 when the base electrode material is alloyed, and no leak occurs between the base and the collector. .

  Furthermore, since the HBT 24a can be manufactured by an existing method including the base electrode 12, it can be manufactured easily and reliably.

  Next, an example of a method for manufacturing the HBT 20a will be described with reference to FIGS.

First, as shown in FIGS. 3 (1) and 3 (2), an n ⁺ -type InGaAs subcollector material (subcollector layer constituting material) having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is formed on a semi-insulating InP substrate 1. Layer 2a is formed to a thickness of 300 nm by chemical vapor deposition (CVD).

Next, as shown in FIG. 3 (3), an n-type InP collector material (collector layer constituting material layer) 3a having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ is formed on the subcollector material 2a to a thickness of 300 nm by CVD. Form.

Next, as shown in FIG. 3 (4), a p ⁺ -type InGaAs base material (base layer constituting material layer) 4a having an impurity concentration of 3 × 10 ¹⁹ cm ⁻³ is formed on the collector material 3a to a thickness of 50 nm by CVD. Form.

Next, as shown in FIG. 3 (5), an n-type InP emitter material (emitter layer constituting material layer) 5a having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is formed on the base material 4a to a thickness of 100 nm by CVD. To do.

4 (6), an n ⁺ -type InGaAs emitter cap material (emitter cap layer constituting material layer) 6a having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is formed on the emitter material 5a by CVD to a thickness of 50 nm. To form.

  Next, as shown in FIG. 4 (7), an emitter electrode material (emitter electrode constituent material layer) 7a is formed on the emitter cap material 6a by CVD.

  Next, as shown in FIG. 4 (8), by etching the emitter electrode material 7a, the emitter electrode (Ti / Pt / Au, each thickness is 50 nm / 50 nm / 300 nm) 7 is transformed into an HBT epitaxial structure (( 100) on the emitter cap material 6a of the wafer). At this time, it is convenient to use the lift-off method.

  Next, as shown in FIGS. 5 (9) and 5 (10), the emitter cap material 6a is wet-etched with a mixed solution of phosphoric acid, hydrogen peroxide solution, and water to be processed into an undercut shape. The emitter material 5a is wet-etched with a mixed solution of hydrochloric acid and phosphoric acid and processed into an undercut shape. In this way, the emitter cap layer 6 and the emitter layer 5 are formed.

  By processing into an undercut shape in this way, a step is generated between the emitter cap layer 6 and the emitter layer 5, and this step causes an organic layer to be described later from the side surface of the emitter cap layer 6 to the side surface of the emitter layer 5. It becomes easy to deposit the insulating film 9A.

  At the time of this processing, by making the direction of the side of the emitter material 5a parallel to the direction equivalent to the <010> direction, in particular, the side etching can be greatly performed in the emitter material 5a. Further, since the side etch rate of the emitter cap material 6a is not fast, each undercut shape can be adjusted depending on the overetching time.

  Next, as shown in FIGS. 5 (11) and 5 (12), a resist 8 is applied to the entire surface of the base material 4a, and the entire surface is exposed. As a result, the emitter electrode 7 acts as a mask, and the resist 8 remains only in the undercut portions of the emitter cap layer 6 and the emitter layer 5 by development processing.

  Next, as shown in FIGS. 6 (13) and 6 (14), the base material 4a is wet-etched with a mixed solution of phosphoric acid, hydrogen peroxide water, and water, and subsequently, the collector material 3a is treated with hydrochloric acid and phosphorus. Wet etching with a mixed solution with acid to process into an undercut shape. In this way, the base layer 4 and the collector layer 3 are formed.

  Also at this time, since the direction of the collector material 2a is parallel to the direction equivalent to the <010> direction, the side etching is greatly performed in the collector material 2a.

  By processing into an undercut shape in this way, the junction area between the base layer 4 and the collector layer 3 can be reduced, and the junction capacitance generated between the base layer 4 and the collector layer 3 can be reduced. The characteristics can be improved. Moreover, the insulation protection of the edge part of the collector layer 3 can fully be performed, and the electrical short circuit with the collector layer 3 and the base electrode 12 can be prevented.

  Next, as shown in FIG. 6 (15), after removing the resist 8, an organic insulating material (for example, BCB: benzocyclobutene) is applied to the entire surface of the collector material 2a, and is hardened and flattened.

  Next, as shown in FIGS. 7 (16) and 7 (17), the organic insulating material 9a is partially etched back by reactive ion etching (RIE). This etch back can be performed by two-stage etching.

  For example, as a first step, anisotropic etching by RIE is performed until a part of the side surface of the base layer 4 is exposed along the extended line of the side surface of the emitter electrode 7 as shown in FIG. As a second stage, as shown in FIG. 7 (17), by performing normal isotropic etching, side etching is performed on the organic insulating material 9a on the side surfaces of the emitter cap layer 6 and the emitter layer 5 to form an organic insulating film. 9A is formed, and isotropic etching is stopped when the side surface of the base layer 4 is completely exposed, thereby preventing side etching from entering the organic insulating material 9a under the base layer 4.

  As a first step in another method using RIE, etching with a certain amount of isotropic component is performed until a part of the side surface of the base layer 4 is exposed, and the emitter cap layer 6 and the emitter layer. Side-etching is performed on the organic insulating material 9a on the side surface 5 to form an organic insulating film 9A. As a second step, after a part of the side surface of the base layer 4 is exposed, anisotropic etching is performed so that side etching does not enter the organic insulating material 9a under the base layer 4. It is desirable to stop the etching when is completely exposed.

  Since the organic insulating film 9A is deposited on the undercut portion, current leakage between the emitter cap layer 6 and the emitter layer 5 and the base electrode 12 can be prevented.

  Next, as shown in FIGS. 7 (18) to 9 (22), a resist pattern for lifting off the base electrode 12 is formed, and the base electrode material (Ti / Pt / Au, each thickness is 50 nm / 50 nm / 200 nm) 12 a is deposited, and the base electrode 12 is formed by lift-off.

  That is, first, as shown in FIG. 7 (18), a resist 10 is formed on the organic insulating material 9a so as to cover the emitter electrode 7 and the like, and another resist 11 is formed thereon.

  Next, as shown in FIG. 8 (19), the resist 11 is exposed and developed with a developer to form an opening 14a.

  Next, as shown in FIG. 8 (20), the resist 10 is isotropically over-developed with the developer used for developing the resist 11, thereby opening the opening 14b having a step with respect to the opening 14a. Form. The opening 14a and the opening 14b communicate with each other to form an integrated opening, between the side surface of the resist 11 and the side surface of the resist 10, and between the side surface of the emitter electrode 7 and the organic insulating film 9A. Steps (protrusions) are provided between the side surfaces.

  Next, as shown in FIG. 8 (21), the base electrode material 12 a is vacuum-deposited from all directions on the resist 11 through the opening 14 a and the opening 14 b to form the base electrode 12. In this deposition, omnidirectional deposition with vertical and oblique components is performed so that the base electrode material 12a is sufficiently deposited on the side surface of the base layer 4. Then, the base electrode 12 can be selectively formed on the organic insulating material 9a. The base electrode 12 does not necessarily have to be formed over a part of the upper surface of the base layer 4, and may be formed only on the side surface of the base layer 4.

  At this time, steps are provided between the side surface of the resist 11 and the side surface of the resist 10 and between the side surface of the emitter electrode 7 and the side surface of the organic insulating film 9A. When it does not exist, it is possible to prevent the base electrode material 12a from being deposited and the emitter electrode 7 and the base electrode 12 from being electrically short-circuited as indicated by a broken line in the drawing.

  Next, as shown in FIG. 9 (22), the resist 10, the resist 11, and the base electrode material 12a deposited thereon are removed by lift-off to leave the base electrode 12 selectively. The base electrode material 12a on the emitter electrode 7 may be removed or left as it is.

  Next, as shown in FIG. 9 (23), a resist 13 and further another resist 16 are formed on the organic insulating material 9a so as to cover the entire surface.

  Next, as shown in FIG. 9 (24), the resist 16 is exposed and developed with a developer to form an opening 15a. Next, the resist 13 is isotropically over-developed with the developer used for developing the resist 16, whereby the opening 15b having a step with respect to the opening 15a can be formed. The opening 15 a and the opening 15 b communicate with each other to form an integrated opening, and a step (ridge) is provided between the side surface of the resist 16 and the side surface of the resist 13.

  Next, as shown in FIG. 10 (25), an opening 15c having the same shape and size as the opening 15b is formed in the organic insulating material 9a by etching.

  Next, as shown in FIG. 10 (26), by using the resists 16 and 13 as a mask, the collector electrode material is selectively deposited by omnidirectional deposition similar to the above through the openings 15a and 15b. The collector electrode (Ti / Pt / Au, each thickness is 50 nm / 50 nm / 300 nm) 17 is formed. In this way, the collector electrode 17 is formed in the opening 15c.

  At this time, since the step (ridge) is provided between the side surface of the resist 16 and the side surface of the resist 13, the collector electrode material does not adhere to the resist side surface (inner wall surface), and the residue after the next lift-off is removed. The short circuit between the electrodes due to this residue can be prevented.

  Next, as shown in FIG. 11 (27), the resist 16, the resist 13, and the collector electrode material deposited thereon are removed by lift-off.

  Next, as shown in FIG. 11 (28), an organic insulating material 19 made of BCB is formed on the organic insulating film 9a so as to cover the entire surface. Thereafter, openings (contact holes) 18 are formed on the base electrode lead-out portion 23 (see FIG. 2), the emitter electrode 7 and the collector electrode 17.

  Next, as shown in FIG. 12 (29), each opening 18 is filled with a plug material up to the surface height of the organic insulating layer 19 to form a collector contact (plug) 21 C on the collector electrode 17. An emitter contact (plug) 21E is formed thereon, and a base contact (plug) 21B is formed on the base lead portion 23.

  Next, as shown in FIG. 12 (30), wirings 22 are formed on the collector contact (plug) 21C, the emitter contact (plug) 21E, and the base contact (plug) 21B, respectively, so that the HBT 24a is manufactured. Exit.

  According to this manufacturing method, an HBT can be easily and reliably manufactured simply by applying existing processes including the formation of the base electrode 12.

Second Embodiment FIG. 13 shows a second embodiment of the present invention.

  According to the structure of the heterojunction bipolar transistor (HBT) 24b according to the present embodiment, a part of the thickness of the organic insulating film 9B is etched away along the side surface of the base layer 4, and the upper surface of the base layer 4 is removed. The base electrode 12 is provided continuously from a part of the base layer 4 to the side surface of the base layer 4, the vertical surface and the bottom surface of the organic insulating film 9B, and is the same as in the first embodiment described above.

  That is, in the first embodiment described above, since the etch-back control shown in FIG. 7 (17) is relatively difficult, the organic insulating material 9a provided on the side portion of the collector layer 3 is a collector. There is a case where overetching is performed up to a position below the surface of the layer 3. The present embodiment has a structure in accordance with the actual situation in the actual manufacturing process.

  In addition, in the present embodiment, the same operations and effects as described in the first embodiment described above can be obtained.

Third Embodiment FIG. 14 shows a third embodiment of the present invention.

  The heterojunction bipolar transistor (HBT) 24c according to the present embodiment is the same as the first embodiment described above except that it has a collector-up structure.

  In the present embodiment, the arrangement of the constituent layers from the emitter electrode 7 to the collector electrode 17 is changed up and down as compared with the first embodiment described above, and the subcollector layer 2 immediately below the collector electrode 17 is replaced. And a step of processing the collector layer 3 into an undercut shape, a step of protecting the undercut portion with a resist, a step of processing the emitter layer 5 immediately below after forming the base layer 4 into an undercut shape, After removing the resist, the step of applying an organic insulating material to the entire surface, the step of etching until at least the side surface of the base layer 4 is exposed by etch back, and the side surface of the collector layer 3 are filled by isotropic etching. A step of side-etching the organic insulating film 9A so that the emitter cap layer 6 and the emitter layer 5 are not exposed; and a base electrode After depositing the 12a, and a step of selectively forming a base electrode 12 by a self-aligned manner liftoff performed in the same manner as described in the first embodiment described above.

  In addition, in the present embodiment, the same operations and effects as described in the first embodiment described above can be obtained.

Fourth Embodiment Figure 15 embodiment of the shows a fourth embodiment of the present invention.

  As shown in FIG. 15, according to the structure of the heterojunction bipolar transistor (HBT) 24d according to the present embodiment, an emitter ledge structure in which the emitter layer 5 is disposed on the entire upper surface of the base layer 4 is formed. Except that the base electrode 12 is selectively provided continuously from a part of the upper surface and the side surface of the layer 5 to the side surface of the base layer 4 and the upper surface of the organic insulating film 9B, the first embodiment described above It is the same.

  According to the present embodiment, the entire upper surface of the base layer 4 is covered with the emitter layer 5, and there is no need to dispose the base electrode 12 on the emitter layer 5, and the base layer 4 is interposed via the side surface of the base layer 4. And the base electrode 12 can be electrically connected. As a result, in the emitter ledge structure, it is possible to prevent the base contact from being increased or unstable due to alloying of the base electrode material, and further to prevent the collector layer from being distorted without increasing the base contact resistance. It is advantageous for.

  In addition, in the present embodiment, the same operations and effects as described in the first embodiment described above can be obtained.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  For example, the shape, position, size, and the like of the base electrode 12 can be freely changed as long as the base electrode 12 is in contact with the side surface of the base layer 4.

  The base layer 4 is preferably formed in the same pattern and size as the emitter electrode in a self-aligning manner, but may be patterned using another mask. Also at this time, a small base contact resistance can be ensured from the balance between the distance between the emitter layer and the base electrode and the area size of the side surface of the base layer for the base contact. If the base contact resistance and the junction capacitance can be suppressed, the size and size of the base layer 4 may be freely changed.

  Further, each contact (plug) 21E, 21B, and 21C and each wiring 22 connected thereto may be provided integrally. In addition, the formation method such as the layer configuration and material of each component layer may be changed. A graded layer may be provided between each layer, for example, between the base and the collector. However, in the case of the above-described example, the p-type improves the etching uniformity of the collector layer (however, the n-type may be used). ). In addition, light etching of the semiconductor layer may be performed before removing the base electrode in order to remove the damaged layer.

  The present invention is preferably applied to an HBT, but can be applied to a semiconductor device having another function such as a diode using a similar structure.

  The heterojunction semiconductor device and the manufacturing method thereof of the present invention can be applied to an ultrahigh-speed digital integrated circuit, a microwave analog integrated circuit, an optical signal amplification device, and the like.

FIG. 3 is a cross-sectional view taken along line A-A ′ and a cross-sectional view taken along line B-B ′ in FIG. 2 of the heterojunction bipolar transistor according to the first embodiment of the present invention. 2 is a plan view of the heterojunction bipolar transistor. FIG. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a heterojunction bipolar transistor. It is sectional drawing of the heterojunction bipolar transistor by the 2nd Embodiment of this invention. It is sectional drawing of the heterojunction bipolar transistor by the 3rd Embodiment of this invention. It is sectional drawing of the heterojunction bipolar transistor by the 4th Embodiment of this invention. It is sectional drawing (A) which shows an example of the heterojunction bipolar transistor by a prior art example, and sectional drawing (B) which shows another example. FIG. 6 is a cross-sectional view (A) showing another example of the heterojunction bipolar transistor and a cross-sectional view (B) showing still another example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2a ... Subcollector material, 2 ... Subcollector layer, 3a ... Collector material,
3 ... collector layer, 4a ... base material, 4 ... base layer, 5a ... emitter material, 5 ... emitter layer, 6a ... emitter cap material, 6 ... emitter cap layer, 7a ... emitter electrode material,
7 ... Emitter electrode, 8 ... Resist, 9a ... Organic insulating material, 9A, 9B ... Organic insulating film,
10, 11, 13, 16 ... resist,
14a, 14b, 15a, 15b, 15c, 18 ... opening, 12a base electrode material,
12 ... Base electrode, 17 ... Collector electrode, 19 ... Organic insulating layer,
21B: Base contact (plug), 21C: Collector contact (plug),
21E ... Emitter contact (plug), 22 ... Wiring, 23 ... Base lead-out part,
24a, 24b, 24c, 24d ... heterojunction bipolar transistors

Claims (23)

  A heterojunction type semiconductor device having a laminate comprising at least a collector layer, a base layer, and an emitter layer, wherein a base electrode is formed on at least a side surface of the base layer.   The heterojunction semiconductor device according to claim 1, wherein the base layer is formed in the same pattern and size as the emitter electrode in a self-aligning manner.   The emitter cap layer directly below the emitter electrode and the emitter layer have an undercut shape with respect to the emitter electrode, and the collector layer immediately below the base layer has an undercut shape with respect to the base layer. The heterojunction semiconductor device according to claim 1, wherein the cut portion is filled with an insulator.   The sub-collector layer immediately below the collector electrode and the collector layer have an undercut shape with respect to the collector electrode, and the emitter layer immediately below the base layer has an undercut shape with respect to the base layer. The heterojunction semiconductor device according to claim 1, wherein the cut portion is filled with an insulator.   The heterojunction semiconductor device according to claim 3, wherein the insulator is made of an organic insulating film.   The heterojunction type according to claim 3 or 4, wherein a surface of the base layer on the emitter electrode side is partially exposed around the insulator, and the base electrode is formed from the exposed surface to the side surface. Semiconductor device.   5. The heterojunction semiconductor device according to claim 3, wherein the base electrode is formed in contact with the insulator, and the base electrode extends to the base electrode extraction portion on the insulator.   The heterojunction semiconductor device according to claim 1, wherein at least a constituent layer of the stacked body is made of a semiconductor lattice-matched to indium phosphide.   The heterojunction semiconductor device according to claim 1, wherein an orientation of a side of the emitter layer or the collector layer is parallel to a direction equivalent to a <010> direction.   The heterojunction semiconductor device according to claim 1, wherein the stacked body has an emitter ledge structure. In a method of manufacturing a heterojunction bipolar semiconductor device having a laminate composed of at least a collector layer, a base layer, and an emitter layer,
Laminating at least a collector layer constituent material layer, a base layer constituent material layer, and an emitter layer constituent material layer;
Processing the base layer constituent material layer to form the base layer;
Forming a base electrode on at least a side surface of the base layer. A method of manufacturing a heterojunction semiconductor device, comprising:   The method of manufacturing a heterojunction semiconductor device according to claim 11, wherein an adjacent layer of the base layer is processed into an undercut shape, and an insulator is filled in the undercut portion.   The method of manufacturing a heterojunction semiconductor device according to claim 11, wherein the base layer is formed in a self-aligned manner in the same pattern and size as the emitter electrode.   Processing the emitter cap layer immediately below the emitter electrode and the emitter layer into an undercut shape with respect to the emitter electrode, processing the collector layer immediately below the base layer into an undercut shape with respect to the base layer, The method of manufacturing a heterojunction semiconductor device according to claim 12, wherein the undercut portion is filled with the insulator.   Processing the sub-collector layer immediately below the collector electrode and the collector layer into an undercut shape with respect to the collector electrode, processing the emitter layer immediately below the base layer into an undercut shape with respect to the base layer, The method of manufacturing a heterojunction semiconductor device according to claim 12, wherein the insulator is filled in an undercut portion.   The method of manufacturing a heterojunction semiconductor device according to claim 14, wherein the insulator is formed of an organic insulating film.   16. The heterojunction semiconductor device according to claim 14, wherein a surface of the base layer on the emitter electrode side is partially exposed around the insulator, and the base electrode is formed from the exposed surface to the side surface. Manufacturing method.   The method of manufacturing a heterojunction semiconductor device according to claim 14, wherein the base electrode is formed in contact with the insulator, and the base electrode is extended to the base electrode extraction portion on the insulator. Processing the emitter cap layer directly below the emitter electrode and the emitter layer into the undercut shape;
Protecting this undercut with a resist,
After forming the base layer, processing the collector layer immediately below the undercut shape;
After removing the resist, applying an insulator over the entire surface;
Etching back and etching until at least the side surface of the base layer is exposed;
Applying isotropic etching to the insulator filled in the side surface of the emitter layer so as to prevent the semiconductor layer from being exposed;
The method of manufacturing a heterojunction semiconductor device according to claim 14, further comprising a step of forming the base electrode by performing a self-aligned lift-off after depositing the base electrode constituent material. Processing the sub-collector layer and the collector layer immediately below the collector electrode into the undercut shape;
Protecting this undercut with a resist,
After forming the base layer, processing the emitter layer immediately below the undercut shape;
After removing the resist, applying an insulator over the entire surface;
Etching back and etching until at least the side surface of the base layer is exposed;
Applying a side etch to the insulator filled in the side surface of the collector layer by isotropic etching to such an extent that the semiconductor layer is not exposed;
The method of manufacturing a heterojunction semiconductor device according to claim 15, further comprising: forming the base electrode by performing a self-aligned lift-off after depositing the base electrode constituent material.   The method of manufacturing a heterojunction semiconductor device according to claim 11, wherein at least a constituent layer of the stacked body is made of a semiconductor lattice-matched with indium phosphide.   The method of manufacturing a heterojunction semiconductor device according to claim 11, wherein an orientation of a side of the emitter layer or the collector layer is parallel to a direction equivalent to a <010> direction.   The method of manufacturing a heterojunction semiconductor device according to claim 11, wherein the stacked body is formed in an emitter ledge structure.

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