JP2008147245A - Deterioration diagnostic circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a deterioration diagnostic circuit formed of a simple circuit and a semiconductor integrated circuit to which the deterioration diagnostic circuit formed of an IP core is integrated. <P>SOLUTION: The deterioration diagnostic circuit 13a can forecast the period when a failure occurs due to aging deterioration of an actual circuit 12 provided within the semiconductor integrated circuit 10a. This deterioration diagnostic circuit 13a includes a signal generating circuit 14 for outputting a pulse signal at the constant frequency, a deterioration diagnosis object circuit 16a that is provided in the same period as the actual circuit 12 to pass and output a pulse signal outputted from the signal generating circuit 14, and a deterioration determination circuit 18 that is activated with a delay for a predetermined time from rise of the pulse signal outputted from the signal generating circuit 14 to generate a clock signal having the same frequency as the pulse signal outputted from the signal generating circuit 14 and also to output determination result to at least one of the actual circuit and external circuit by determining whether deterioration is generated or not in the deterioration diagnosis object circuit 16a through comparison of the timings of the pulse signal outputted from the deterioration diagnosis object circuit 16 and the clock signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a deterioration diagnosis circuit that predicts a failure time due to aged deterioration of an actual circuit provided in a semiconductor integrated circuit.

  The failure occurrence rate of a general semiconductor integrated circuit over time has a tendency like a failure rate curve (so-called “bathtub curve”) shown in FIG. This bathtub curve is divided into three periods according to the failure occurrence rate, and is called an initial failure period, an accidental failure period, and a friction failure period, respectively.

  Conventionally, as a measure to reduce the failure rate of semiconductor integrated circuits, for failures that occur during the initial failure period, the failure is caused to operate under a high load condition with respect to the standard of temperature condition and voltage condition, and the initial failure due to the passage of time is accelerated. In other words, a so-called burn-in method is adopted in which defective products are eliminated.

  However, the method for the failure occurring in the initial failure period is not effective for the failure occurring in the friction failure period in which the probability of occurrence increases due to deterioration of the semiconductor integrated circuit.

  If the failures that occur during the friction failure period are classified, the following three cases can be considered. The first is breakdown voltage degradation and short-circuiting due to a failure of the oxide film (insulating film). The second is the opening, short circuit, and increased resistance due to voids due to corrosion and electromigration of wiring, via contacts, and through holes. The third is high resistance and disconnection due to the growth of the metal compound at the junction of wire bonding.

  By suppressing the occurrence of a failure in this friction failure period, the MTBF (Mean Failure Interval) is extended and the quality of the semiconductor integrated circuit can be improved.

  As a method of determining a failure due to deterioration of a semiconductor integrated circuit, a plurality of devices having the same function as a functional circuit are provided in the same semiconductor chip, and the output signal of the functional circuit is compared with an expected value, resulting in a mismatch. In some cases, there is known a semiconductor device that determines that a functional circuit having a mismatch has failed (see, for example, Patent Document 1). When it is determined that a failure has occurred, it is possible to achieve a long life by selecting the output of the functional circuit in which no failure has occurred.

  In addition, a deterioration check circuit is provided separately. The deterioration check circuit is subjected to a larger load than the actual circuit, and the deterioration progress measurement sensor measures the electrical characteristics of the deterioration check circuit to determine the deterioration progress. A semiconductor device to be grasped is known (for example, see Patent Document 2). Since the degradation check circuit is given a large load, the degradation progresses faster than the actual circuit, and the degradation of the actual circuit can be predicted quickly.

  FIG. 10 shows a configuration of a semiconductor device disclosed in Patent Document 2. The semiconductor device 1 includes an integrated circuit 3 that performs various data processing and the like including an actual circuit element 2 that deteriorates with time due to an increase in usage frequency or due to the surrounding environment, and input / output of data to / from the integrated circuit 3. A plurality of input / output terminals 4, a deterioration check circuit element 5 having the same layered structure as the actual circuit element 2, and a maximum use load circuit 6 that applies a use load of the actual circuit element 2 or more to the deterioration check circuit element 5; The sensor 7 for measuring the deterioration progress of the deterioration check circuit element 5 and the output terminal 8 for outputting a signal from the sensor 7 to the outside.

  Here, the same structure has the same cross-sectional area as the same laminated structure such that the actual circuit element 2 and the film quality, the stress state, the precipitation state of the additive, etc. are in substantially the same conditions with respect to deterioration over time. The structure which can simulate deterioration of the actual circuit element 2 is shown.

In the semiconductor device having the above-described configuration, the sensor 7 measures the progress of deterioration of the circuit element 5 for checking deterioration, so that the progress of deterioration of the actual circuit element 2 can be indirectly grasped. Therefore, for example, when performing maintenance, it is possible to know whether or not the semiconductor device can maintain the specifications until the next maintenance by observing the progress of deterioration of the circuit element 5 for deterioration check. It is possible to accurately determine the replacement time of the corresponding semiconductor device.
JP 2004-340877 A JP 7-128384 A

  However, the semiconductor device described in Patent Document 1 as described above has a problem in that the circuit scale increases because it is necessary to provide a plurality of circuits having the same function as the actual functional circuit of the semiconductor integrated circuit. In addition, when only a plurality of specific limited functional circuits are provided, the circuit that is the target of failure determination is only that specific part.

  Further, the semiconductor device described in Patent Document 2 as described above requires a circuit that gives a large use load that is not necessary for an actual circuit, and a sensor that determines deterioration (for example, a change in resistance value) as an analog value. However, there is a problem that the circuit becomes complicated and large-scale.

  The present invention solves the above-mentioned problems of the prior art, and provides a deterioration diagnosis circuit constituted by a simple circuit and a semiconductor integrated circuit incorporating an IP core deterioration diagnosis circuit. Is an issue.

  In order to solve the above-described problem, the deterioration diagnosis circuit according to the present invention is a deterioration diagnosis circuit for predicting a failure time due to aged deterioration of an actual circuit provided in a semiconductor integrated circuit. A signal generation circuit that outputs a pulse signal at a constant frequency; a deterioration diagnosis target circuit that is provided at the same time as the actual circuit and that outputs the pulse signal output by the signal generation circuit; and the signal generation A pulse signal output from the deterioration diagnosis target circuit, generating a clock signal that rises with a delay of a predetermined time from the rising edge of the pulse signal output by the circuit and has the same frequency as the pulse signal output by the signal generation circuit. And the timing of the clock signal are compared to determine whether or not the deterioration diagnosis target circuit has deteriorated. The results are characterized by comprising a determination circuit for outputting at least one of said actual circuit and the outside.

  According to a second aspect of the present invention, in the first aspect, the determination circuit causes the deterioration diagnosis target circuit to deteriorate when the pulse signal output by the deterioration diagnosis target circuit at the rising edge of the clock signal is at an L level. It is characterized in that it is determined that occurrence has occurred.

  According to a third aspect of the present invention, in the first or second aspect, the determination circuit has a predetermined time period from when the pulse signal output by the deterioration diagnosis target circuit rises to when the clock signal rises. In some cases, it is determined that the deterioration diagnosis target circuit has deteriorated.

  According to a fourth aspect of the present invention, in the first or second aspect, the determination circuit includes a time from a rise of the clock signal to a fall of the pulse signal output by the deterioration diagnosis target circuit within a predetermined time. If it is, it is determined that the deterioration diagnosis target circuit has deteriorated.

  According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the deterioration diagnosis target circuit is composed of a metal conductor wiring that deteriorates due to corrosion or oxidation over time. And

  The invention according to claim 6 is characterized in that, in claim 5, the metal conductor wiring is aluminum or copper wiring.

  A seventh aspect of the present invention is characterized in that, in the fifth or sixth aspect, the metal conductor wiring is wired near the actual circuit or inside the actual circuit.

  The invention according to claim 8 is the electronic device according to any one of claims 5 to 7, wherein the metal conductor wiring is routed longer than a shortest distance from the signal generation circuit to the determination circuit. It is characterized by.

  According to a ninth aspect of the present invention, in the method according to any one of the first to eighth aspects, the degradation diagnosis target circuit includes a via contact on a wiring, a buffer composed of a transistor, wire bonding, an aluminum electrode, and a lead. It is characterized by comprising at least one of the frames.

  A tenth aspect of the present invention is the electronic device according to any one of the fifth to ninth aspects, wherein the metal conductor wiring is routed around an outer periphery of the semiconductor integrated circuit and is folded and folded in the middle of the wiring. The metal conductor wiring is arranged in the vicinity of the metal conductor wiring before being folded back.

  According to an eleventh aspect of the present invention, in any one of the fifth to ninth aspects, the deterioration diagnosis target circuit includes a logic inversion circuit on a wiring, and the metal conductor wiring is formed on the semiconductor integrated circuit. The metal conductor wiring is routed around the outer periphery, folded back by the logic inversion circuit, and placed near the metal conductor wiring before being folded back.

  According to a twelfth aspect of the present invention, in any one of the fifth to ninth aspects, the deterioration diagnosis target circuit is constituted by a plurality of the metal conductor wirings having different thicknesses.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention is characterized in that the degradation diagnosis circuit according to any one of claims 1 to 12 is formed into an IP core, The deterioration diagnosis circuit is provided in an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) package.

  According to the first aspect of the present invention, since it is determined whether or not deterioration has occurred in the deterioration diagnosis target circuit based on a change in the transmission time of the pulse signal passing through the deterioration diagnosis target circuit, a simple circuit configuration Can provide a deterioration diagnosis circuit.

  According to the second aspect of the present invention, the deterioration is determined based on whether or not the pulse signal output from the deterioration diagnosis target circuit at the rising edge of the clock signal is at the L level. The deterioration diagnosis can be performed by detecting the change in the transmission time.

  According to the third aspect of the present invention, if the time from when the pulse signal output from the degradation diagnosis target circuit rises to when the clock signal rises is within a predetermined time, it is determined that degradation has occurred. Therefore, even if the pulse signal output by the degradation diagnosis target circuit at the rising edge of the clock signal is at the H level, degradation can be detected early as a setup violation.

  According to the fourth aspect of the present invention, it is determined that degradation has occurred when the time from when the clock signal rises to when the pulse signal output by the degradation diagnosis target circuit falls within a predetermined time. Therefore, even if the pulse signal output by the degradation diagnosis target circuit at the rising edge of the clock signal is at the H level, it can be detected early as a hold violation when a short circuit or the like occurs in the degradation diagnosis target circuit. .

  According to the fifth aspect of the present invention, since the metal conductor wiring that deteriorates due to corrosion or oxidation over time is used for the deterioration diagnosis target circuit, the deterioration of the metal conductor wiring can be examined. Moreover, when deterioration occurs, it can be estimated that the metal conductor wiring is the cause of the deterioration.

  According to the invention described in claim 6 of the present invention, since the metal conductor wiring is aluminum or copper, it is possible to predict the presence or absence of deterioration when wiring with aluminum or copper is performed in the actual circuit, and the deterioration. Can be identified.

  According to the seventh aspect of the present invention, since the metal conductor wiring is wired near or inside the actual circuit, the deterioration occurring in the actual circuit can be predicted with an early and high probability.

  According to the eighth aspect of the present invention, the metal conductor wiring is routed longer than the shortest distance from the signal generation circuit to the determination circuit, so that the signal transmission time becomes longer and the transmission of the metal conductor wiring becomes longer. If a delay occurs, it can be detected early. In addition, since a large area is routed in the semiconductor integrated circuit, it is possible to perform deterioration diagnosis for deterioration occurring in various places.

  According to the ninth aspect of the present invention, since at least one of via contact, transistor buffer, wire bonding, aluminum electrode, and lead frame is provided on the wiring, it can be applied to all parts in the semiconductor circuit. Deterioration diagnosis can be performed. Moreover, a deterioration factor and a place can be specified from the provided parts.

  According to the tenth aspect of the present invention, when the insulating silicon between the adjacent metal conductor wiring lines deteriorates and a short circuit occurs, the determination circuit can detect the deterioration of the silicon.

  According to the eleventh aspect of the present invention, since the logic is inverted by the logic inversion circuit, the two metal conductor wirings that are folded and close to each other have a potential difference. Accordingly, stress due to a potential difference is applied between adjacent metal conductor wiring lines to promote deterioration of insulating silicon, so that deterioration of silicon can be detected at an early stage.

  According to the twelfth aspect of the present invention, since the deterioration diagnosis target circuit is composed of a plurality of metal conductor wirings having different thicknesses, the metal conductor wiring is cut by the deterioration in the thin order, and the progress of the deterioration. Can be determined.

  According to the thirteenth aspect of the present invention, since the deterioration diagnosis circuit with the IP core is provided in the ASIC or FPGA package, the necessary deterioration diagnosis circuit can be easily selected, and the earlier Accurate deterioration diagnosis can be performed.

  Embodiments of a deterioration diagnosis circuit and a semiconductor integrated circuit according to the present invention will be described below in detail with reference to the drawings.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit 10a having a deterioration diagnosis circuit 13a according to the first embodiment of the present invention.

  First, the configuration of the present embodiment will be described. As shown in FIG. 1, the semiconductor integrated circuit 10a includes an actual circuit 12 and a deterioration diagnosis circuit 13a according to the present embodiment. The actual circuit 12 has a possibility of aging. The deterioration diagnosis circuit 13a includes a signal generation circuit 14, a deterioration diagnosis target circuit 16a, and a deterioration determination circuit 18.

  The deterioration diagnosis circuit 13a predicts a failure time due to aged deterioration of the actual circuit 12 provided in the semiconductor integrated circuit 10a. The signal generation circuit 14 outputs a pulse signal at a constant frequency to the degradation diagnosis target circuit 16a.

  The deterioration diagnosis target circuit 16a is provided at the same time as the actual circuit 12, passes the pulse signal output from the signal generation circuit 14, and outputs the pulse signal to the deterioration determination circuit 18. Since the deterioration diagnosis target circuit 16a is provided at the same time as the actual circuit 12, when the deterioration diagnosis target circuit 16a is deteriorated, the deterioration diagnosis circuit 13a causes the real circuit 12 to have a failure due to deterioration over time. Judge that there is a high probability that it has occurred.

  The degradation determination circuit 18 corresponds to the determination circuit of the present invention, and has the same frequency as the pulse signal that rises after a predetermined time from the rise of the pulse signal output by the signal generation circuit 14 and is output by the signal generation circuit 14. A clock signal is generated, and the timing of the pulse signal output from the degradation diagnosis target circuit 16a is compared with the timing of the clock signal to determine whether or not the degradation diagnosis target circuit 16a has deteriorated. Output to at least one of the actual circuit 12 and the outside.

  In this embodiment, the deterioration determination circuit 18 is connected to both the actual circuit 12 and the outside. The operation after the deterioration determination circuit 18 outputs the determination result to the actual circuit 12 or the outside may be any operation. For example, when the determination result sent to the outside detects deterioration, the user can be notified of the possibility of deterioration by a lamp or the like. When a determination result indicating deterioration is output to the actual circuit 12, the operation of the actual circuit 12 may be temporarily stopped or a maintenance time may be set.

  There are various methods for synchronizing the timing of the pulse signal output from the signal generation circuit 14 and the clock signal generated in the deterioration determination circuit 18, but the following method is considered as an example. It is assumed that a clock (not shown) is provided in the semiconductor integrated circuit 10 a and a second clock signal that is much faster than the clock signal generated in the deterioration determination circuit 18 is generated. A pulse signal is generated and output in the signal generation circuit 14 every 10 cycles of the second clock signal, and a clock signal is always generated in the deterioration determination circuit 18 after 3 cycles of the second clock signal. Then, the timing of the pulse signal and the clock signal generated in the deterioration determination circuit 18 can be synchronized. In this case, as long as there is no delay in the second clock signal itself, both signals have the same frequency and a rise time shift corresponding to three cycles of the second clock signal. Here, it is assumed that there are three cycles of the second clock signal, but it is necessary to adjust in accordance with the pulse signal transmission time in the degradation diagnosis target circuit 16a.

  Next, the operation of the deterioration diagnosis circuit 13a according to the first embodiment will be described. 2 and 3 are diagrams showing operation time charts of signals in the respective units. In this embodiment, the deterioration determination circuit 18 uses a D (Delay) type flip-flop for determination of deterioration. The D type flip-flop outputs the state of the signal input to the D terminal of the flip-flop as it is to the Q terminal when the clock signal rises (when it changes from L level to H level).

Signal generating circuit 14 generates and outputs a pulse signal at time t _1. Output pulse signal passes through the deterioration diagnosis target circuit 16a, is input to the deterioration determination circuit 18 at time t _2. It takes a predetermined time degradation diagnosis target circuit 16a to the pulse signal is transmitted, it takes the normal delay time T ₁ until the pulse signal is input from the output of the signal generating circuit 14 to the degradation judgment circuit 18.

  The ON time (H level time) of the pulse signal generated by the signal generation circuit 14 is a total period of the setup time + α and the hold time + β. Here, the setup time corresponds to the predetermined time of the present invention, and indicates the minimum necessary time from when the pulse signal is input to the flip-flop until the clock signal rises. The hold time corresponds to the predetermined time of the present invention, and indicates the minimum time required from the rise of the clock signal to the fall of the pulse signal input to the flip-flop.

  α and β are specific values of the degradation diagnosis target circuit 16a, and are obtained and set by calculation or empirical rules. By adjusting the time of α and β, it is possible to determine the criteria for deterioration diagnosis. When α and β are very short, the determination circuit 18 can detect deterioration with respect to an increase in delay time based on slight deterioration. Conversely, when α and β are long, the determination circuit 18 detects the deterioration only when the deterioration progresses and the delay time increases very long.

  Therefore, the signal generation circuit 14 has a function of adjusting the times α and β. This adjustment adjusts the margin for deterioration determination.

Deterioration determination circuit 18, the clock signal at time t ₃ rises are generated. From the time t ₂ of the pulse signal to the deterioration determining circuit 18 is inputted, the time until time t ₃ when the deterioration determination circuit 18 generates a clock signal is set-up time + alpha. Therefore, the deterioration determination circuit 18 needs to be set in advance so that the clock signal rises with a delay of the normal delay time T ₁ + setup time + α from the rise of the pulse signal output by the signal generation circuit 14.

At the rising edge of the clock signal at time t _3, the pulse signal input to the flip-flop in the deterioration determination circuit 18 is at the H level, so the flip-flop in the deterioration determination circuit 18 outputs an H level signal. If the normal state continues, the output signal of the flip-flop in the degradation determination circuit 18 is always at the H level.

  When the deterioration diagnosis target circuit 16a is deteriorated, a phenomenon in which the time for which the pulse signal input to the deterioration diagnosis target circuit 16a is transmitted through the deterioration diagnosis target circuit 16a is delayed or advanced appears. The cause when the pulse signal is delayed may be a high resistance due to a deterioration phenomenon of the semiconductor in the deterioration diagnosis target circuit 16a.

In FIG. 2, the operation when the pulse signal is delayed will be described. Signal generating circuit 14 generates and outputs a pulse signal at time t _4. Output pulse signal passes through the degradation diagnosis target circuit 16a, if normal state is input to the deterioration determination circuit 18 at time t _5. However, since degradation occurs in the degradation diagnosis target circuit 16a, a delay occurs in the transmission time of the pulse signal, and the time T from when the pulse signal is output by the signal generation circuit 14 until it is input to the degradation determination circuit 18 _2, longer than the normal delay time _{T 1.}

Therefore, at the rising edge of the clock signal at time t _6, since the pulse signal inputted to the flip-flop of the output by the deterioration diagnosis target circuit 16a in the deterioration determination circuit 18 is at L level, the flip-flop in the deterioration determination circuit 18 , An L level signal is output (time t ₇ ).

The deterioration determination circuit 18 performs latch determination on the output signal of the flip-flop and outputs a deterioration determination signal. Therefore, when the flip-flop outputs an L level signal even once, the deterioration determination circuit 18 continues to output an L level deterioration determination signal thereafter (time t ₇ ). That is, when the deterioration determination circuit 18 detects that deterioration has occurred in the deterioration diagnosis target circuit 16a, the deterioration determination circuit 18 outputs an L level deterioration determination signal. When the pulse signal output by the deterioration diagnosis target circuit 16a at the time of rising is at the L level, it is determined that the deterioration diagnosis target circuit 16a has deteriorated.

  Further, when a setup violation or a hold violation occurs at the rising edge of the clock signal, it can be determined that the deterioration diagnosis target circuit 16a has deteriorated. The operation in this case will be described with reference to FIG.

When no deterioration has occurred in the deterioration diagnosis target circuit 16a, the pulse signal requires a normal delay time T ₁ ′ from being output by the signal generation circuit 14 until being input to the deterioration determination circuit 18. The operation of each unit at times t ₁ ′, t ₂ ′, and t ₃ ′ is the same as the operation of each unit at times t ₁ , t ₂ , and t ₃ in FIG.

The signal generation circuit 14 generates and outputs a pulse signal at time t ₄ ′. Output pulse signal passes through the degradation diagnosis target circuit 16a, if normal state is input to the deterioration determination circuit 18 at time t _{5 '.} However, since degradation occurs in the degradation diagnosis target circuit 16a, a delay occurs in the transmission time of the pulse signal, and the time T from when the pulse signal is output by the signal generation circuit 14 until it is input to the degradation determination circuit 18 ₂ ', normal delay time _{T 1'} longer than.

However, the pulse signal output by the deterioration diagnosis target circuit 16a is still clock signal when the input to the flip-flops in the degradation judgment circuit 18 at time t _{6 'does} not rise. Thereafter, when the clock signal rises at time t ₇ ′, the pulse signal output by the deterioration diagnosis target circuit 16a and input to the flip-flop in the deterioration determination circuit 18 is at the H level.

However, since the time from the time t ₆ ′ when the pulse signal is input to the flip-flop in the deterioration determination circuit 18 to the time t ₇ ′ when the clock signal rises is shorter than the setup time, a setup violation occurs. At this time, the output signal of the flip-flop becomes a metastable. Here, metastable means that the output signal becomes unstable when the setup time or hold time is not observed in the input signal of the flip-flop.

The deterioration determination circuit 18 performs latch determination on the output signal of the flip-flop and outputs a deterioration determination signal. Therefore, when the output signal of the flip-flop becomes a metastable and outputs an L level signal even once, the deterioration determination circuit 18 continues to output an L level deterioration determination signal thereafter (time t ₈ ′).

That is, when the time from when the pulse signal output from the degradation diagnosis target circuit 16a rises to when the clock signal rises is within a predetermined time (setup time), the degradation determination circuit 18 degrades the degradation diagnosis target circuit 16a. It is determined that the signal has occurred, and an L level deterioration determination signal is output. Conversely, a short circuit or the like may occur in the deterioration diagnosis target circuit 16a, and the pulse signal transmission time may be short. In this case, a hold violation occurs and a metastable occurs as in the case of a setup violation. That is, when the time from when the clock signal rises to when the pulse signal output by the degradation diagnosis target circuit 16a falls is within a predetermined time (hold time), the degradation determination circuit 18 It is determined that deterioration has occurred, and an L level deterioration determination signal is output.

  As described above, according to the deterioration diagnosis circuit 13a according to the first embodiment of the present invention, whether deterioration has occurred in the deterioration diagnosis target circuit 16a based on the change in the transmission time of the pulse signal passing through the deterioration diagnosis target circuit 16a. Therefore, it is possible to provide the deterioration diagnosis circuit 13a with a simple circuit configuration.

  Further, since the deterioration is determined based on whether or not the pulse signal output from the deterioration diagnosis target circuit 16a at the rising edge of the clock signal is at the L level, a change in the signal transmission time is reliably detected with a simple configuration, Deterioration diagnosis can be performed.

  Further, when the time from when the pulse signal output from the degradation diagnosis target circuit 16a rises to when the clock signal rises is within a predetermined time, it is determined that degradation has occurred. Even if the pulse signal output by the circuit is at the H level, it is possible to detect deterioration early as a setup violation.

  On the other hand, if the time from when the clock signal rises to when the pulse signal output by the degradation diagnosis target circuit 16a falls is within a predetermined time, it is determined that degradation has occurred, so degradation diagnosis is performed when the clock signal rises. Even if the pulse signal output by the target circuit is at the H level, it can be detected early as a hold violation when a short circuit or the like occurs in the degradation diagnosis target circuit 16a.

  FIG. 4 is a block diagram showing the configuration of the semiconductor integrated circuit 10b having the deterioration diagnosis circuit 13b according to the second embodiment of the present invention. As a difference from the configuration of the first embodiment, the degradation diagnosis target circuit 16b is configured by a copper wiring 20 which is a metal conductor wiring that deteriorates due to corrosion or oxidation over time. In this embodiment, the copper wiring 20 is used, but an aluminum wiring may be used.

  Further, the copper wiring 20 is provided in the vicinity of the actual circuit 12 and extending around the actual circuit 12 for a long time. Therefore, when the deterioration due to oxidation or the like occurs in the actual circuit 12, since the copper wiring 20 is provided near the actual circuit 12, the deterioration due to oxidation or the like similarly occurs in the copper wiring 20, and the deterioration is discovered at an early stage. can do. The copper wiring 20 can be wired so as to pass through the inside of the actual circuit 12, and the same effect can be expected.

  Furthermore, since the copper wiring 20 is routed longer than the shortest distance from the signal generation circuit 14 to the deterioration determination circuit 18, the signal transmission time becomes longer, and when a transmission delay occurs earlier, Can be found. Further, since the copper wiring 20 is routed so as to occupy a large area in the semiconductor integrated circuit 10b, it is possible to perform deterioration diagnosis for deterioration occurring in various places.

  On the copper wiring 20, a via contact 22 that performs interlayer connection of the wiring and a buffer 24 including a transistor are provided. In the present embodiment, both are provided, but it is not always necessary to install both, and either one or both may not be installed.

  Next, the operation of the deterioration diagnosis circuit 13b according to the second embodiment will be described. The pulse signal output from the signal generation circuit 14 is transmitted to the deterioration diagnosis target circuit 16b and input to the deterioration determination circuit 18, as in the first embodiment. In the degradation diagnosis target circuit 16b, there is a possibility that the copper wiring 20 may have increased resistance or disconnection due to voids due to electromigration, or short circuit or disconnection due to corrosion. In addition to the deterioration similar to that of the copper wiring 20, the via contact 22 may be opened due to the deterioration of the impurity due to the mixing of the impurity. Further, the buffer 24 composed of transistors may lead to malfunction due to dielectric breakdown of the gate oxide film.

  As a result of the deterioration as described above, the transmission time of the pulse signal output from the signal generation circuit 14 becomes longer or shorter in the deterioration diagnosis target circuit 16b. The operation of the deterioration determination circuit 18 is the same as that in the first embodiment.

  As described above, according to the deterioration diagnosis circuit 13b according to the second embodiment of the present invention, the copper wiring 20, which is a metal conductor wiring that deteriorates due to corrosion or oxidation with time, is used for the deterioration diagnosis target circuit 16b. The deterioration of the copper wiring 20 can be examined. Moreover, when deterioration occurs, it can be estimated that the copper wiring 20 is the cause of the deterioration.

  Moreover, since the copper wiring 20 is used, when the copper wiring is performed in the actual circuit 12, it is possible to predict the presence or absence of deterioration and to specify the cause of the deterioration.

  Furthermore, since the copper wiring 20 is wired in the vicinity of the actual circuit 12, the deterioration occurring in the actual circuit 12 can be predicted with an early and high probability.

  On the other hand, since the copper wiring 20 is routed longer than the shortest distance from the signal generation circuit 14 to the deterioration determination circuit 18, the signal transmission time becomes longer and the transmission delay occurs earlier. Can be found. Further, since the copper wiring 20 is routed so as to occupy a large area in the semiconductor integrated circuit 10b, it is possible to perform deterioration diagnosis for deterioration occurring in various places.

  Further, since the via contact 22 and the buffer 24 composed of a transistor are provided on the wiring, it is determined that the via contact or the buffer in the actual circuit 12 is a deterioration factor when the deterioration occurs in the deterioration diagnosis target circuit 16b. In addition, the location of deterioration can be specified.

  Next, FIG. 5 is a block diagram showing a configuration of the semiconductor integrated circuit 10c having the deterioration diagnosis circuit 13c according to the third embodiment of the present invention. The difference from the configuration of the second embodiment is that the wire bonding 28, the aluminum electrode 26 connected to one end of the wire bonding 28 and the signal generation circuit 14, and the wire bonding 28 are arranged on the wiring of the degradation diagnosis target circuit 16 c. The lead frame 30 connected to the end is provided. In this embodiment, all of the wire bonding 28, the aluminum electrode 26, and the lead frame 30 are provided. However, it is not always necessary to provide all of them, and at least one of them may be provided.

  The lead frame 30 is connected to the external connection wiring 32. The external connection wiring 32 may be a wiring on a printed board provided in advance, for example. The other end of the external connection wiring 32 is connected to the deterioration determination circuit 18 through another wire bonding and an aluminum electrode.

  Next, the operation of the deterioration diagnosis circuit 13c according to the third embodiment will be described. The pulse signal output from the signal generation circuit 14 is transmitted to the deterioration diagnosis target circuit 16c and input to the deterioration determination circuit 18, as in the first embodiment. In the deterioration diagnosis target circuit 16c, there is a possibility that the aluminum electrode 26, which is the surface electrode of the semiconductor integrated circuit 10c, or the joint portion between the lead frame 30 of the package and the wire bonding 28 may deteriorate. When deterioration occurs, high resistance and disconnection occur due to growth of the metal compound.

  As a result of the deterioration as described above, the transmission time of the pulse signal output from the signal generation circuit 14 becomes longer or shorter in the deterioration diagnosis target circuit 16c. The operation of the deterioration determination circuit 18 is the same as that in the first embodiment.

  As described above, according to the deterioration diagnosis circuit 13c according to the third embodiment of the present invention, the aluminum electrode 26, the wire bonding 28, and the lead frame 30 are provided on the wiring. When deterioration occurs, it can be specified that any one of the aluminum electrode 26, the wire bonding 28, and the lead frame 30 in the actual circuit 12 is a deterioration factor, and the deterioration location can also be specified.

  Next, FIG. 6 is a block diagram showing a configuration of the semiconductor integrated circuit 10d having the deterioration diagnosis circuit 13d according to the fourth embodiment of the present invention. The difference from the configuration of the third embodiment is that the degradation diagnosis target circuit 16d has a logic inversion circuit 34 that inverts and outputs the logic input on the wiring. The copper wiring 20 is routed around the semiconductor integrated circuit 10d so as to surround the actual circuit 12 and the deterioration diagnosis circuit 13d. The copper wiring 20 is folded back by the logic inversion circuit 34. It is arranged close to the copper wiring 20 before being folded.

  Note that the logic inversion circuit 34 is not always essential. If the logic inversion circuit 34 is not provided, the copper wiring 20 is routed around the semiconductor integrated circuit 10d so as to surround the actual circuit 12 and the deterioration diagnosis circuit 13d, and is also folded and folded in the middle of the wiring. The copper wiring 20 is disposed in the vicinity of the copper wiring 20 before being folded back.

  Next, the operation of the deterioration diagnosis circuit 13d according to the fourth embodiment will be described. The pulse signal output from the signal generation circuit 14 is transmitted to the deterioration diagnosis target circuit 16d and input to the deterioration determination circuit 18, as in the first embodiment. In the degradation diagnosis target circuit 16d, contraction stress is applied to the semiconductor integrated circuit 10d in a temperature cycle environment, so that a wiring slide phenomenon occurs particularly at the corner portion of the semiconductor integrated circuit 10d, and the copper wiring 20 is broken such as a crack. The semiconductor integrated circuit 10d generally uses a resin-encapsulated package. This package gets into moisture over time. In particular, moisture entering from the interface between the resin and the lead frame becomes a corrosive aqueous solution containing impurities adhering to the package surface, entering from the periphery of the semiconductor integrated circuit 10d, and corroding the aluminum wiring or the copper wiring 20.

  Therefore, since the copper wiring 20 is disposed on the outer periphery of the semiconductor integrated circuit 10d, when the deterioration due to the disconnection due to the sliding phenomenon occurring in the corner portion or the corrosion due to the entering moisture occurs, the deterioration determination circuit 18 Degradation can be detected. The logic circuit 34 inverts the logic of the input signal. Therefore, since the logic of the pulse signal input to the copper wiring 20 is inverted before and after being folded by the logic inversion circuit 34, a potential difference is generated between the two adjacent copper wirings 20. The potential difference promotes the deterioration of the insulating silicon between the two copper wirings 20. Therefore, the deterioration of the short circuit between adjacent wirings is detected at an early stage. The operation of the deterioration determination circuit 18 is the same as that in the first embodiment.

  Further, even if the logic inversion circuit 34 is not provided, stress due to a potential difference is not applied between two adjacent copper wirings 20, but when a short circuit occurs, the pulse signal is subject to deterioration diagnosis earlier than usual. Since the signal is transmitted through the circuit 16d, the deterioration determination circuit 18 can detect the deterioration.

  As described above, according to the deterioration diagnosis circuit 13d according to the fourth embodiment of the present invention, the logic is inverted by the logic inversion circuit 34. Therefore, the two copper wirings 20 that are folded and close to each other have a potential difference. Therefore, stress due to a potential difference is applied between adjacent copper wirings 20 and the deterioration of the insulating silicon is promoted, so that the deterioration of the silicon can be found at an early stage. Even if there is no logic inversion circuit 34, it is possible to detect a short circuit between adjacent copper wirings 20 for the reason described above.

  The copper wiring 20 is disposed on the outer periphery of the semiconductor integrated circuit 10d. Therefore, when the deterioration based on the disconnection due to the slide phenomenon occurring in the corner portion or the corrosion due to the entering moisture occurs, the deterioration determination circuit 18 can detect the deterioration.

  Next, FIG. 7 is a block diagram showing a configuration of the semiconductor integrated circuit 10e having the deterioration diagnosis circuit 13e according to the fifth embodiment of the present invention. As a difference from the configuration of the fourth embodiment, the deterioration diagnosis target circuit 16e is configured by a plurality of wirings 36 (36-1 to 36-n) having different thicknesses. When the deterioration determination circuit 18 determines deterioration using flip-flops, the deterioration determination circuit 18 has the same number of flip-flops as the number n of the plurality of wirings 36 (36-1 to 36-n) having different thicknesses. Must be connected to each wiring.

  Next, the operation of the deterioration diagnosis circuit 13e according to the fifth embodiment will be described. The pulse signal output from the signal generation circuit 14 is transmitted to the deterioration diagnosis target circuit 16e and input to the deterioration determination circuit 18, as in the first embodiment. The plurality of wirings 36 (36-1 to 36-n) having different thicknesses are disconnected in order of narrowness due to aging deterioration. The degradation determination circuit 18 continues to receive an L level signal without inputting a pulse signal when a disconnection occurs in any of the plurality of wirings 36 (36-1 to 36-n) having different thicknesses. Which wiring is deteriorated is determined. The operation of the deterioration determination circuit 18 is the same as that in the first embodiment. Further, the deterioration determination circuit 18 determines which wiring has deteriorated, and then outputs the determination result to the actual circuit 12 and the outside.

  As described above, according to the deterioration diagnosis circuit 13e according to the fifth embodiment of the present invention, the deterioration diagnosis target circuit 16e is composed of a plurality of wirings 36 (36-1 to 36-n) having different thicknesses. Therefore, the deterioration determination circuit 18 can determine the progress of deterioration by determining a plurality of wires individually.

  Next, FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit 10f according to the sixth embodiment of the present invention. The semiconductor integrated circuit 10f is configured by an ASIC or FPGA package, and includes an actual circuit 12, a deterioration diagnosis target circuit 16f, a deterioration diagnosis target circuit 16g, a deterioration diagnosis IP core 38, and a deterioration diagnosis IP core 40. In any case, arbitrary processing can be performed by writing a large-scale functional block obtained by programming an IP core called processing with many needs.

  The actual circuit 12 a has an IP core that is a functional block that performs specific processing, such as an arithmetic device IP core 42, an analog IP core 44, and a communication IP core 46.

  Further, the signal generation circuit 14 and the deterioration determination circuit 18 in the deterioration diagnosis circuits 13a to 13e described in detail in the first to fifth embodiments are IP cores, and are deteriorated in the semiconductor integrated circuit 10f which is an ASIC or FPGA package. The diagnostic IP core 38 and the degradation diagnostic IP core 40 are provided. There may be one or more deterioration diagnosis IP cores, and in this embodiment, the deterioration diagnosis IP core 38 and the deterioration diagnosis IP core 40 are provided.

  The deterioration diagnosis IP core 38 determines whether or not deterioration has occurred in the deterioration diagnosis target circuit 16f provided in the vicinity of the actual circuit 12 as described in the second embodiment.

  The deterioration diagnosis IP core 40 determines whether or not deterioration has occurred in the deterioration diagnosis target circuit 16g provided on the outer periphery of the semiconductor integrated circuit 10d as described in the fourth embodiment.

  Next, the operation of the semiconductor integrated circuit 10f according to the sixth embodiment will be described. In the deterioration diagnosis IP core 38 and the deterioration diagnosis IP core 40, parameters such as normal delay information are set in accordance with the ASIC or FPGA package, respectively. In addition, information on easily deteriorated portions for each package is registered. The user selects a necessary deterioration diagnosis IP core according to a place where diagnosis is considered necessary. Alternatively, the actual circuit 12a automatically selects.

  As described above, according to the semiconductor integrated circuit 10f according to the form of the sixth embodiment of the present invention, the deterioration diagnosis circuit formed into the IP core is provided in the ASIC or FPGA package, which is suitable for each ASIC or FPGA package. A deterioration diagnosis IP core can be selected and configured, and earlier and more accurate deterioration diagnosis can be realized.

  The degradation diagnosis circuit and the semiconductor integrated circuit according to the present invention can be used for a semiconductor integrated circuit having a circuit that causes a failure due to aging degradation.

It is a block diagram which shows the structure of the semiconductor integrated circuit which has a deterioration diagnostic circuit of the form of Example 1 of this invention. It is a time chart which shows operation | movement of the deterioration diagnostic circuit of the form of Example 1 of this invention. It is a time chart which shows operation | movement of the deterioration diagnostic circuit of the form of Example 1 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which has a deterioration diagnostic circuit of the form of Example 2 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which has a deterioration diagnostic circuit of the form of Example 3 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which has a deterioration diagnostic circuit of the form of Example 4 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which has a deterioration diagnostic circuit of the form of Example 5 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit of the form of Example 6 of this invention. It is a figure which shows the failure occurrence rate with respect to time passage of a general semiconductor integrated circuit. It is a block diagram which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Actual circuit element 3 Integrated circuit 4 Input / output terminal 5 Deterioration check circuit element 6 Maximum load circuit 7 Deterioration progress measurement sensor 8 Output terminals 10a, 10b, 10c, 10d, 10e, 10f Semiconductor integrated circuit 12, 12a Actual circuits 13a, 13b, 13c, 13d, 13e Deterioration diagnosis circuit 14 Signal generation circuits 16a, 16b, 16c, 16d, 16e, 16f, 16g Degradation diagnosis target circuit 18 Degradation determination circuit 20 Copper wiring 22 Via contact 24 Buffer 26 Aluminum Electrode 28 Wire bonding 30 Lead frame 32 External connection wiring 34 Logic inversion circuits 36-1 to 36 -n Wirings 38 and 40 having different thicknesses Degradation diagnosis IP core 42 Computing device IP core 44 Analog IP core 46 Communication IP core

Claims (13)

A deterioration diagnosis circuit for predicting a failure time due to aging of an actual circuit provided in a semiconductor integrated circuit,
A signal generation circuit that outputs a pulse signal at a constant frequency;
A deterioration diagnosis target circuit that is provided at the same time as the actual circuit and outputs a pulse signal output by the signal generation circuit;
A clock signal that rises after a predetermined time from the rising edge of the pulse signal output by the signal generation circuit and has the same frequency as the pulse signal output by the signal generation circuit is generated, and is output by the deterioration diagnosis target circuit. A determination circuit that compares the timing of the pulse signal and the timing of the clock signal to determine whether or not the degradation of the degradation diagnosis target circuit has occurred, and outputs a determination result to at least one of the actual circuit and the outside When,
A deterioration diagnosis circuit comprising:   The determination circuit determines that the deterioration of the deterioration diagnosis target circuit has occurred when the pulse signal output by the deterioration diagnosis target circuit at the rising edge of the clock signal is at an L level. 1. The deterioration diagnosis circuit according to 1.   The determination circuit determines that the deterioration of the deterioration diagnosis target circuit has occurred when the time from when the pulse signal output by the deterioration diagnosis target circuit rises to when the clock signal rises is within a predetermined time. 3. A deterioration diagnosis circuit according to claim 1, wherein the deterioration diagnosis circuit is characterized in that:   The determination circuit determines that the deterioration of the deterioration diagnosis target circuit has occurred when the time from the rise of the clock signal to the fall of the pulse signal output by the deterioration diagnosis target circuit is within a predetermined time. The deterioration diagnosis circuit according to claim 1, wherein the deterioration diagnosis circuit is provided.   5. The deterioration diagnosis circuit according to claim 1, wherein the deterioration diagnosis target circuit includes a metal conductor wiring that deteriorates due to corrosion or oxidation over time.   6. The deterioration diagnosis circuit according to claim 5, wherein the metal conductor wiring is aluminum or copper wiring.   The degradation diagnosis circuit according to claim 5 or 6, wherein the metal conductor wiring is wired near or inside the actual circuit.   8. The deterioration diagnosis circuit according to claim 5, wherein the metal conductor wiring is routed longer than a shortest distance from the signal generation circuit to the determination circuit.   9. The deterioration diagnosis target circuit includes at least one of a via contact, a transistor buffer, wire bonding, an aluminum electrode, and a lead frame on the wiring. 2. The deterioration diagnosis circuit according to item 1.   The metal conductor wiring is routed around the periphery of the semiconductor integrated circuit, is folded in the middle of the wiring, and is disposed in the vicinity of the metal conductor wiring before the folded metal conductor wiring is folded. 10. The deterioration diagnosis circuit according to claim 5, wherein the deterioration diagnosis circuit is characterized in that: The degradation diagnosis target circuit has a logic inversion circuit on the wiring,
The metal conductor wiring is routed around an outer periphery of the semiconductor integrated circuit, is folded by the logic inversion circuit, and is disposed adjacent to the metal conductor wiring before the folded metal conductor wiring is folded. 10. The deterioration diagnosis circuit according to claim 5, wherein the deterioration diagnosis circuit is any one of claims 5 to 9.   The deterioration diagnosis circuit according to any one of claims 5 to 9, wherein the deterioration diagnosis target circuit includes a plurality of the metal conductor wires having different thicknesses.   13. The deterioration diagnosis circuit according to claim 1 is made into an IP core, and the deterioration diagnosis circuit that is made into an IP core is packaged in an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). A semiconductor integrated circuit comprising:

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