JP2001296334A - Integrated circuit and failure detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit and a failure detection method in which the scan test of a CMOS integrated circuit and an IDDQ test can be executed. SOLUTION: In the integrated circuit, shift-mode connections in which all flip-flops at the inside are connected in series can be selected, and signals are exchanged with the outside by an input/output buffer. A scan control circuit 11 sets the direction of an input/output buffer circuit 31 to an output in the shift mode of the scan test. Thereby, the generation of a floating state is prevented, and the IDDQ test by the measurement of a power-supply current can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit and a method for detecting a failure thereof, and more particularly, to a CMOS integrated circuit and a method for detecting a failure which can easily detect a failure based on a power supply current value.

[0002]

2. Description of the Related Art In an integrated circuit such as a CMOS, a physical failure may occur in a manufacturing process. Therefore, an integrated circuit needs a test to detect a failure. As a method of detecting a failure of the integrated circuit, the integrated circuit is configured in advance so that it can be changed to a scan circuit configuration in which all the flip-flops in the integrated circuit are serially chain-connected by setting separately from the original function of the integrated circuit. After setting the test values to all the flip-flops in the normal configuration, change the setting to a chain connection configuration and apply a clock to the flip-flops to sequentially shift the set values, There is a method based on a scan test for monitoring a signal output from the flip-flop.

[0003] The state when all flip-flops are set to a test value is called a capture mode, and the state when a flip-flop is clocked and shifted sequentially is called a shift mode.

Referring to FIG. 7, a conventional integrated circuit has a main circuit 90, a scan control circuit 10, an input / output buffer control circuit 20, and an input / output buffer circuit 30.

[0005] The main circuit 90 is a circuit for realizing the original function of the integrated circuit, and has a combinational circuit 91 and a sequential circuit 92. However, there is no clear boundary between the combinational circuit 91 and the sequential circuit 92, and the combinational circuit 91 is a set of various gate elements in the main circuit 90, and the sequential circuit 92 is a flip-flop FF in the main circuit 90. It is a set of _{1 to} FF _n0 .

[0006] The sequential circuit 92 can be changed to a scan circuit configuration by setting. The scan circuit configuration is a connection configuration used only in the shift mode of the scan test. All flip-flops FF _{1 to} FF
_n0 has an input SIN is selected in addition to the shift mode of a normal input D, either the input D or input SIN is selected by the select signal SS _5. further,
Other normal output Q to all flip-flops FF ₁ ~FF _n0, there is an output SQ used in shift mode.
The output from the output SQ has the same value as the normal output Q.
Then, all the flip-flops FF _{1 to} FF _n0 are chain-connected in series, such that the output SQ of a certain flip-flop is connected to the input SIN of another flip-flop. The first input SIN is the scan input terminal 901 of the flip-flop FF _1, the output SQ of the last flip-flop FF _n0 is connected to the scan observation terminal 902. Therefore, when the input SIN is valid by the selection of the select signal SS _5, the sequence circuit 92 is not a normal circuit configuration, all the flip-flops FF ₁ ~
The FF _n0 operates in a scan circuit configuration connected in a chain.

The input / output buffer circuit 30 includes a plurality of input / output buffers BB ₁ connected to input / output signal lines of the main circuit 90.
ＢBB _m0 . I / O buffers BB ₁ -BB _m0
Is an interface with the outside of the integrated circuit, and is a buffer element that can set the signal direction to “input” or “output” by setting.

[0008] The scan control circuit 10 is provided with a scan mode signal SS ₁ , which is an external instruction to execute a scan test.
When a scan clock signal SS ₂ is a clock signal for scan test given from the outside, and receives the shift / capture switching signal SS ₃ for switching the shift mode and capture mode from the outside. At the time of the scan test, the scan clock signal SS ₁ is output as it is as the clock signal SS ₄ to the main circuit 90, and the test enable signal SS ₆ for causing the input / output buffer control circuit 20 to perform direction control.
Is output. Further, the shift mode of a scan test, it is output as a select signal SS ₅ the shift / capture switching signal SS ₃ notifies the shift mode in the main circuit 90.

The input / output buffer control circuit 20 receives a test enable signal SS ₆ during a scan test.
The output as the enable signal SS ₇ performs direction control of the output buffer circuit 30 as it is. This direction control
Set to "input" the output buffer BB ₁ ~BB _m0 in the capture mode is performed so as to set to "output" in the shift mode.

[0010] In the scan test in the conventional integrated circuit, the test pattern is set in the flip-flop FF ₁ to ff _n0 in the capture mode, all being chained in a shift mode flip-flop FF ₁ to ff
Signals passing through _n0 are sequentially output from the scan observation terminal 902. Whether or not the integrated circuit is normal or faulty is determined based on whether or not this output is a desired signal.

However, in the method of setting the test pattern and monitoring the output, there is a case where no error occurs in the output depending on the test pattern and the way of failure. It is difficult to select a test pattern to occur. That is, it is difficult to detect all physical failures with this.

By the way, it is known that a static current is very small in a CMOS integrated circuit. However, due to short-circuit of the gate oxide film during the manufacturing process, C
When a bridge failure occurs between an input signal line and an output signal line in a MOS integrated circuit, a source and a drain of a transistor, a power supply voltage, a ground potential, and the like, a power supply current in a quiescent state increases. Using this property, the power supply current is measured, and the abnormality is detected to detect the failure of the CMOS integrated circuit.
The DDQ test has recently received attention.

According to the IDDQ test, a fault that cannot be detected by the method of monitoring the output, that is, a fault that does not cause an error in the output, can be detected. Also,
Since it is not always necessary to make the effect of the failure appear in the output signal, there is an advantage that the test pattern can be easily selected. Therefore, ID along with scan test
By performing the DQ test, the failure detection rate can be improved.

[0014]

In the shift mode in the scan test of the conventional integrated circuit shown in FIG. 7, the enable signal for the input / output buffer circuit 30 is not generally controlled. This is usually the input / output terminal 301 ₁
To 301 ₃ shift mode state of is because no effect on the output signal of the scan observation terminal 902. C
In the case of the MOS integrated circuit, if the input of the input / output buffer circuit 30 is high impedance, a floating state occurs in the input / output buffer circuit 30 and the gate element of the combination circuit 91. Then, a through current flows through the gate elements of the input / output buffer circuit 30 and the combinational circuit 91 in the floating state. As a result, the power supply current value of the integrated circuit becomes larger than the normal flowing current. At this time, the IDDQ test for determining whether the integrated circuit is normal or has failed depending on whether the current value is normal or abnormal cannot be performed. That is, such a conventional CMOS integrated circuit cannot perform the IDDQ test in the shift mode.

Therefore, in such a conventional CMOS integrated circuit, a method of performing an IDDQ test only in a capture mode in which an input / output buffer is fixed to “input” is sometimes used.

In the shift mode, the value set in the capture mode is shifted among all the flip-flops FF _{1 to} FF _n0 connected in a chain. Can take the number of states corresponding to the number of the flip-flops existing in the memory. For example, when the number of flip-flops is 1000, the maximum is 1
There are 000 states. However, in the capture mode for setting a desired value to all flip-flops, depending on the circuit configuration of the integrated circuit, if the flip-flop has a general circuit configuration of up to about 10 stages, it is possible to use all 10 clocks. Can be set to a desired value. Therefore, in the capture mode, there are only about 10 states, and a large measured value of IDDQ cannot be obtained.

Further, in order to enable the IDDQ test in the shift mode, there is a way to avoid floating by fixing the voltage level of the normal input and output terminals 301 ₁ to 301 ₃ to the shift mode. However, since the logic of the circuit consisting of the normal input and output terminals 301 ₁ to 301 ₃ in various gate elements to the first flip-flop during the shift mode is not changed in this way, the combination circuit 91
Cannot be given a sufficient pattern. Therefore, the number of cases where a failure in the combinational circuit 91 cannot be detected increases, and it is difficult to improve the failure detection rate.

An object of the present invention is to provide a C circuit having a scan circuit.
It is an object of the present invention to provide an integrated circuit and a fault detection and determination method which enable an IDDQ test to be executed in a shift mode in a scan test of a MOS integrated circuit.

[0019]

In order to achieve the above object, an integrated circuit according to the present invention has a plurality of flip-flops therein and an input / output buffer capable of selecting a signal direction by setting as an external interface. Scanning for outputting a test enable signal for setting the direction of an input / output buffer to an output side when an external terminal of the input / output buffer becomes high impedance in a test for detecting a failure of the integrated circuit in the integrated circuit It has a control circuit and an input / output buffer control circuit for setting the input / output buffer to the output side in accordance with the test enable signal.

Since the direction of the input / output buffer whose input is high impedance is set to the output side, no floating state occurs in the integrated circuit and no through current flows. Therefore, the power supply current when there is no failure can be suppressed to a small value, and a change in the power supply current when there is a failure can be detected.

Further, since the signal on the output side is repeatedly input to the input side of the input / output buffer, the input value changes. Therefore, the test can be performed while changing the input value.

According to an embodiment of the present invention, the flip-flop has a normal input terminal and a normal output terminal,
It has a test input terminal that can be selected by setting and a test output terminal that outputs the same value as a normal output terminal, all flip-flops are connected in series by the test input terminal and the test output terminal, and scanning is performed. The control circuit sets the flip-flop to select the test input terminal during the test, sets the direction of the input / output buffer to the output side, and applies a clock to the flip-flop to sequentially shift the value.

Since the direction of the input / output buffer is set to the output side in the shift mode, no floating state occurs in the integrated circuit and no through current flows. Therefore, it is possible to detect a change in the power supply current value in the shift mode.

According to another embodiment, a pull-up resistor for raising the voltage level of the input / output signal of the input / output buffer is connected between the external terminal of the input / output buffer and the pull-up resistor. It has a switch that turns off when the direction is set to the output side and turns on when the direction is set to the input side.

According to still another embodiment, a pull-down resistor for lowering the voltage level of the input / output signal of the input / output buffer is connected between an external terminal of the input / output buffer and the pull-down resistor. It has a switch that turns off when the direction of the writing output buffer is set to the output side and turns on when the direction is set to the input side.

The fault detecting method according to the present invention is a fault detecting method for an integrated circuit having a plurality of flip-flops therein and an input / output buffer capable of selecting a signal direction by setting as an external interface, Setting the direction of the input / output buffer to the output side when an external terminal of the input / output buffer becomes high impedance in a test for detecting a failure of the integrated circuit; Causing the integrated circuit to measure a power supply current value of the integrated circuit;
And determining a failure based on the power supply current value.

According to the embodiment of the present invention, in addition to the normal input terminal and the normal output terminal, a test input terminal selectable by setting and a test output terminal for outputting the same value as the normal output terminal are provided. Failure detection of an integrated circuit having a plurality of flip-flops connected in series by the test input terminal and the test output terminal and having an input / output buffer capable of selecting a signal direction by setting as an external interface Setting a desired value to the flip-flop, setting the flip-flop to select a test input terminal during a test, and setting a direction of the input / output buffer to an output side. Operating the flip-flop by applying a clock thereto, and measuring a power supply current value of the integrated circuit And step, comprising the step of performing failure determination based on the source current value.

[0028]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an integrated circuit according to an embodiment of the present invention includes a main circuit 95, a scan control circuit 11, an input / output buffer control circuit 21, and input / output buffer circuits 31A, 31A, 3C.
1B.

The main circuit 95 is a circuit for realizing the main function of the integrated circuit.

As shown in FIG. 2, the main circuit 95 has combination circuits 96A and 96B and a sequential circuit 97. There is no physical boundary between the combinational circuits 96A and 96B and the sequential circuit 97, the combinational circuits 96A and 96B are a set of various gate elements, and the sequential circuit 97 is a flip-flop F ₁
NF _n1 .

The sequential circuit 97 outputs the select signal S ₅
Can be changed to a scan circuit configuration by setting. The scan circuit configuration is a connection configuration used only in the shift mode of the scan test. All flip-flops F ₁ to F _{n 1} in the sequence circuit 97, in addition to the normal input D, there is an input SIN is selected by the shift mode, the input SIN of the selection and input D by the select signal S ₅ Done. Further, all flip-flops F _{1 to} F _n1 have:
In addition to the normal output Q, the output S used in the shift mode
There is Q. Then, all the flip-flops F _{1 to} F _n1 are connected in series, such that the output SQ of a certain flip-flop is connected to the input SIN of another flip-flop. The first input SIN is the scan input terminal 951 of the flip-flop F _1, the output SQ of the last flip-flop F _n1 is connected to the scan observation terminal 952. Therefore, when the input SIN is valid by the selection of the select signal S _5, the sequence circuit 97 is not a normal circuit configuration, all the flip-flops F ₁ to F
_n1 operates in a chain-connected scan circuit configuration.

The input / output buffer circuits 31A and 31B have a plurality of input / output buffers (not shown) connected to input / output signal lines of the main circuit 95.

The scan control circuit 11 includes a scan mode signal S ₁ externally instructing execution of a scan test, a scan clock signal S ₂ externally provided as a scan test clock signal, an external shift mode and a capture mode. shift / capture switching signal S ₃ for performing mode switching of the mode is set to input. At the time of the scan test, the scan clock signal S ₁
Is directly output as a clock signal S ₄ to the main circuit 95, and a test enable signal S ₆ for causing the input / output buffer control circuit 21 to perform direction control is output. Further, the shift mode of a scan test, it is output as a select signal S ₅ to the shift / capture switching signal S ₃ notifies the shift mode in the main circuit 95.

The input / output buffer control circuit 21 inputs a test enable signal S
₆ outputs to as the enable signal S ₇ as it performs direction control of the output buffer circuit 31.

The input / output buffer circuit 31 is set to “input” in the capture mode and “output” in the shift mode by the enable signal S ₇ from the input / output buffer control circuit 21.

With reference to FIG. 3, the operation of the integrated circuit of this embodiment in a scan test accompanied by an IDDQ test will be described.

First, when a scan test is instructed from the outside by the scan mode signal S _{1 and the} capture mode is set by the shift / capture switching signal S ₃ , the input / output buffer control circuit 21 sets the enable signal S 1
By ₇ sets output buffer circuit 31A, the input and output buffers B ₁ .about.B _m1 of 31B to "Input".

Then, from the outside, the normal input / output terminal 311 ₁
While giving a test value to ~ 311 _m1 , the clock signal S
Given a predetermined number of clock to the flip-flop F ₁ to F _n1 sequential circuits 97 _4, all the flip-flops F ₁ ~
A desired value is set to F _n1 . The number of clocks is a value determined by the maximum number of flip-flop stages in a normal circuit configuration in which the sequential circuit 97 does not have a scan circuit configuration, and is generally about 10 stages. After the operation in the capture mode, the operation shifts to the operation in the shift mode.

As shown in FIG. 4, when the shift mode is set in the integrated circuit of this embodiment, the sequential circuit 97 has a scan circuit configuration in which flip-flops F _{1 to} F _n1 are connected in a chain. Furthermore, the input-output buffer B ₁ .about.B _m1 is set by the enable signal S ₇ to "output". In addition,
Output buffer circuit 31A, the 31B is set to "output", the input of the input buffer IB ₁ ~IB _m1 in the interior output buffer B ₁ .about.B _m1, the output buffer OB ₁ ~OB _m1 of the corresponding Is input. Therefore, no through current flows.

[0041] Here, the sequential circuit 97, given a clock signal S ₄ to the number of internal flip-flops (in FIG. 4 n1 pieces), the value is set to the flip-flops F ₁ to F _n1 is chain The signals are shifted between the connected flip-flops and sequentially output from the scan observation terminal 952.
At this time, the sequential circuit 97, a state each time the clock signal S ₄ is given (the value set in the flip-flop) is changed. Each time this change passes through the transient state and becomes a steady state, the value sequentially output from the scan observation terminal 952 is measured, and the power supply current value of the entire integrated circuit is measured by an external measuring device (not shown).

All the power supply current values measured after the scan test is completed are compared with the reference value, and if there is an abnormally higher value than the reference value, it indicates that the integrated circuit has a failure. When there is no abnormality in the value output from the scan observation terminal 952 and there is an abnormality in the power supply current value, it is considered that the failure is such that the output value is not affected by the test pattern of the scan test at that time.

In the integrated circuit of this embodiment, since the input / output buffer circuit 31 is set to "output" in the shift mode, a floating state does not occur in the input / output buffer circuit 31 and the combination circuit 96, and a through current flows. Absent. Therefore, the failure of the integrated circuit can be easily determined based on whether or not there is a large value among the power supply current values measured in the shift mode, and the failure detection rate is improved.

[0044] Further, in the input buffer IB ₁ ~IB _m1 in the interior of the output buffer B ₁ .about.B _m1, the output of the corresponding output buffer OB ₁ ~OB _m1 is input, the input values every clock Changes. Thereby, the combination circuit 9
Since the input given to 6 changes sequentially, various values can be given to the combinational circuit 96 to perform the IDDQ test. Therefore, the failure detection rate of the combinational circuit 96 is improved.

FIGS. 1 and 2 show another embodiment of the present invention.
5 is different from the integrated circuit shown in FIG. 6 only in the configuration of the input / output buffer circuit, and has an input / output buffer circuit 32 having a pull-up resistor shown in FIG.

The input / output buffer circuit 32 shown in FIG.
Between the resistor 323 and the normal input terminal 321
Enable signal S from the buffer control circuit 21₇By
A controlled switch 322 is connected. switch
322 is an enable signal S ₇Is selected by
Turns off when touched, and turns off when
It becomes.

[0047] Thus, output buffer circuit 32 by the enable signal S ₇ is set to "output", and,
When the output signal is low, the switch 322 prevents a through current from flowing through the input / output buffer circuit 32 and the pull-up resistor 323. Thus, in an integrated circuit having an input / output buffer to which a pull-up resistor is connected, it is possible to detect a failure by a power supply current value in a shift mode.

Another embodiment of the present invention also differs only in the configuration of the input / output buffer circuit. Instead of the input / output buffer circuit 31 of the integrated circuit of FIGS. 1 and 2, the pull-down circuit shown in FIG. An input / output buffer circuit 33 having a resistance is provided.

The input / output buffer circuit 33 shown in FIG.
Between the input resistor 333 and the normal input terminal 331.
Enable signal S from the buffer control circuit 21₇By
The switch 332 to be controlled is connected. switch
332 is an enable signal S ₇Is selected by
Turns off when "Input" is selected.

The switch 332 prevents a through current from flowing through the input / output buffer and the pull-down resistor 333 when the input / output buffer is set to “output” by the enable signal S ₇ and the output signal is high. . Thus, in a configuration having an input / output connected to a pull-down resistor, a failure can be detected based on the value of the power supply current in the shift mode.

[0051]

As described above, in the integrated circuit of the present invention, a floating state does not occur in the shift mode of the scan test, and no through current flows. Therefore, a change in the power supply current value of the entire integrated circuit causes a physical change in the integrated circuit. It is possible to detect a temporary failure, and the failure detection rate is improved.

For example, an integrated circuit having 1000 flip-flops and the maximum number of flip-flops is 10 is taken as an example. The integrated circuit can take 10 states in the capture mode and 1000 states in the shift mode in a series of tests from the capture mode to the shift mode. Therefore, when the IDDQ test is performed in both the capture mode and the shift mode, the IDDQ test is performed about 1/100 of the case where the IDDQ test is performed only in the capture mode.
With the number of test patterns, the same failure detection rate can be obtained.

According to one example, the failure detection rate was 60% when the IDDQ test was performed only in the capture mode.
It has been found that the DDQ test improves the fault detection rate to 90%.

Further, since the output side signal is input to the input side of the input / output buffer, the input value changes every clock, and the integrated circuit can be tested with many input patterns. Therefore, the failure detection rate is higher than when the input value is fixed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram showing a configuration of a main circuit 95.

FIG. 3 is an explanatory diagram for explaining an operation in a capture mode of the integrated circuit according to the embodiment;

FIG. 4 is an explanatory diagram for explaining an operation in a shift mode of the integrated circuit according to the embodiment;

FIG. 5 is a schematic circuit diagram showing a configuration of an input / output buffer circuit according to another embodiment of the present invention.

FIG. 6 is a schematic circuit diagram showing a configuration of an input / output buffer circuit according to another embodiment of the present invention.

FIG. 7 is a schematic circuit diagram showing a configuration of a conventional integrated circuit.

[Explanation of symbols]

Reference Signs List 11 scan control circuit 111 scan mode signal input terminal 112 scan clock signal input terminal 113 shift / capture switching signal input terminal 21 input / output buffer control circuits 31A, 31B input / output buffer circuit 311 _{1 to} 311 _m1 normal input / output terminal 95 main circuit 951 Scan input terminal 952 scan observation terminal 96A, 96B combination circuit 97 sequential circuit 32 input / output buffer circuit 321 normal input / output terminal 322 switch 323 pull-up resistor 33 input / output buffer circuit 331 normal input / output terminal 332 switch 333 pull-down resistor 10 scan control circuit DESCRIPTION OF SYMBOLS 101 Scan mode signal input terminal 102 Scan clock signal input terminal 103 Shift / capture switching signal input terminal 20 I / O buffer control circuit 30 I / O buffer circuit 01 ₁ to 301 _m0 normal input and output terminals 90 main circuit 91 combining circuit 92 sequential circuit 901 test input terminal 902 test output terminal _{B 1 ~B m1, BB 1 ~BB} m0 output buffer IB ₁ ~IB _m1 input buffer OB ₁ ~ OB _m1 output buffer _{F 1 ~F n1, FF 1 ~FF} n0 flip-flop

Claims (6)

[Claims] 1. A semiconductor device comprising: a plurality of flip-flops therein;
In an integrated circuit having an input / output buffer capable of selecting a signal direction as an external interface by setting, when an external terminal of the input / output buffer becomes high impedance in a test for detecting a failure of the integrated circuit,
A scan control circuit that outputs a test enable signal for setting the direction of the input / output buffer to the output side; and an input / output buffer control circuit that sets the input / output buffer to the output side according to the test enable signal. An integrated circuit characterized by the above. 2. The flip-flop has, in addition to a normal input terminal and a normal output terminal, a test input terminal selectable by setting and a test output terminal for outputting the same value as the normal output terminal. All the flip-flops are connected in series by the test input terminal and the test output terminal, and the scan control circuit sets the flip-flop to select a test input terminal during the test, and Set the direction of the output buffer to the output side,
2. The integrated circuit according to claim 1, wherein a value is sequentially shifted by applying a clock to said flip-flop. 3. A pull-up resistor for raising a voltage level of an input / output signal of the input / output buffer, and a pull-up resistor connected between an external terminal of the input / output buffer and the pull-up resistor. 3. The integrated circuit according to claim 1, further comprising a switch that is turned off when set to an output side and turned on when set to an input side. 4. A pull-down resistor for lowering a voltage level of an input / output signal of the input / output buffer, connected between an external terminal of the input / output buffer and the pull-down resistor, wherein a direction of the input / output buffer is an output side. 3. The integrated circuit according to claim 1, further comprising a switch that is turned off when set to the input side and turned on when set to the input side. 5. A semiconductor device having a plurality of flip-flops therein.
A failure detection method for an integrated circuit having an input / output buffer capable of selecting a signal direction by setting as an external interface, wherein an external terminal of the input / output buffer becomes high impedance in a test for detecting a failure of the integrated circuit. sometimes,
Setting the direction of the input / output buffer to the output side; applying a clock to the flip-flop to operate; measuring a power supply current value of the integrated circuit; determining a failure based on the power supply current value A failure detection method comprising the steps of: 6. In addition to a normal input terminal and a normal output terminal, a test input terminal selectable by setting and a test output terminal for outputting the same value as the normal output terminal, the test input terminal And a plurality of flip-flops connected in series by the test output terminal, and an input / output buffer capable of selecting a signal direction by setting as an external interface. Setting a desired value to the flip-flop; setting the flip-flop to select a test input terminal during a test; setting the direction of the input / output buffer to the output side; and setting the clock to the flip-flop. Providing the integrated circuit; operating the integrated circuit; measuring a power supply current value of the integrated circuit; A failure detection method including a step of performing a failure determination based on a flow value.