JP2007173606A - Electronic device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the erroneous mounting of a semiconductor memory device to a socket and reduce the number of times of mounting to the socket. <P>SOLUTION: The electronic device is provided with a plurality of semiconductor devices in which semiconductor chips are sealed by a resin sealing body, and a plurality of first terminals for external connection electrically connected to the semiconductor chips are projected out of the resin sealing body; a wiring substrate having a main surface and a rear surface which are positioned on the opposite side of each other and the plurality of semiconductor devices are mounted on the main surface; and a cover member provided on the main surface of the wiring substrate so as to cover the plurality of semiconductor devices. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic device and a manufacturing technique thereof, and more particularly to a technology effective when applied to an electronic device (module) in which a plurality of semiconductor devices are mounted on a wiring board.

Information processing systems using computers as key devices are rapidly spreading from information communication networks represented by the Internet and LAN to consumer electronics and passenger cars. Even in such an information processing system, the capacity of a storage circuit for temporarily or semi-permanently storing electronic information has been increased along with higher performance and more functions, and a small and large capacity storage circuit is required. Has been.
Therefore, various semiconductor products have been proposed and commercialized in order to increase the capacity of the memory circuit in the information processing system.

For example, Japanese Patent Laying-Open No. 2005-150647 discloses a semiconductor memory device in which two semiconductor chips each having a memory circuit are stacked in two stages, and the two semiconductor chips are resin-sealed with one resin sealing body. It is disclosed.
Japanese Patent Application Laid-Open No. 2005-298003 discloses a semiconductor module (electronic device) in which a semiconductor memory device on which a memory circuit is mounted is mounted on a wiring board in two stages.

JP 2005-150647 A JP 2005-298003 A

  By the way, computerization is also progressing in a pachinko machine that is one of the gaming machines, and images, sounds, and the like are controlled by an information processing system. In an information processing system using a pachinko machine, a large-capacity storage circuit is required as the performance and multifunction of images and sounds are increased, and a large number of semiconductor storage devices are incorporated. As the semiconductor memory device, for example, an EEPROM (Electrically Erasable Programmable Lead Only Memory), which is also referred to as a flash memory, and in which electronic information can be electrically rewritten, is used. As the semiconductor memory device, for example, a TSOP (Thin Small Outline Package) type semiconductor memory device suitable for miniaturization and thinning is used.

  In the pachinko machine, for example, eight 512 Mbit semiconductor memory devices are used to store electronic information such as images and sounds. These eight semiconductor memory devices are mounted in a detachable state on a mounting board via a socket in order to facilitate rewriting of electronic information accompanying a change in function of the pachinko machine.

  However, in the mounting of the semiconductor memory device by the socket, since eight corresponding sockets are arranged for each of the eight semiconductor memory devices, the semiconductor memory device must be originally mounted in the corresponding socket. Incorrect mounting is likely to occur when another semiconductor memory device is mounted by mistake.

In addition, since eight semiconductor memory devices are mounted one by one in the corresponding eight sockets, the number of mounting steps required is the same as the number of semiconductor memory devices. If the capacity increases further in the future, the number of memories to be installed will increase, which will be more troublesome.
Moreover, on the mounting board of the pachinko machine, eight socket areas are required, and it is difficult to downsize the mounting board.

  In the pachinko machine, in order to prevent fraud, the Secure Electronic Communication Technology Association (Hotsukyo Co., Ltd.) is obliged to attach identification labels to all semiconductor memory devices so that the contents of the semiconductor memory devices can be identified. Yes. For this reason, it is necessary to affix the identification label for each semiconductor memory device one by one, which is cumbersome and time-consuming.

The TSOP type semiconductor memory device has a package structure in which a lead electrically connected to an electrode pad of a semiconductor chip protrudes from a side surface of a resin sealing body and is bent into a predetermined shape. The lead is easily deformed, and poor contact with the socket is likely to occur.
Accordingly, the present inventor made the present invention paying attention to modularizing a plurality of semiconductor memory devices.

A first object of the present invention is to provide a technique capable of reducing erroneous mounting of a semiconductor memory device on a socket and reducing the number of mountings on the socket.
A second object of the present invention is to provide a technique capable of downsizing a mounting board.
A third object of the present invention is to provide a technique capable of reducing labor caused by attaching an identification label.
A fourth object of the present invention is to provide a module that achieves the first object and has high connection reliability with a socket.
A fifth object of the present invention is to provide a module having high reliability against fraud.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
The first object is achieved by mounting a plurality of semiconductor memory devices on the main surface of the wiring board to form a module.
The second object is to arrange a plurality of first semiconductor devices in a plane on the main surface of the wiring board, and a plurality of the first semiconductor devices corresponding to the plurality of first semiconductor devices on the plurality of first semiconductor devices. This is achieved by arranging the second semiconductor device.
The third object is achieved by covering the plurality of semiconductor memory devices with a cover member.
The fourth object is achieved by providing an LGA (Land Grid Array) type package structure in which a plurality of electrode pads are arranged as external connection terminals on the back surface opposite to the main surface of the wiring board.
The fifth object is achieved by using a resin sealing body that seals the plurality of semiconductor memory devices as the cover member.

  The semiconductor memory device has a package structure in which a semiconductor chip on which a memory circuit is mounted is resin-sealed by a resin sealing body, and a plurality of leads electrically connected to the semiconductor chip protrude from the resin sealing body. ing.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, it is possible to reduce the erroneous mounting of the semiconductor memory device to the socket, and to reduce the number of mountings to the socket.
According to the present invention, the mounting board can be reduced in size.
According to the present invention, it is possible to reduce labor caused by attaching an identification label.
ADVANTAGE OF THE INVENTION According to this invention, a module with high connection reliability with a socket can be provided.
ADVANTAGE OF THE INVENTION According to this invention, the module with high reliability with respect to fraud can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

1 to 23 are diagrams related to a memory module (electronic device) according to an embodiment of the present invention.
FIG. 1 is a diagram showing an external structure of a memory module ((a) is a schematic plan view, (b) is a schematic side view),
2A and 2B are diagrams showing an internal structure of the memory module of FIG. 1 (a) a schematic plan view in which a resin sealing body is omitted, and FIG. 2b is a schematic diagram along the line a′-a ′ in FIG. Sectional view),
FIG. 3 is a schematic bottom view of the memory module of FIG.
FIG. 4 is a schematic cross-sectional view enlarging FIG.
FIG. 5 is a schematic cross-sectional view enlarging a part of FIG.
FIG. 6 is a development view showing a simplified view of FIG.
7 is a diagram showing an external structure of the semiconductor memory device of FIG. 6 ((a) is a schematic plan view of the lower semiconductor memory device, (b) is a schematic plan view of the upper semiconductor memory device),
FIG. 8 is a development view showing a simplified first cross section different from FIG.
FIG. 9 is a development view showing a second cross section different from FIG. 6 in a simplified manner,
10 is a schematic plan view showing an arrangement pattern of electrode pads arranged on the main surface of the wiring board of FIG.
11 to 14 are schematic plan views showing the first to fourth wiring patterns in the wiring board of FIG.
FIG. 15 is a schematic plan view showing a schematic configuration of a multi-wiring board used for manufacturing a memory module;
FIG. 16 is a flowchart showing a manufacturing process of a memory module;
FIG. 17 is a schematic plan view showing a state in which a semiconductor memory device is mounted on a multi-wiring board in manufacturing a memory module;
FIG. 18 is a schematic perspective plan view showing a state in which a multi-wiring board is clamped in a molding die in manufacturing a memory module;
19 is a schematic cross-sectional view taken along line b′-b ′ in FIG.
FIG. 20 is a schematic perspective plan view showing details of the sealing cavity of FIG.
FIG. 21 is a schematic perspective plan view showing a state where a resin sealing body is formed by injecting resin into a sealing cavity of a molding die in the manufacture of a memory module;
22 is a schematic cross-sectional view taken along the line c′-c ′ in FIG.
FIG. 23 is a schematic plan view showing a state in which a multi-wiring board and a resin sealing body are fragmented in the manufacture of a memory module;
FIG. 24 is a schematic cross-sectional view showing a state where the memory module is mounted in the socket;
FIG. 25 is a schematic diagram for explaining the contact operation of the contact pins of the socket.

FIG. 26 is a schematic bottom view of a memory module which is a modification of the embodiment of the present invention.
FIG. 27 is a schematic bottom view of a memory module which is a modification of the embodiment of the present invention.

  2 ((a), (b)) and FIG. 3, the memory module (electronic device) 1 of this embodiment includes a plurality of semiconductor memory devices (semiconductor devices) 10 on the main surface 2x of the wiring board 2. Is mounted, and a plurality of electrode pads 26 (for example, 120) and four electrode pads 26s are arranged as external connection terminals on the back surface 2y opposite to the main surface 2x of the wiring board 2, resulting in an LGA type package structure. Yes. Furthermore, the memory module 1 of the present embodiment has a package structure having a resin sealing body 3 that covers and covers the plurality of semiconductor memory devices 10 as a cover member that covers the plurality of semiconductor memory devices 10.

  The plurality of semiconductor memory devices 10 are mounted on the main surface 2x of the wiring board 2 in a two-tiered manner as shown in FIGS. 2 (a) and (b) and FIG. A plurality of semiconductor memory devices 10a arranged in a plane 2x and a plurality of semiconductor memory devices 10b arranged on each semiconductor memory device 10a corresponding to the plurality of semiconductor memory devices 10a are included. In the present embodiment, for example, four semiconductor memory devices 10a are mounted on the lower stage, four semiconductor memory devices 10b are mounted on the upper stage, and a total of eight semiconductor memory devices 10 are mounted.

  As shown in FIGS. 5 and 6, the lower semiconductor memory device 10a and the upper semiconductor memory device 10b have different lead 16 heights (lengths), but basically have the same package structure. Yes. The semiconductor memory devices 10a and 10b of the present embodiment have, for example, a TSOP type package structure suitable for thinning and miniaturization.

  As shown in FIGS. 6 and 7, the semiconductor memory devices 10 a and 10 b include a first semiconductor chip (12, 13) 11, a die pad 15, and a plurality of leads (first external connection terminals) 16. It has a package structure in which a lead group, a second lead group including a plurality of leads (first external connection terminals) 16, a plurality of bonding wires 17, and the like are resin-sealed by a resin sealing body 18. The planar shape of the resin sealing body 18 in all the semiconductor memory devices of this embodiment extends, for example, in a direction intersecting with two opposing short sides and the direction in which the short sides extend, and is longer than the short sides. It consists of a so-called rectangle consisting of two opposing long sides.

  The semiconductor chips 12 and 13 have a rectangular planar shape that intersects the thickness direction, and are, for example, rectangular in this embodiment. Although not limited to this, the semiconductor chips 12 and 13 mainly include a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, a thin film stack provided on the main surface of the semiconductor substrate, It has a structure having a surface protective film provided so as to cover the thin film laminate. The thin film laminate has a multilayer structure in which a plurality of insulating layers and wiring layers are stacked. The semiconductor substrate is made of, for example, single crystal silicon. The insulating layer of the thin film stack is formed of an insulating film such as a silicon oxide film. The wiring layer of the thin film laminate is formed of a metal film such as aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

  The semiconductor chips 12 and 13 have a main surface (circuit forming surface, element forming surface) and a back surface that are located on opposite sides, and each main surface of the semiconductor chips 12 and 13 has, for example, a flash memory as a memory circuit. A 256 megabit (Mbit) EEPROM (Electrically Erasable Programmable Lead Only Memory) is formed (mounted). This memory circuit is mainly constructed by transistor elements formed on the main surface of the semiconductor substrate and wiring formed in the wiring layer of the thin film stack. That is, the memory module 1 of this embodiment has a large capacity (256 Mbit × 2 × 8) of 4 gigabits (Gbit).

  A plurality of electrode pads (bonding pads) 14 are formed on the main surfaces of the semiconductor chips 12 and 13. For example, the plurality of electrode pads 14 are arranged along two long sides on two long sides located on opposite sides of the semiconductor chip 11 (12, 13). The plurality of electrode pads 14 are formed in the uppermost wiring layer of the thin film stack, and are exposed from bonding openings formed in the surface protective film corresponding to the plurality of electrode pads 14.

  Although the circuit patterns of the semiconductor chips 12 and 13 are mirror-inverted, the outer dimensions and the storage capacity are basically the same. The back surface of the semiconductor chip 12 is bonded and fixed to the main surface of the die pad 15 with an adhesive interposed. The back surface of the semiconductor chip 13 is bonded and fixed to the back surface opposite to the main surface of the die pad 15 with an adhesive interposed.

  As shown in FIGS. 7 (a) and 7 (b), the resin sealing body 18 has a rectangular planar shape that intersects the thickness direction, and is rectangular in this embodiment. For the purpose of reducing the stress, the resin sealing body 18 is formed of, for example, an epoxy-based thermosetting insulating resin to which a phenolic curing agent, silicone rubber, and a large number of fillers (for example, silica) are added. . As a method for forming the resin sealing body 18, for example, a transfer molding method suitable for mass production is used.

  Among the two long sides located on the opposite sides of the resin sealing body 18, a plurality of leads 16 of the first lead group are arranged along one long side on the long side, and the other A plurality of leads 16 of the second lead group are arranged along the other long side on the long side.

  As shown in FIG. 6, each lead 16 of the first and second lead groups is formed integrally with the inner portion located inside the resin sealing body 18 and the resin sealing body. 18 is configured to have an outer portion protruding (exposed) from the side surface of 18, and extends over the inside and outside of the resin sealing body 18. The outer portion of the lead 16 is bent into a predetermined lead shape (for example, a gull wing shape), and the upper semiconductor memory device 10b is higher (longer) than the lower semiconductor memory device 10a.

  In the first lead group, the inner portions of each of the plurality of leads 16 are electrically connected to each other by a plurality of electrode pads 14 and a plurality of bonding wires 17 arranged along one long side of the semiconductor chip 12. Further, the plurality of electrode pads 14 arranged along one long side of the semiconductor chip 13 and the plurality of bonding wires 17 are electrically connected to each other.

  In the second lead group, each inner portion of the plurality of leads 16 is electrically connected by a plurality of electrode pads 14 and a plurality of bonding wires 17 arranged along the other long side of the semiconductor chip 12. Further, the plurality of electrode pads 14 arranged along the other long side of the semiconductor chip 13 and the plurality of bonding wires 17 are electrically connected to each other.

  As shown in FIG. 8, only the electrode pad 14 of the semiconductor chip 12 is electrically connected to the plurality of leads 16 via the bonding wires 17 (in the lower semiconductor memory device 10a, reference numeral a1 is the upper one). As shown in FIG. 9, only the electrode pad 14 of the semiconductor chip 13 is electrically connected via the bonding wire 17 (reference symbol a2 in the lower semiconductor memory device 10a, upper symbol in the upper stage). In the semiconductor memory device 10b, reference numeral b2) is included. These two leads (a1 and a2, b1 and b2) are chip selection leads to which a select signal for selecting one semiconductor chip from the two semiconductor chips (12, 13) is applied.

  The two chip selection leads (b1, b2) of the upper semiconductor memory device 10b are arranged at positions where they overlap with the two chip selection leads (a1, a2) of the lower semiconductor memory device 10a, respectively. ing.

  As shown in FIG. 2A, the wiring substrate 2 has a square shape that intersects the thickness direction thereof, and is a square of, for example, 26 mm × 26 mm in this embodiment.

  As shown in FIG. 10, four product mounting areas (device mounting areas) 33 for mounting the semiconductor memory device 10 are provided on the main surface 2x of the wiring board 2. Are provided with a first and a second pad group composed of a plurality of electrode pads 25 arranged in a line along one direction. The first and second pad groups are spaced apart from each other in a direction orthogonal to the arrangement direction of the electrode pads 25 in a plane.

  Of the first and second pad groups, the first pad group includes four chip selection electrode pads (25a1, 25b1, 25a2, 25b2). The chip selection electrode pads 25a1 and 25b1 are spaced apart from each other in series along a direction orthogonal to the arrangement direction of the electrode pads 25 in a plane, and are electrically separated. The chip selection electrode pads 25a2 and 25b2 are spaced apart from each other in series along a direction perpendicular to the arrangement direction of the electrode pads 25 in a plane, and are electrically separated. The chip selection electrode pads 25a1 and 25a2 are disposed inside the chip selection electrode pads 25b1 and 25b2.

  As shown in FIG. 8, the chip selection electrode pad 25a1 has a chip selection lead a1 of the lower semiconductor storage device 10a, and the chip selection electrode pad 25b1 has a chip selection lead b1 of the upper semiconductor storage device 10b. However, they are electrically and mechanically connected via a solder material, for example.

  As shown in FIG. 9, the chip selection electrode pad 25a2 has a chip selection lead a2 of the lower semiconductor storage device 10a, and the chip selection electrode pad 25b2 has a chip selection lead b2 of the upper semiconductor storage device 10b. However, they are electrically and mechanically connected via a solder material, for example.

  As shown in FIG. 6, the plurality of electrode pads 25 of the first and second pad groups include a plurality of leads 25 of the first and second lead groups of the lower and upper semiconductor memory devices (10a, 10b). (Excluding chip selection leads) are electrically and mechanically connected, for example, via a solder material.

  As shown in FIG. 2A, on the main surface 2x of the wiring board 2, for example, a plurality of capacitors 5 are mounted as surface mount type passive components. The plurality of capacitors 5 are arranged at the central portion where two diagonal lines intersect on the main surface 2x of the wiring board 2, and are soldered to the plurality of passive component electrode pads provided on the main surface 2x of the wiring board 2, for example. Each is electrically and mechanically connected via a material.

  As shown in FIG. 10, the four product mounting areas 33 are formed between the central portion of the main surface 2 x of the wiring board 2 and the outer peripheral side of the wiring board 2, in other words, on the main surface 2 x of the wiring board 2. It is arranged so as to surround the central part.

  Of the four product mounting regions 33, the first and second pad groups of the first product mounting region 33a extend along the extending direction of the first side 2a of the wiring board 2, and the second product mounting region 33a The first and second pad groups in the product mounting area 33b extend along the extending direction of the second side 2b of the wiring board 2, and the first and second pads in the third product mounting area 33c. The group extends along the extending direction of the third side 2c of the wiring board 2, and the first and second pad groups of the fourth product mounting region 33d are the fourth side 2d of the wiring board 2. It extends along the extending direction. That is, the four product mounting areas 33 are the wiring board 2 in the state where the directions of the first and second pad groups are 90 degrees different from each other in the two product mounting areas 33 adjacent along the outer periphery of the wiring board 2. It is arranged so as to surround the central portion of the main surface 2x.

  As shown in FIG. 3, the plurality of electrode pads 26 arranged on the back surface 2 y of the wiring board 2 have a rectangular shape that intersects the thickness direction. The plurality of electrode pads 26 are arranged along each side of the wiring board 2 such that each long side is along a direction away from the outer peripheral side of the wiring board 2. The four electrode pads 26 arranged on the back surface of the wiring board 2 are arranged at the four corners 2s of the wiring board 2, and the length of each side along the two sides of the corner 2s is the width of the electrode pad 26. The planar shape is wider than (short side).

  Although the wiring board 2 is not limited to this, for example, as shown in FIG. 5, mainly a base material (core material) 20 and a protective film 27 a provided so as to cover the main surface of the base material 20. The protective film 27 b is provided so as to cover the back surface opposite to the main surface of the base material 20. The base material 20 is, for example, a multilayer wiring in which a plurality of high-elasticity resin substrates impregnated with glass fiber epoxy resin or polyimide resin are stacked in multiple stages, and have a main surface and a back surface (front and back surfaces), and a wiring layer inside. In this embodiment, for example, a four-layer wiring structure is used. The protective films 27 a and 27 b are provided mainly for the purpose of protecting the wiring formed on the wiring layers on the front and back surfaces of the base material 20. As the protective films 27a and 27b, for example, an insulating resin film (solder resist film) is used.

  The plurality of electrode pads 25 and the plurality of chip selection electrode pads (25a1, 25b1, 25a2, 25b2) are formed in the first wiring layer counting from the main surface 2x of the wiring board 2, and Correspondingly, it is exposed from the opening formed in the protective film 27a.

  The plurality of electrode pads 26 and the four electrode pads 26s are formed in the fourth wiring layer as counted from the main surface 2x of the wiring board 2, and are formed in the protective film 27b corresponding to each electrode pad. It is exposed from the opening.

  In the wiring substrate 2, the wiring pattern 21 shown in FIG. 11 is formed in the first wiring layer, and the wiring pattern 22 shown in FIG. 12 is formed in the second wiring layer. A wiring pattern 23 shown in FIG. 13 is formed in this wiring layer, and a wiring pattern 24 shown in FIG. 14 is formed in the fourth wiring layer. Each wiring layer is formed of a metal film (conductive film) such as Cu or Cu alloy.

  Eight semiconductor memory devices 10, a plurality of capacitors 5 and the like are made of resin by a resin sealing body 3 formed on the main surface 2x of the wiring board 2, as shown in FIG. 2 ((a), (b)). It is sealed. For the purpose of reducing the stress, the resin sealing body 3 is formed of, for example, an epoxy thermosetting insulating resin to which a phenolic curing agent, silicone rubber, a large number of fillers (for example, silica) and the like are added. .

  As shown in FIG. 1 ((a), (b)), the resin sealing body 3 has a rectangular planar shape that intersects the thickness direction. In this embodiment, for example, the same as the wiring board 2 is used. It has a planar size (26 mm × 26 mm). As a method for forming the resin sealing body 3, for example, a transfer molding method suitable for mass production is used.

  Here, in the manufacture of the memory module 1, each product is formed by using a multi-wiring board (multiple wiring board) having a plurality of product forming areas (device forming areas, product acquiring areas) partitioned by scribe lines. Semiconductors mounted in each product formation area using an individual transfer molding method that encapsulates the semiconductor memory device mounted in each area for each product formation area or a multi-wiring board that has multiple product formation areas A batch type transfer molding method in which the memory device is collectively sealed with a single resin sealing body can be employed. In this embodiment, a batch type transfer molding method effective for miniaturization is employed.

  In the case of the collective transfer molding method, after forming the resin sealing body, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces by, for example, dicing. Therefore, the planar size of the resin sealing body 3 and the wiring board 2 of the present embodiment is almost the same.

  As shown in FIG. 4, the resin sealing body 3 has a mounting height of two semiconductor memory devices 10 mounted in two layers (the resin sealing body of the upper semiconductor memory device 10 b from the main surface of the wiring board 2. A first portion 3a having a thickness (height from the main surface 2x of the wiring board 2 to the upper surface) t1 thicker than the height h1), and the first portion 3a. The second portion 3b is thicker than the thickness 3a (thickness from the main surface 2x to the upper surface of the wiring board 2) t2. The second portion 3 b has a smaller planar area than the first portion 3 a and is formed along one side of the wiring board 2. That is, the resin sealing body 3 according to the present embodiment has an external structure in which a step extending along one side of the wiring board 2 is provided on the upper surface thereof. In the present embodiment, the thickness of the first portion 3a is, for example, about 2.5 mm, and the thickness of the second portion 3b is, for example, about 4.0 mm. Further, the flat area of the first portion 3a is, for example, about 26 mm × 21 mm, and the flat area of the second portion 3b is, for example, about 26 mm × 4 mm.

  As shown in FIG. 1 ((a), (b)), an identification label 4 is attached to the upper surface 3x of the first portion 3a of the resin sealing body 3. The identification label 4 describes the model name and the memory contents (stored data). The product name is marked with a laser on the upper surface 3x of the resin sealing body 3.

  As shown in FIG. 2A, the upper four semiconductor memory devices 10 b and the lower four semiconductor memory devices 10 a include a central portion (a plurality of capacitors 5) of the main surface 2 x of the wiring board 2 and the wiring board 2. In other words, it is arranged so as to surround the central portion (a plurality of capacitors 5) of the main surface 2 x of the wiring board 2.

  Of the upper four semiconductor memory devices 10b and the lower four semiconductor memory devices 10a, the upper and lower semiconductor memory devices (10a, 10b) mounted in the product mounting area 33a shown in FIG. The upper and lower semiconductor memory devices (10a, 10a, 10a, 10b) are arranged so that the long side of the stopper 18 extends along the extending direction of the first side 2a of the wiring board 2 and is mounted in the product mounting region 33b shown in FIG. 10b) is arranged such that the long side of each resin sealing body 18 is along the extending direction of the second side 2b of the wiring board 2, and the upper stage mounted on the product mounting region 33c shown in FIG. The lower semiconductor memory devices (10a, 10b) are arranged so that the long sides of the respective resin sealing bodies 18 are along the extending direction of the third side 2c of the wiring board 2, and the product mounting shown in FIG. The upper stage mounted in the area 33d and The semiconductor memory device of the stage (10a, 10b) are arranged long side of each of the resin sealing body 18 is set along the extending direction of the fourth side 2d of the wiring substrate 2. That is, each of the four semiconductor memory devices (10a, 10b) in the lower stage and the upper stage is divided into two semiconductor memory devices (10a, 10b) adjacent to each other along the outer periphery of the wiring board 2. It is arranged so as to surround the central portion of the main surface 2x of the wiring board 2 in a state where the directions are different by 90 degrees, in other words, in a state where the tips of the respective leads 16 do not face each other. In other words, the short side of the resin sealing body 18 surrounds the central portion of the main surface 2x of the wiring board 2 in a state of facing the long side of the resin sealing body 18 adjacent along the outer periphery of the wiring board 2. Is arranged.

Next, a multi-wiring substrate used for manufacturing the memory module 1 will be described with reference to FIG.
As shown in FIG. 15, the multi-wiring board 30 has a rectangular planar shape that intersects with the thickness direction thereof, and is, for example, a rectangle in this embodiment. A mold region (resin sealing region) 31 is provided on the main surface of the multi-wiring substrate 30, and a plurality of product formation regions 32 arranged in a plane are provided in the mold region 31. In the product formation area 32, four product mounting areas 33 are provided. In the manufacture of the memory module 1, the semiconductor storage devices 10 a and 10 b are mounted in two product layers in each product mounting region 33 of each product forming region 32, and each product in each product forming region 32 is mounted in the mold region 31. A resin sealing body (collective resin sealing body) for collectively sealing a plurality of semiconductor memory devices (10a, 10b) mounted in two layers corresponding to the mounting region 33 is formed.

  Each product formation region 32 is partitioned by a scribe line (separation region), and basically has the same structure and planar shape as the wiring substrate 2 shown in FIGS. The wiring board 2 is formed by individually dividing a plurality of product forming regions 32 of the multi-wiring board 30. In the present embodiment, the multi-wiring board 30 is not limited to this, but has a configuration including, for example, a total of four product formation regions 32 arranged in a matrix arrangement of two in the X direction and two in the Y direction. Yes.

  Next, the structure of the molding die used in the molding process (resin sealing process) during the manufacturing process of the memory module 1 will be described with reference to FIGS. The configuration of the molding die will be described in a state where the multi-wiring board is positioned and clamped between the upper die and the lower die of the molding die.

  As shown in FIGS. 18 and 19, the molding die 40 has an upper die 41 and a lower die 42 that overlap in the vertical direction, and further includes a pot, a cull portion 46, a runner (resin flow passage) 45, and a resin injection gate. 44, a sealing cavity (resin sealing body forming portion) 43, and the like. The multi-wiring board 30 is disposed between the clamping surface (mating surface) 41a of the upper mold 41 and the clamping surface (mating surface) 42a of the lower mold 42, and when the upper mold 41 and the lower mold 42 are clamped. It is clamped and fixed by the clamping force.

  The cull portion 46, the runner 45, the resin injection gate 44, and the sealing cavity 43 are not limited to this. For example, the cull portion 46, the runner 45, and the sealing cavity 43 are provided on the upper mold 41 side and are recessed in the depth direction from the clamping surface 41 a of the upper mold 41. It is comprised by the recessed part. The pot is not limited to this, but is provided on the lower mold 42 side, for example, and is disposed at a position overlapping the cull portion 46 in a planar manner.

  The sealing cavity 43 is positioned on the main surface of the multi-wiring board 30 so as to cover the four product-forming areas 32 of the multi-wiring board 30, and collectively includes the four product-forming areas 32 of the multi-wiring board 30. It is formed in a size to cover (planar size). The planar shape of the sealing cavity 43 is a rectangle corresponding to the planar shape of the multi-wiring substrate 30.

  A plurality of runners 45 are provided. The plurality of runners 45 are arranged along one side of the multi-wiring board 30. The plurality of runners 45 extend across the inside of the multi-wiring board 30 across one side of the multi-wiring board 30. One end side of each of the plurality of runners 45 is connected to the sealing cavity 43, and the other end side of each of the plurality of runners 45 is connected to a plurality of cull portions 46 provided corresponding to the plurality of runners 45.

  The resin injection gate 45 is provided at the connection portion between the runner 45 and the sealing cavity 43, and the same number as the runner 45 is provided. The runner 45 is a resin flow path for flowing resin from the pot to the sealing cavity 43, and the resin injection gate 44 is an inlet for the resin injected into the sealing cavity 43 and controls the flow rate. Is.

  As shown in FIG. 19, the sealing cavity 43 is higher than the mounting height h1 (see FIG. 4) of the two semiconductor memory devices 10 mounted in two layers (from the main surface of the multi-wiring board 30). A first portion 43a having a high depth 43ah, and a first portion 43a that is continuous with the first portion 43a and has a height (depth from the main surface of the multi-wiring substrate 30) 43bh that is higher than the first portion 43a. 2 portion 43b (h1 <43ah <43bh).

  As shown in FIG. 20, in the second portion 43b, the injection direction 48a of the resin injected from the runner 45 into the sealing cavity 43 and the resin injected into the sealing cavity 43 from the plurality of runners 45 are sealed. It extends along a direction that intersects the resin flow direction 48b that flows from one side of the stop cavity 43 toward the other side opposite to it. In the present embodiment, the second portion 43b is one for two product formation regions 32 arranged along one side of the multi-wiring substrate 30 (the side crossed by the runner 45), and one side of the multi-wiring substrate 30. A total of two are provided, one for the two product forming regions 32 arranged along the other side of the opposite side. The second portion 43b has a smaller planar area than the first portion 43a.

Next, manufacture of the memory module 1 will be described with reference to FIGS.
First, the semiconductor memory devices 10a and 10b shown in FIG. 5 are prepared. Semiconductor memory devices 10a and 10b are mainly formed by a manufacturing process including a die bonding step <101> to an appearance inspection step <105> shown in FIG. In the die bonding step <101>, the semiconductor chips 12 and 13 are bonded and fixed to the main surface and the back surface of the die pad 15 of the lead frame, respectively. In the wire bonding step <102>, the plurality of electrode pads 14 of the semiconductor chips 12 and 13 and the plurality of leads 16 of the lead frame are electrically connected by the plurality of bonding wires 17, respectively. In the resin sealing step <103>, the semiconductor chips 12 and 13, the inner portions of each of the plurality of leads 16, the plurality of bonding wires 17, and the like are resin-sealed to form the resin sealing body 18. In the characteristic inspection step <104>, operation tests of the semiconductor memory devices 10a and 10b are performed to select grades and defects. In the appearance inspection step <105>, defective inspection is performed by inspecting appearance of the resin sealing body 18 such as burrs and scratches, and inspecting lead bending and flatness of the leads 16 protruding from the resin sealing body 18.

  Next, as shown in FIG. 17, the semiconductor memory devices 10 a and 10 b are mounted on each product mounting area 33 of each product forming area 32 of the multi-wiring substrate 30 in a two-tiered manner, and the center of each product forming area 32 is mounted. A plurality of capacitors 5 are mounted on the portion (mounting step <201> in FIG. 16). The semiconductor memory devices 10a and 10b and the capacitor 5 are mounted by, for example, screen printing on the electrode pads 25 and the chip selection electrode pads (25a1, 25b1, 25a2, and 25b2) in the product mounting region 33 and the passive component electrode pads. Solder pace material is supplied, and then the product mounting area 33 so that the leads 16 of the semiconductor memory devices 10a and 10b are positioned on the electrode pads 25 and the chip selection electrode pads (25a1, 25b1, 25a2, 25b2). The semiconductor memory devices 10a and 10b are disposed in a two-layered manner on top of each other, and the capacitor 5 is disposed on the passive component electrode pads, and then the solder material is melted.

  Next, as shown in FIGS. 18 and 19, the multi-wiring board 30 is positioned and clamped between the upper mold 41 and the lower mold 42 of the molding die 40 (resin sealing step <202 in FIG. 16). >).

  Next, as shown in FIGS. 18 and 19, with the multi-wiring substrate 30 clamped, a fluid resin (from the pot through the cull portion 46, the runner 45 and the resin injection gate 44 to the inside of the sealing cavity 43 ( Thermosetting resin) is injected under pressure, and then the resin is cured to form a resin sealing body 47 as shown in FIGS. 21 and 22 (resin sealing step <202> in FIG. 16).

  Next, after performing a curing step for stabilizing the curing of the resin sealing body 47, the molding die 40 is opened and the multi-wiring substrate 30 is taken out from the molding die 40.

  Next, on the upper surface of the resin sealing body 47 corresponding to each product formation region 32 of the multi-wiring board 30, for example, an identification mark such as a product name, a company name, a product type, a production lot number, etc., an inkjet marking method, a direct printing method, It forms using a laser marking method etc. (marking process <203> of FIG. 16).

  Next, as shown in FIG. 23, the resin sealing body 47 and the multi-wiring board 30 are divided into a plurality of small pieces (individual pieces) corresponding to the respective product formation regions 32 (individualization step <204 in FIG. 16). >). For example, as shown in FIG. 23, this division is performed by dicing the multi-wiring board 30 and the resin sealing body 47 with a dicing blade along dicing lines that divide the product forming regions 32 of the multi-wiring board 30. Is called. By this step, the memory module 1 having an external structure as shown in FIG. 1 is almost completed.

  Next, an operation test of the memory module 1 is performed to select a grade and a defect (characteristic inspection step <205> in FIG. 16).

  Next, an appearance inspection such as burrs and scratches on the resin sealing body 3 is performed to select defects (an appearance inspection step <206> in FIG. 16). Thereafter, the identification label 4 is affixed to the upper surface of the resin sealing body 3 of the memory module 1 (identification label affixing step <207> in FIG. 16), whereby the memory module 1 shown in FIG. 1 is completed.

  The memory module 1 is used by being incorporated in, for example, a pachinko machine that is one of the gaming machines. The memory module 1 is mounted in a detachable state on the mounting substrate 50 via a socket 51 as shown in FIG. 24 in order to facilitate rewriting of electronic information accompanying a change in the function of the pachinko machine.

  The socket 51 includes a base member 52 provided with a storage portion for storing the memory module 1, and a lid member 53 that covers the memory module 1 attached to the storage portion of the base member 52. In the housing portion of the base member 52, a plurality of contact pins 54 shown in FIG. 25 are arranged corresponding to the plurality of external connection terminals (electrode pads 26, 26s) of the memory module 1. The contact pin 54 includes a pin main body 54a that passes straight through the inside of the base member 52, a bending allowance portion 54b that is connected to the pin main body 54a and that protrudes to the side in a substantially U shape, and is bent. The connection portion 54c protrudes upward from the intermediate portion of the portion 54b. The contact pin 54 is made of spring steel such as phosphor bronze.

  The socket 51 presses the memory module 1 mounted in the storage portion of the base member 52 downward with the lid member 53, whereby a plurality of external connection terminals (26, 26 s) arranged on the back surface of the memory module 1. ) And the contact portions 54c of the plurality of contact pins 54 are in contact with each other, and electrical conduction is achieved. As shown in FIG. 25, the connection portion 54c of the contact pin 54 is connected to the external connection terminals (26, 26s) while rubbing the external connection terminals (26, 26s) on the back surface of the memory module 1 from the outer periphery to the inner side. 26, 26s). A structure in which the connection portion 54c of the contact pin 54 moves from the outside toward the inside is called an inner wiping structure.

  By the way, in the pachinko machine, for example, eight 512 Mbit semiconductor memory devices are used to store electronic information such as images and sounds. These eight semiconductor memory devices are mounted in a detachable state on a mounting board via a socket in order to facilitate rewriting of electronic information accompanying a change in function of the pachinko machine.

  However, in the mounting of the semiconductor memory device by the socket, since eight corresponding sockets are arranged for each of the eight semiconductor memory devices, the semiconductor memory device must be originally mounted in the corresponding socket. Incorrect mounting is likely to occur when another semiconductor memory device is mounted by mistake.

  On the other hand, as shown in FIG. 2, the memory module 1 of the present embodiment is modularized by mounting eight semiconductor memory devices 10 on the main surface 2x of the wiring board 2, so that the memory is stored in the socket 51. By mounting the module 1, eight semiconductor memory devices 10 are mounted in the socket. Therefore, it is possible to reduce erroneous mounting of the semiconductor memory device 10 in the socket as compared with the case where one semiconductor memory device is mounted in one socket.

In addition, since it is not necessary to mount each of the eight semiconductor storage devices 10 in the corresponding eight sockets, the number of mounting of the semiconductor storage device 10 in the socket can be reduced.
Further, since it is not necessary to arrange eight sockets on the mounting substrate, the mounting substrate 50 can be reduced in size.

  In the pachinko machine, when one semiconductor memory device is mounted in one socket, in order to prevent fraud, all of the contents of the semiconductor memory device can be identified from the Secure Electronic Communication Technology Association (Hotsukyo Association). It is mandatory to attach an identification label to the semiconductor memory device. For this reason, it is necessary to affix the identification label for each semiconductor memory device one by one, which is cumbersome and time-consuming.

  On the other hand, as shown in FIG. 2, in the memory module 1 of the present embodiment, eight semiconductor memory devices 10 are mounted on the main surface 2x of the wiring board 2, and further eight semiconductor memory devices 10 are made of resin. Since the resin sealing is performed by the sealing body 3, the identification labels to be attached to the eight semiconductor memory devices 10 can be omitted by attaching the identification labels 4 to the resin sealing body 3 of the memory module 1. Therefore, as compared with the case where the identification labels are attached to all the eight semiconductor memory devices 10, the labor caused by the application of the identification labels can be reduced.

  The TSOP type semiconductor memory device has a package structure in which a lead electrically connected to an electrode pad of a semiconductor chip protrudes from a side surface of a resin sealing body and is bent into a predetermined shape. The lead is easily deformed, and poor contact with the socket is likely to occur.

  On the other hand, the memory module 1 of this embodiment has an LGA type package structure in which a plurality of electrode pads 26 are arranged as external connection terminals on the back surface of the wiring board 2 as shown in FIG. There is no problem that the lead is deformed by attaching / detaching to / from the socket unlike the TSOP type semiconductor device. Therefore, the memory module 1 having high connection reliability with the socket 51 can be provided.

  In the memory module 1 of this embodiment, as shown in FIG. 2, eight semiconductor memory devices 10 mounted on the main surface 2x of the wiring board 2 are sealed with a resin sealing body 3. In this way, by sealing the eight semiconductor memory devices 10 with the resin sealing body 3, compared to the case where the eight semiconductor memory devices are simply covered with a cover member such as a metal case, the resin sealing is performed. Since the body 3 cannot be easily removed, the memory module 1 with high reliability against fraud can be provided.

  Even in the TSOP type semiconductor memory device, an index indicating the direction is provided on the upper surface of the resin sealing body, but the TSOP type semiconductor device is symmetrical with respect to the center line along the direction of the lead arrangement. Even if it is reversed, it can be mounted in the socket, and there is a concern that it may be erroneously mounted in the socket in the opposite direction.

  On the other hand, the resin sealing body 3 of the memory module 1 of the present embodiment has a mounting height (the main surface of the wiring board 2) of the two semiconductor memory devices 10 mounted in two layers as shown in FIG. The first portion 3a having a thickness t1 (thickness from the main surface 2x to the upper surface of the wiring board 2) t1 greater than h1 (height from the top surface of the resin sealing body of the upper semiconductor memory device 10b to h1); And a second portion 3b that is continuous with the first portion 3a and has a thickness t2 (thickness from the main surface 2x to the upper surface of the wiring board 2) t2 that is thicker than the first portion 3a. It has an external structure in which a step extending along one side of the wiring board 2 is provided on the upper surface. By providing a step on the lid member 53 of the socket 51 corresponding to this step, the memory module 1 cannot be mounted in the socket 51 when the orientation is wrong. Therefore, it is possible to suppress erroneous mounting with respect to the directionality of the memory module 1 to the socket.

  The memory module 1 according to the present embodiment includes four semiconductor memory devices 10a arranged in a plane on the main surface 2x of the wiring board 2, and each of the semiconductor memory devices 10a corresponding to the four semiconductor memory devices 10a. Since the four semiconductor memory devices 10b arranged are resin-sealed by one resin sealing body 3, the resin sealing is performed more than the mounting height h1 of the two semiconductor memory devices 10 mounted in two layers. It is difficult to reduce the thickness of the body 3 and form a step on the upper surface of the resin sealing body 3. Therefore, as in the present embodiment, the first portion 3a having a thickness t1 larger than the mounting height h1 of the two semiconductor memory devices 10 mounted in two layers is connected to the first portion 3a. The second portion 3b is thicker than the first portion 3a (thickness from the main surface 2x to the upper surface of the wiring substrate 2) t2 and extends along one side of the wiring substrate 2 on the upper surface. It is desirable to make the resin sealing body 3 provided with existing steps.

  When the resin sealing body 3 is partially thickened and a step is provided on the upper surface of the resin sealing body 3 as in the present embodiment, the amount of resin increases, so the wiring board 2 and the resin sealing The wiring board 2 is likely to warp due to the influence of stress resulting from the difference in linear expansion coefficient with the body 3. Therefore, as in this embodiment, it is desirable that the second portion 3b of the resin sealing body 3 has a smaller planar area than the first portion 3a.

  In the memory module 1 of the present embodiment, as shown in FIG. 2, each of the lower and upper four semiconductor memory devices (10 a and 10 b) has two adjacent semiconductor memory devices along the outer periphery of the wiring board 2 ( 10a and 10b), the resin sealing bodies 18 are disposed so as to surround the central portion of the main surface 2x of the wiring board 2 in a state where the directions of the resin sealing bodies 18 are different by 90 degrees, in other words, in a state where the tips of the leads 16 do not face each other. ing.

  By adopting such a configuration, the linear expansion coefficient between the wiring substrate 2 and the resin sealing body 3 can be increased as compared with the case where the tips of the leads of adjacent semiconductor devices are arranged to face each other. Since the resulting stress can be dispersed, warping of the wiring board 2 can be suppressed. As a result, the flatness of the plurality of external connection terminals arranged on the back surface of the memory module 1 can be ensured, and poor contact between the external connection terminals of the memory module 1 and the lead pins of the socket 51 can be suppressed. The memory module 1 with high connection reliability can be provided.

  In the socket 51, as shown in FIG. 25, the connection portion 54c of the contact pin 54 is used for external connection on the back surface of the memory module 1 from the outer periphery to the inner side when the memory module 1 is mounted in the socket. The terminal (26, 26s) is connected to the external connection terminal (26, 26s) while rubbing the terminal (26, 26s). In the case of this inner wiping structure, since the connection portions of the two contact pins corresponding to the two electrode pads adjacent to each other across the corner 2s on the back surface of the wiring board 2 are close to each other, there is a concern that they may be short-circuited. Is done.

  Therefore, by connecting the two electrode pads adjacent to each other with the corner 2s of the wiring board 2 as the electrode pads that are fixed to the reference potential, the connection portions of the two contact pins corresponding to the two electrode pads can be obtained. There is no electrical failure even when touching. In this embodiment, as shown in FIG. 3, the electrode having a planar shape in which the length of each side along the two sides of the corner 2 s is wider than the width (short side) of the electrode pad 26 on the back surface of the wiring board 2. Pads 26s are arranged at the four corners 2s, respectively. By adopting such a configuration, even if the connection portions of the two contact pins connected to the electrode pad 26s are in close contact with each other, no electrical failure occurs. Connection reliability can be improved.

  In the batch molding method, the ratio of the flat area to the thickness (height) of the sealing cavity becomes very large, so that the thermosetting resin begins to harden and the flowability is reduced. Therefore, it is necessary to quickly and uniformly fill the thermosetting resin. In order to quickly and uniformly fill the thermosetting resin, it is necessary to reduce the difference in flow rate in the planar direction of the thermosetting resin flowing in the sealing cavity from the resin injection gate toward the opposite side as much as possible. is there. The thermosetting resin flows fast where the sealing cavity is thick and slow when the cavity is thin.

  In the present embodiment, as shown in FIG. 19, the sealing cavity 43 is higher than the mounting height h1 (see FIG. 4) of the two semiconductor memory devices 10 mounted in a two-layer stack (multi-wiring board). The first portion 43a having a high 43ah (depth from the main surface 30) and the first portion 43a are connected to the first portion 43a and are higher than the first portion 43a (the depth from the main surface of the multi-wiring board 30). ) 43bh is a second portion 43b having a high height, and the second portion 43b is, as shown in FIG. 20, the injection direction 48a of the resin injected into the sealing cavity 43 from the runner 45 through the resin injection gate 44. As well as extending in the direction intersecting the flow direction 48b of the resin flowing in the sealing cavity 43 from the resin injection gate 44 side toward the opposite side, the second portion 43b is Resin injection direction Compared with the case of extending in the direction along the flow direction 48b of the resin 8a and the resin, the flow rate difference in the plane direction of the thermosetting resin flowing in the sealing cavity 43 from the resin injection gate 44 toward the opposite side. Can be reduced. Therefore, by forming the sealing cavity 43 as in the present embodiment, the thermosetting resin can be filled quickly and uniformly, so that generation of voids can be suppressed and the manufacturing yield of the memory module 1 can be improved. Can be achieved.

  As shown in FIG. 10, the chip selection electrode pads 25a1 and 25b1 and the chip selection electrode pads 25a2 and 25b2 are spaced apart from each other along a direction perpendicular to the arrangement direction of the electrode pads 25 in series. And are electrically separated. The chip selection electrode pads 25a1 and 25a2 are disposed inside the chip selection electrode pads 25b1 and 25b2.

  As shown in FIG. 11, the wiring 21a is connected to the chip selection electrode pad 25a1, and the wiring 21b is connected to the chip selection electrode pad 25b1. The wiring 21a is drawn from the chip selection electrode pad 25a1 to the inside of the electrode pad group, and the wiring 21b is drawn from the chip selection electrode pad 25b1 to the outside of the electrode pad group.

  For example, when the adjacent product mounting areas 33 are arranged so that the electrode pad groups face each other, an area for routing the wiring 21b between the adjacent product mounting areas 33 is necessary. The product mounting area 33 is the main surface 2x of the wiring board 2 in the two product mounting areas 33 adjacent along the outer periphery of the wiring board 2 with the directions of the first and second pad groups being 90 degrees different from each other. Therefore, a region for routing the wiring 21b between the adjacent product mounting regions 33 is not necessary. Therefore, in this embodiment, the memory module 1 can be downsized.

FIG. 26 is a schematic bottom view of a memory module which is a modification of the embodiment of the present invention.
As shown in FIG. 26, this modification is an example in which two electrode pads 26m adjacent to each other with the corner 2s of the wiring board 2 interposed therebetween are electrode pads whose potential is fixed to a reference potential. By adopting such a configuration, even if the connection portions of the two contact pins corresponding to the two electrode pads are in contact with each other, no electrical failure occurs.

  By the way, a module is known in which a plurality of semiconductor chips are mounted directly on the main surface of a wiring board, and the plurality of semiconductor chips are resin-sealed with a resin sealing body. In this module, when a defect is found in a semiconductor chip before resin sealing, it is difficult to replace only the defective semiconductor chip. On the other hand, in the memory module 1 of this embodiment, since the semiconductor memory device in which the semiconductor chip is packaged is mounted on the wiring board, if a defect is found in the semiconductor memory device before resin sealing, Since only the semiconductor memory device can be easily replaced, the manufacturing yield of the memory module 1 can be improved.

  In the above-described embodiment, the example in which the resin sealing body 3 is used as the cover member that covers the plurality of semiconductor storage devices 10 has been described. However, if the reliability against fraud is not taken into consideration, a plurality of simple cover members may be used. The semiconductor memory device 10 may be covered.

  As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, in the present embodiment, the case where the semiconductor memory device 10 has a TSOP type package structure has been described, but a plurality of leads (first external connection terminals) 16 are on the mounting surface (the lower surface of the resin sealing body 18) side. It may be a QFN type package structure, a BGA type package structure, or an LGA type package structure that protrudes (exposes). Thereby, as shown in FIG. 27, since the plurality of leads (first external connection terminals) 16 do not protrude from the side surface of the resin sealing body 18, the semiconductor memory device 10 manufactured with the TSOP type package structure is wired. Compared with the case where the semiconductor memory device 55 is mounted on the main surface of the substrate 2, the semiconductor memory device 55 can be further reduced in size. However, as described above, in the QFN type package structure, the BGA type package structure, and the LGA type package structure, the plurality of leads (first external connection terminals) 16 are exposed on the mounting surface side. As described above, it is difficult to further stack the semiconductor memory device 10 on the semiconductor memory device. As a result, the total capacity of the memory module 1 obtained is lower than when the semiconductor memory device 10 is manufactured with the TSOP type package structure.

  Further, for example, in the present embodiment, it has been described that the EEPROM is formed as the memory circuit on each of the main surfaces of the semiconductor chips 12 and 13, but a NOR type, an AND type, and a NAND type may be used. However, unlike the NOR type, the AND type and the NAND type have a minute defect portion in their characteristics. Therefore, an ASIC (control IC) for supporting the processing operation of the memory is necessary to compensate for the missing portion. Therefore, when using a semiconductor chip on which an AND-type or NAND-type storage circuit is formed, a semiconductor chip having an ASIC on its main surface is also mounted in the memory module 1. As a result, it is possible to configure a memory module capable of performing higher-speed processing than the memory module 1 configured of an EEPROM or a semiconductor chip having a NOR type storage circuit.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure ((a) is a typical top view, (b) is a typical side view) which shows the external appearance structure of the memory module which is one Example of this invention. 1A and 1B are diagrams illustrating an internal structure of the memory module in FIG. 1 (a is a schematic plan view in which a resin sealing body is omitted, and FIG. 1b is a schematic cross-sectional view taken along line a′-a ′ in FIG. 1a). is there. FIG. 2 is a schematic bottom view of the memory module of FIG. 1. FIG. 3 is an enlarged schematic cross-sectional view of FIG. FIG. 5 is a schematic cross-sectional view in which a part of FIG. 4 is enlarged. FIG. 6 is a development view showing FIG. 5 in a simplified manner. 7A is a schematic plan view showing the external structure of the semiconductor memory device of FIG. 6, and FIG. 7B is a schematic plan view of the upper semiconductor memory device. FIG. FIG. 7 is a development view schematically showing a first cross section different from FIG. 6. FIG. 7 is a development view schematically showing a second cross section different from FIG. 6. FIG. 6 is a schematic plan view showing an arrangement pattern of electrode pads arranged on the main surface of the wiring board of FIG. 5. FIG. 6 is a schematic plan view showing a first layer wiring pattern in the wiring board of FIG. 5. FIG. 6 is a schematic plan view showing a second-layer wiring pattern in the wiring board of FIG. 5. FIG. 6 is a schematic plan view showing a third layer wiring pattern in the wiring board of FIG. 5. FIG. 6 is a schematic plan view showing a fourth layer wiring pattern in the wiring board of FIG. 5. It is a typical top view showing a schematic structure of a multi wiring board used for manufacture of a memory module which is one example of the present invention. It is a flowchart which shows the manufacturing process of the memory module which is one Example of this invention. 1 is a schematic plan view showing a state in which a semiconductor memory device is mounted on a multi-wiring board in the manufacture of a memory module that is one embodiment of the present invention. FIG. 5 is a schematic perspective plan view showing a state in which a multi-wiring board is clamped to a molding die in manufacturing a memory module according to an embodiment of the present invention. It is typical sectional drawing which follows the b'-b 'line | wire of FIG. FIG. 19 is a schematic perspective plan view showing details of the sealing cavity of FIG. 18. FIG. 4 is a schematic perspective plan view showing a state in which a resin sealing body is formed by injecting resin into a sealing cavity of a molding die in manufacturing a memory module according to an embodiment of the present invention. It is typical sectional drawing which follows the c'-c 'line | wire of FIG. FIG. 5 is a schematic plan view showing a state in which a multi-wiring board and a resin sealing body are fragmented in the manufacture of a memory module according to an embodiment of the present invention. It is typical sectional drawing which shows the state which mounted | wore the socket with the memory module which is one Example of this invention. It is a schematic diagram for demonstrating the contact operation | movement of the contact pin of the socket of FIG. It is a typical bottom view of the memory module which is a modification of one Example of this invention. It is a typical bottom view of the memory module which is a modification of one Example of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory module (electronic device), 2 ... Wiring board, 3 ... Resin sealing body, 4 ... Identification label, 5 ... Capacitor (passive component), 10 ... Semiconductor device, 11 ... Semiconductor chip, 14 ... Electrode pad, 15 DESCRIPTION OF SYMBOLS ... Die pad, 16 ... Lead, 17 ... Bonding wire, 18 ... Resin sealing body, 21 ... First layer wiring pattern, 22 ... Second layer wiring pattern, 23 ... Third layer wiring pattern, 24 ... 4th layer wiring pattern, 25, 25a1, 25a2, 25b1, 25b2 ... Electrode pad, 26, 26m, 26s ... Electrode pad, 27a, 27b ... Protective film, 30 ... Multi-wiring board, 31 ... Mold area (resin Sealing area), 32 ... Product formation area, 33 ... Product mounting area, 40 ... Mold, 41 ... Upper mold, 41a ... Nipping surface, 42 ... Lower mold, 42a ... Nipping surface, 43 ... For sealing Cavite (Resin sealing body forming part), 44 ... resin injection gate, 45 ... runner, 46 ... cull part, 47 ... resin sealing body, 50 ... mounting substrate, 51 ... socket, 52 ... base member, 53 ... lid member, 54: Contact pin, 55: Semiconductor memory device.

Claims (35)

A plurality of semiconductor devices in which a semiconductor chip is sealed by a resin sealing body, and a plurality of first external connection terminals electrically connected to the semiconductor chip are exposed from the resin sealing body;
A wiring board having a main surface and a back surface located on opposite sides, wherein the plurality of semiconductor devices are mounted on the main surface;
An electronic device comprising: a cover member provided on a main surface of the wiring board so as to cover the plurality of semiconductor devices. The electronic device according to claim 1,
The plurality of first external connection terminals protrude from a side surface of the resin sealing body. The electronic device according to claim 1,
An electronic device, wherein an identification label is affixed to the cover member. The electronic device according to claim 1,
An electronic device, wherein a plurality of electrode pads are arranged as second external connection terminals on the back surface of the wiring board. The electronic device according to claim 1,
The electronic device, wherein the cover member is a resin sealing body that seals the plurality of semiconductor devices. The electronic device according to claim 1,
The plurality of semiconductor devices include a plurality of first semiconductor devices arranged in a plane on a main surface of the wiring board, and the plurality of first semiconductor devices corresponding to the plurality of first semiconductor devices. And a plurality of second semiconductor devices disposed in the electronic device. The electronic device according to claim 1,
The electronic device is characterized in that the semiconductor chip is one of a NOR type, an AND type, a NAND type, an ASIC, or an EEPROM capable of electrically rewriting electronic information. A plurality of semiconductor devices in which a semiconductor chip is sealed by a first resin sealing body, and a plurality of first external connection terminals electrically connected to the semiconductor chip are exposed from the resin sealing body;
A wiring board having a main surface and a back surface located on opposite sides, and a plurality of second external connection terminals disposed on the back surface, wherein the plurality of semiconductor devices are mounted on the main surface;
An electronic device comprising: a second resin sealing body that is formed on a main surface of the wiring board and seals the plurality of semiconductor devices. The electronic device according to claim 8.
The plurality of first external connection terminals protrude from a side surface of the resin sealing body. The electronic device according to claim 8.
An electronic device, wherein an identification label is attached to the second resin sealing body. The electronic device according to claim 8.
The electronic device according to claim 2, wherein the second external connection terminal is an electrode pad made of a conductive film. The electronic device according to claim 8.
The plurality of semiconductor devices include a plurality of first semiconductor devices arranged in a plane on a main surface of the wiring board, and the plurality of first semiconductor devices corresponding to the plurality of first semiconductor devices. And a plurality of second semiconductor devices disposed in the electronic device. The electronic device according to claim 8.
The electronic device is characterized in that the semiconductor chip is one of a NOR type, an AND type, a NAND type, an ASIC, or an EEPROM capable of electrically rewriting electronic information. A plurality of semiconductor devices in which a semiconductor chip is sealed by a first resin sealing body, and a plurality of first external connection terminals electrically connected to the semiconductor chip are exposed from the resin sealing body;
A wiring board having a main surface and a back surface located on opposite sides, and a plurality of second external connection terminals disposed on the back surface, wherein the plurality of semiconductor devices are mounted on the main surface;
A second resin sealing body that is formed on a main surface of the wiring board and seals the plurality of semiconductor devices;
The second resin sealing body includes a first portion that is thicker than a height after mounting the semiconductor device, and a second portion that is continuous with the first portion and is thicker than the first portion. An electronic device comprising: The electronic device according to claim 14.
The plurality of first external connection terminals protrude from a side surface of the resin sealing body. The electronic device according to claim 14.
The electronic device according to claim 1, wherein the second portion has a smaller area than the first portion. The electronic device according to claim 14.
The second resin encapsulant is formed with a rectangular plane.
The electronic device, wherein the second portion is formed along one side of the second resin sealing body. The electronic device according to claim 14.
The electronic device according to claim 2, wherein the second external connection terminal is an electrode pad made of a conductive film. The electronic device according to claim 14.
The plurality of semiconductor devices include a plurality of first semiconductor devices arranged in a plane on a main surface of the wiring board, and the plurality of first semiconductor devices corresponding to the plurality of first semiconductor devices. And a plurality of second semiconductor devices disposed in the electronic device. The electronic device according to claim 14.
The electronic device is characterized in that the semiconductor chip is one of a NOR type, an AND type, a NAND type, an ASIC, or an EEPROM capable of electrically rewriting electronic information. A plurality of semiconductor devices in which a semiconductor chip is sealed by a first resin sealing body, and a plurality of first external connection terminals electrically connected to the semiconductor chip are exposed from the resin sealing body;
A wiring board having a main surface and a back surface located on opposite sides, and a plurality of second external connection terminals disposed on the back surface, wherein the plurality of semiconductor devices are mounted on the main surface;
A second resin sealing body that is formed on a main surface of the wiring board and seals the plurality of semiconductor devices;
The plurality of first resin sealing bodies has a planar shape of a rectangle,
The short side of said 1st resin sealing body is arrange | positioned in the state which faces the long side of said adjacent 1st resin sealing body, The electronic device characterized by the above-mentioned. The electronic device according to claim 21, wherein
The plurality of first external connection terminals protrude from a side surface of the resin sealing body. The electronic device according to claim 21, wherein
Having passive components mounted on the main surface of the wiring board;
The plurality of semiconductor devices are disposed between the passive component and the periphery of the wiring board. The electronic device according to claim 21, wherein
The electronic device according to claim 1, wherein the passive component is disposed at a central portion of a main surface of the wiring board. The electronic device according to claim 21, wherein
The electronic device according to claim 2, wherein the second external connection terminal is an electrode pad made of a conductive film. The electronic device according to claim 21, wherein
The plurality of semiconductor devices include a plurality of first semiconductor devices arranged in a plane on a main surface of the wiring board, and the plurality of first semiconductor devices corresponding to the plurality of first semiconductor devices. And a plurality of second semiconductor devices disposed in the electronic device. The electronic device according to claim 21, wherein
The electronic device is characterized in that the semiconductor chip is one of a NOR type, an AND type, a NAND type, an ASIC, or an EEPROM capable of rewriting electronic information. A wiring board having a main surface and a back surface located on opposite sides of each other, and a flat surface formed in a rectangular shape;
A plurality of electrode pads arranged along each side of the wiring board on the back surface of the wiring board;
A plurality of semiconductor devices mounted on the main surface of the wiring board;
A resin sealing body that is formed on a main surface of the wiring board and seals the plurality of semiconductor devices;
Two of the plurality of electrode pads, which are adjacent to each other across a corner of the wiring board, are electrode pads whose potential is fixed to a reference potential. A wiring board having a main surface and a back surface located on opposite sides of each other, and a flat surface formed in a rectangular shape;
A plurality of semiconductor devices mounted on the main surface of the wiring board;
A resin sealing body that is formed on a main surface of the wiring board and seals the plurality of semiconductor devices;
A plurality of first electrode pads disposed on the back surface of the wiring board along each side of the wiring board;
A second electrode pad disposed at a corner of the back surface of the wiring board and having a width wider than the first electrode pad;
2. The electronic device according to claim 1, wherein the second electrode pad is an electrode pad whose potential is fixed to a reference potential. (A) A semiconductor chip is sealed with a first resin sealing body, and a plurality of first external connection terminals electrically connected to the semiconductor chip are exposed from the first resin sealing body. A step of preparing a semiconductor device;
(B) mounting the plurality of semiconductor devices on the main surface of the wiring board;
(C) forming a second resin sealing body for resin-sealing the plurality of semiconductor devices mounted on the main surface of the wiring board. The method of manufacturing an electronic device according to claim 30,
The plurality of first external connection terminals protrude from a side surface of the resin sealing body. The method of manufacturing an electronic device according to claim 30,
After the step (c), the method for manufacturing an electronic device includes a step of attaching an identification label to the second resin sealing body. (A) A plurality of semiconductor chips are sealed with a first resin sealing body, and a plurality of first external connection terminals electrically connected to the semiconductor chips are exposed from the first resin sealing body. Preparing a semiconductor device of
(B) mounting the plurality of semiconductor devices on the main surface of the wiring board;
(C) Resin sealing located on the main surface of the wiring board so as to cover the plurality of semiconductor devices mounted on the wiring board when the wiring board is disposed between the upper mold and the lower mold A step of preparing a molding die having a body forming portion and a resin flow passage continuing to the resin sealing body forming portion;
(D) The wiring board is mounted on the wiring board by placing the wiring board between the upper mold and the lower mold of the molding die and injecting resin into the resin sealing body forming portion through the resin flow path. Forming a second resin sealing body for resin-sealing the plurality of semiconductor devices,
The resin sealing body forming portion is connected to the first portion having a height from the main surface of the wiring substrate higher than the mounting height of the semiconductor device mounted on the wiring substrate, and the first portion. A second portion having a height from the main surface of the wiring board higher than that of the first portion;
In the electronic device, the second portion extends along a direction intersecting an injection direction of the resin injected from the resin flow passage into the resin sealing body forming portion. Production method. The method of manufacturing an electronic device according to claim 33,
The plurality of first external connection terminals protrude from a side surface of the resin sealing body. The method of manufacturing an electronic device according to claim 33,
The method of manufacturing an electronic device, wherein the second portion has an area smaller than that of the first portion.

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