JP2007173606A5 - - Google Patents
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- Publication number
- JP2007173606A5 JP2007173606A5 JP2005370587A JP2005370587A JP2007173606A5 JP 2007173606 A5 JP2007173606 A5 JP 2007173606A5 JP 2005370587 A JP2005370587 A JP 2005370587A JP 2005370587 A JP2005370587 A JP 2005370587A JP 2007173606 A5 JP2007173606 A5 JP 2007173606A5
- Authority
- JP
- Japan
- Prior art keywords
- electronic device
- wiring board
- main surface
- semiconductor devices
- electrode pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 16
- 239000011347 resin Substances 0.000 claims 6
- 229920005989 resin Polymers 0.000 claims 6
- 238000007789 sealing Methods 0.000 claims 5
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Claims (13)
主面と、前記主面に形成された複数の電極パッドと、前記主面とは反対側に位置する裏面と、前記裏面に形成された複数の第２外部接続用端子とを有し、前記複数の半導体装置のそれぞれの前記複数の第１外部接続用端子が前記複数の電極パッドとそれぞれ電気的に接続するように、前記主面に前記複数の半導体装置が実装された配線基板と、
前記複数の半導体装置を封止するように、前記配線基板の前記主面に形成されたカバー部材と、
を含むことを特徴とする電子装置。 A semiconductor chip, a plurality of semiconductor devices having a resin sealing body which seals said semiconductor chip and electrically connected to the plurality of first external connection terminals and each of said semiconductor chip,
Has a main surface, a plurality of electrode pads formed on said main surface, a rear surface located on the opposite side to the main surface, and a terminal for a plurality of second external connection formed on the back surface, the A wiring board on which the plurality of semiconductor devices are mounted on the main surface such that the plurality of first external connection terminals of each of the plurality of semiconductor devices are electrically connected to the plurality of electrode pads, respectively .
So as to seal the front Symbol plurality of semiconductor devices, and a cover member formed on the main surface of the wiring substrate,
An electronic device comprising:
前記複数の第１外部接続用端子は、前記樹脂封止体の側面から突出していることを特徴とする電子装置。 The electronic device according to claim 1,
It said plurality of first external connection terminal is an electronic device, characterized in that projecting from the side surface of the resin sealing body.
前記カバー部材に識別ラベルが貼り付けられていることを特徴とする電子装置。 The electronic device according to claim 1,
An electronic device, wherein an identification label is affixed to the cover member.
前記第２外部接続用端子は、導電膜から成る複数の電極パッドであることを特徴とする電子装置。 The electronic device according to claim 1,
Before SL for the second external connection terminal, an electronic device which is a plurality of electrode pads made of a conductive film.
前記カバー部材は、前記複数の半導体装置を封止する第２樹脂封止体であることを特徴とする電子装置。 The electronic device according to claim 1,
The electronic device according to claim 1, wherein the cover member is a second resin sealing body that seals the plurality of semiconductor devices.
前記複数の半導体装置は、前記配線基板の主面に平面的に配置された複数の第１半導体装置と、前記複数の第１半導体装置に対応して前記複数の第１半導体装置上に配置された複数の第２半導体装置とを含むことを特徴とする電子装置。 The electronic device according to claim 1,
Wherein the plurality of semiconductor devices, said plurality of first semi-conductor device which is planarly disposed in the main surface of the wiring board, the plurality of first semi-conductor device wherein a plurality of first semi-conductor device on in response to electronic apparatus which comprises a plurality of second semi-conductor device arranged.
前記半導体チップは、ＮＯＲ型、ＡＮＤ型、ＮＡＮＤ型、ＡＳＩＣ、又は電子情報の電気的な書き換えが可能なＥＥＰＲＯＭの何れかであることを特徴とする電子装置。 The electronic device according to claim 1,
The electronic device is characterized in that the semiconductor chip is one of a NOR type, an AND type, a NAND type, an ASIC, or an EEPROM capable of electrically rewriting electronic information.
前記第２樹脂封止体は、前記半導体装置の実装後の高さよりも厚い第１部分と、前記第１部分に連なり、前記第１部分よりも厚さが厚い第２部分とを有することを特徴とする電子装置。 The electronic device according to claim 5.
The second resin sealing body includes a first portion that is thicker than a height after the semiconductor device is mounted, and a second portion that is continuous with the first portion and is thicker than the first portion. Electronic device characterized.
前記第２部分は、前記第１部分よりも面積が小さいことを特徴とする電子装置。 The electronic device according to claim 8.
The electronic device according to claim 2, wherein the second portion has a smaller area than the first portion .
前記第２樹脂封止体は、平面が方形状で形成され、
前記第２部分は、前記第２樹脂封止体の一辺に沿って形成されていることを特徴とする電子装置。 The electronic device according to claim 8.
The second resin encapsulant is formed in a rectangular plane.
The electronic device , wherein the second part is formed along one side of the second resin sealing body .
前記配線基板の主面には、受動部品が実装されており、
前記複数の半導体装置は、前記受動部品と前記配線基板の周辺との間に配置されていることを特徴とする電子装置。 The electronic device according to claim 1 ,
Passive components are mounted on the main surface of the wiring board,
The plurality of semiconductor devices are disposed between the passive component and the periphery of the wiring board .
前記受動部品は、前記配線基板の主面の中央部に配置されていることを特徴とする電子装置。 The electronic device according to claim 11 .
The electronic device according to claim 1, wherein the passive component is disposed at a central portion of a main surface of the wiring board .
前記配線基板の前記裏面の平面は、方形状から成り、
前記複数の電極パッドは、前記配線基板の前記裏面の各辺に沿って配置され、
前記複数の電極パッドのうち、前記配線基板の角部を挟んで隣り合う２つの電極パッドは、基準電位に電位固定される電極パッドであることを特徴とする電子装置。 The electronic device according to claim 4 .
The plane of the back surface of the wiring board consists of a square shape,
The plurality of electrode pads are arranged along each side of the back surface of the wiring board,
Two of the plurality of electrode pads adjacent to each other across a corner of the wiring board are electrode pads whose potential is fixed to a reference potential .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005370587A JP4937581B2 (en) | 2005-12-22 | 2005-12-22 | Electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005370587A JP4937581B2 (en) | 2005-12-22 | 2005-12-22 | Electronic equipment |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011207291A Division JP2012023390A (en) | 2011-09-22 | 2011-09-22 | Electronic device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007173606A JP2007173606A (en) | 2007-07-05 |
| JP2007173606A5 true JP2007173606A5 (en) | 2009-02-12 |
| JP4937581B2 JP4937581B2 (en) | 2012-05-23 |
Family
ID=38299738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005370587A Expired - Fee Related JP4937581B2 (en) | 2005-12-22 | 2005-12-22 | Electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4937581B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012023390A (en) * | 2011-09-22 | 2012-02-02 | Renesas Electronics Corp | Electronic device |
| CN109564894B (en) * | 2016-08-05 | 2021-06-08 | 日产自动车株式会社 | Semiconductor capacitor |
| JP6969847B2 (en) * | 2018-04-25 | 2021-11-24 | 京セラ株式会社 | Wiring board |
| JP7128098B2 (en) * | 2018-11-27 | 2022-08-30 | 京セラ株式会社 | wiring board |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0211338A (en) * | 1988-06-30 | 1990-01-16 | Toshiba Corp | Wire dot printer |
| JPH02148756A (en) * | 1988-11-29 | 1990-06-07 | Mitsubishi Electric Corp | Package for integrated circuit |
| JP3123338B2 (en) * | 1993-04-05 | 2001-01-09 | 松下電器産業株式会社 | Integrated circuit device |
| JPH07142624A (en) * | 1993-11-17 | 1995-06-02 | Nec Corp | Semiconductor device |
| JP3417095B2 (en) * | 1994-11-21 | 2003-06-16 | 富士通株式会社 | Semiconductor device |
| JP3644662B2 (en) * | 1997-10-29 | 2005-05-11 | 株式会社ルネサステクノロジ | Semiconductor module |
| JP2000077820A (en) * | 1998-09-02 | 2000-03-14 | Mitsubishi Electric Corp | Mounting board |
| JP2000243894A (en) * | 1999-02-22 | 2000-09-08 | Sony Corp | Semiconductor module and its manufacture |
| JP3798597B2 (en) * | 1999-11-30 | 2006-07-19 | 富士通株式会社 | Semiconductor device |
| JP4562881B2 (en) * | 2000-08-18 | 2010-10-13 | イビデン株式会社 | Manufacturing method of semiconductor module |
| JP2002305286A (en) * | 2001-02-01 | 2002-10-18 | Mitsubishi Electric Corp | Semiconductor module and electronic component |
| JP2004064604A (en) * | 2002-07-31 | 2004-02-26 | Kyocera Corp | Transmission and reception controller |
| JP3819901B2 (en) * | 2003-12-25 | 2006-09-13 | 松下電器産業株式会社 | Semiconductor device and electronic apparatus using the same |
| JP2005302815A (en) * | 2004-04-07 | 2005-10-27 | Toshiba Corp | Laminated semiconductor package and its manufacturing method |
-
2005
- 2005-12-22 JP JP2005370587A patent/JP4937581B2/en not_active Expired - Fee Related
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