JP2006235164A - Substrate for electrooptical device, electrooptical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an inspection which eliminates the need for contacting by a probe from outside and in which sufficient measurement precision can be obtained. <P>SOLUTION: A matrix type display device which has pixels arranged at intersections of source lines and scanning lines is equipped with: an amplifier 4a which compares a potential signal supplied to one terminal so and a potential signal supplied to the other terminal se with each other, and generates an output by making the potential at the terminal so lower when the potential signal supplied to the terminal so is lower and so higher when the potential signal supplied to the terminal is higher; and a supply means 8a which supplies a precharge voltage between both the terminals, and supplies reference voltage 3a to the other terminal se, and reads out and supplies potential signals written to pixels to the other terminal. The display device is equipped with an equalizing means 8a which holds both the terminals at the same potential at least at the end of the supply of the precharge voltage, and comprises a P channel type transistor and an N channel type transistor connected to both the terminals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a substrate for an electro-optical device, an electro-optical device, and an electronic apparatus, and more particularly to a substrate for an electro-optical device, an electro-optical apparatus, and an electronic apparatus each having a plurality of switching elements provided in a plurality of pixels.

Conventionally, display devices such as liquid crystal devices have been widely used in devices such as mobile phones and projectors. 2. Description of the Related Art A liquid crystal display device using a TFT (Thin Film Transistor) or the like is configured by bonding a TFT substrate and a counter substrate and enclosing liquid crystal between both substrates. Generally, an inspection of whether or not a manufactured liquid crystal device operates normally is performed on a finished product. For example, a predetermined image signal is input to the liquid crystal device as display data, and projected, displayed, etc., to check whether the data is correctly displayed or whether there is a defective pixel.
However, when a method for inspecting a finished product is employed, a defective product is found after the substrate manufacturing process. For this reason, there is a disadvantage that discovery of defective products is delayed, which is not preferable from the viewpoint of management of the manufacturing process.

For example, the time until failure discovery information is fed back to process management becomes longer. As a result, the yield reduction period becomes longer and the manufacturing cost increases. Also, in the case of a prototype, since the period from the evaluation of the prototype to the feedback to the design is prolonged, the development period is prolonged and the development cost is increased. Furthermore, after the product is completed, so-called repair, that is, repair of a defective portion is difficult.
Therefore, it is desired to find a defect, particularly a defective pixel of a display device, in the manufacturing process of the substrate.

  As one of such inspection methods, there has been proposed a technique for inspecting a liquid crystal display device by bringing a test probe into contact with an electrode pad of the liquid crystal display device and supplying a predetermined current (for example, a patent). Reference 1). Similarly, a technique has been proposed in which a predetermined voltage is applied to each pixel of the TFT substrate from the capacitor capacity characteristics of the pixel, and the function of the TFT is inspected based on the waveforms of the discharge current and the discharge voltage (for example, Patent Documents). 2).

In addition, a technique for inspecting the operation of each pixel electrode by detecting the amount of change in the potential of the pixel electrode using a counter electrode for inspection corresponding to the pixel electrode of the TFT substrate has been proposed (for example, Patent Documents). 3).
JP-A-5-341302 Japanese Unexamined Patent Publication No. 7-333278 Japanese Patent Laid-Open No. 10-104563

  However, in the case of the techniques described in Patent Document 1 and Patent Document 3 described above, in the inspection apparatus, mechanical positional accuracy is required to bring a predetermined probe or the like into contact with or close to an electrode pad or the like from the outside of the substrate. . As a result, there is a problem that the inspection time becomes long in order to ensure mechanical alignment accuracy. Furthermore, in the case of a high-definition liquid crystal display device, a thin probe or the like must be brought into contact with many electrode pads by performing mechanical control, and these methods may not be applied.

  Also, in general, the capacitance of various capacitance components between the liquid crystal display device and the measuring device, such as source lines, video lines, electrode pad terminals, etc., is much higher than the capacitance of the pixel itself including the additional capacitance of the electrode large. The source potential change ΔV determined by the redistribution of the charge accumulated in the pixel and the charge charged in the source line, and the ratio of the capacitance of the source line etc. to the capacitance of the pixel itself. is there. For this reason, when the voltage held in the pixel is taken out from the electrode pad or the like, a large level of noise is superimposed on the minute level change potential ΔV, and the measurement accuracy of the pixel holding voltage is extremely deteriorated. However, sufficient measurement accuracy cannot be obtained.

  The present invention has been made in view of the above points, and does not require contact with an external probe, etc., realizes an inspection with sufficient measurement accuracy, and reduces the area occupied by the inspection circuit. It is an object to provide a substrate for an electro-optical device, an electro-optical device, and an electronic apparatus.

  The electro-optical device substrate according to the present invention includes a plurality of scanning lines and a plurality of source lines that intersect with each other, and a plurality of scanning lines and a plurality of source lines that are arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines. The pixel electrode has first and second terminals. The potential of the potential signal supplied to the first terminal and the potential signal supplied to the second terminal are compared, and the first When the potential signal supplied to the terminal is low, the potential of the first terminal is made lower. When the potential signal supplied to the first terminal is high, the potential of the first terminal is made higher. And supplying a precharge voltage to the first and second terminals, supplying a reference voltage to one of the first and second terminals, and writing the other to the pixel electrode Supply means for reading out and supplying a potential signal, and said supply A P-channel transistor connected to the first and second terminals, wherein the first and second terminals have the same potential at least at the end of supplying the precharge voltage by the stage. And equalizing means comprising N-channel transistors.

  According to such a configuration, the supply means supplies the precharge voltage to the first and second terminals of the amplifier. At the end of the supply of the precharge voltage, the equalizing means sets the first and second terminals to the same potential. The potential signal read from the pixel electrode is supplied to the amplifier by the supply means. The amplifier compares the potential between the potential signal supplied to the first terminal and the potential signal supplied to the second terminal, and the first signal is supplied when the potential signal supplied to the first terminal is low. When the potential of the terminal is lowered and the potential signal supplied to the first terminal is high, the potential of the first terminal is made higher and output. When the precharge voltage supply is stopped, the potential drops of different pushdown amounts occur at the first and second terminals. Even in this case, before the potential signal from the pixel electrode is supplied to the amplifier, the first and second terminals are set to the same potential by the equalizing means, and the influence of pushdown is avoided. Pushdown also occurs when the equalizing operation by the equalizing means stops. However, the equalizing means is composed of a P-channel transistor and an N-channel transistor, and push-down and push-up occur to suppress potential fluctuations at the first and second terminals of the amplifier. As a result, the amplifier is prevented from malfunctioning, and an accurate comparison result can be obtained.

  The equalizing means is characterized in that a P-channel transistor and an N-channel transistor are connected in parallel.

  According to such a configuration, when the equalizing operation by the equalizing means is stopped, push-down and push-up occur, and potential fluctuations at the first and second terminals of the amplifier are suppressed.

  The electro-optical device substrate according to the present invention includes a plurality of scanning lines and a plurality of source lines that intersect with each other, and a plurality of scanning lines and a plurality of source lines that are arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines. The pixel electrode has first and second terminals, and compares the potential of the first potential signal supplied to the first terminal and the second potential signal supplied to the second terminal. When the first potential signal is low, the potential of the first terminal is lowered, and when the first potential signal is high, the potential of the first terminal is raised and output. An amplifier, supply means for supplying a precharge voltage to the first and second terminals via a precharge power supply line, and a reference wiring connected to the first terminal as a reference voltage to the first terminal Is used to maintain the precharge voltage. And connecting the inspection line connected to the second terminal and the source line, thereby reading out a potential signal written in the pixel electrode and passing through the source line and the inspection line through the first line. The connection means for supplying the second terminal as a potential signal of 2 and the potential of the first and second terminals at the same potential at least at the end of the supply of the precharge voltage by the precharge voltage supply means. And an equalizing means including a P-channel transistor and an N-channel transistor connected to the first and second terminals.

  According to such a configuration, the precharge voltage supply means supplies the precharge voltage to the first and second terminals of the amplifier via the precharge power supply line. The equalizing means sets the first and second terminals to the same potential at the end of supplying the precharge voltage. The precharge voltage is maintained at the second terminal as a reference voltage. The connecting means connects the source line and the inspection wiring to supply the potential signal read from the pixel electrode to the second terminal. The amplifier compares the potentials of the first potential signal supplied to the first terminal and the second potential signal supplied to the second terminal, and the first potential signal is low when the first potential signal is low. When the first potential signal is high, the potential at the first terminal is increased and output. When the precharge voltage supply is stopped, the potential drops of different pushdown amounts occur at the first and second terminals. Even in this case, before the potential signal read from the pixel electrode is supplied to the second terminal, the first and second terminals are made equal to each other by the equalizing means, thereby avoiding the influence of pushdown. . Pushdown also occurs when the equalizing operation by the equalizing means stops. However, the equalizing means is composed of a P-channel transistor and an N-channel transistor, and push-down and push-up occur to suppress potential fluctuations at the first and second terminals of the amplifier. As a result, the amplifier is prevented from malfunctioning, and an accurate comparison result can be obtained.

  Further, the connection means selects one source line of the plurality of source lines and connects it to the inspection wiring.

  According to such a configuration, a plurality of source lines can be associated with one amplifier, and the area occupied by the amplifier can be increased. As a result, the driving capability can be improved, variation can be reduced, and high-accuracy pixel inspection is possible.

  The electro-optical device substrate according to the present invention includes a plurality of scanning lines and a plurality of source lines that intersect with each other, and a plurality of scanning lines and a plurality of source lines that are arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines. The pixel electrode has first and second terminals. The potential of the potential signal supplied to the first terminal and the potential signal supplied to the second terminal are compared, and the first When the potential signal supplied to the terminal is low, the potential of the first terminal is made lower. When the potential signal supplied to the first terminal is high, the potential of the first terminal is made higher. An amplifier for outputting, a supply means for supplying a reference voltage to one of the first and second terminals after applying a precharge voltage to the first and second terminals, and the first and second terminals The inspection wiring connected to the other of the terminals and the source line The connection means for reading out the potential signal written in the pixel electrode and supplying it to the other of the first and second terminals, and at least when the supply of the precharge voltage by the supply means is completed, An equalizing means configured to make the potentials of the first and second terminals equal to each other, and comprising a P-channel transistor and an N-channel transistor connected to the first and second terminals; It is characterized by having.

  According to such a configuration, the precharge voltage supply means supplies the precharge voltage to the first and second terminals of the amplifier via the precharge power supply line. The equalizing means sets the first and second terminals to the same potential at the end of supplying the precharge voltage. A precharge voltage is maintained as a reference voltage at one of the first and second terminals. The connection unit supplies the potential signal read from the pixel electrode to the other of the first and second terminals by connecting the source line and the inspection wiring. The amplifier compares the potential between the potential signal supplied to the first terminal and the potential signal supplied to the second terminal, and the first signal is supplied when the potential signal supplied to the first terminal is low. When the potential of the terminal is lowered and the potential signal supplied to the first terminal is high, the potential of the first terminal is made higher and output. The first and second terminals are set to the same potential by the equalizing means at the time when the potential signal from the pixel electrode is supplied, and the influence of pushdown is avoided. Pushdown also occurs when the equalizing operation by the equalizing means stops. However, the equalizing means is composed of a P-channel transistor and an N-channel transistor, and push-down and push-up occur to suppress potential fluctuations at the first and second terminals of the amplifier. As a result, the amplifier is prevented from malfunctioning, and an accurate comparison result can be obtained.

  Further, the connection means selects one source line of the plurality of source lines and connects it to the inspection wiring.

  According to such a configuration, a plurality of source lines can be associated with one amplifier, and the area occupied by the amplifier can be increased. As a result, the driving capability can be improved, variation can be reduced, and high-accuracy pixel inspection is possible.

  The substrate for an electro-optical device according to the present invention is arranged in a matrix corresponding to a plurality of scanning lines and a plurality of source lines intersecting each other, and corresponding to the intersection of the plurality of scanning lines and the plurality of source lines. A plurality of pixel electrodes; first and second terminals; comparing a potential of a potential signal supplied to the first terminal with a potential signal supplied to the second terminal; When the potential signal supplied to one terminal is low, the potential of the first terminal is made lower, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is set lower. A higher output amplifier and a precharge voltage applied to the first and second terminals, a reference voltage is supplied to one of the first and second terminals, and the other is written to the pixel electrode. Read and supply the embedded potential signal, The precharge voltage supply means constituted by the first P-channel transistor and the first N-channel transistor connected to the first and second terminals and the potentials of the first and second terminals are mutually connected. And an equalizing means comprising a second P-channel transistor and a second N-channel transistor connected to the first and second terminals. And

  The substrate for an electro-optical device according to the present invention is arranged in a matrix corresponding to a plurality of scanning lines and a plurality of source lines intersecting each other, and corresponding to the intersection of the plurality of scanning lines and the plurality of source lines. A plurality of pixel electrodes; first and second terminals; and a potential of a first potential signal supplied to the first terminal and a second potential signal supplied to the second terminal. In comparison, when the first potential signal is low, the potential of the first terminal is made lower, and when the first potential signal is high, the potential of the first terminal is made higher. An output amplifier; and a first P-channel type connected to the first and second terminals for supplying a precharge voltage to the first and second terminals via a precharge power supply line Consists of a transistor and a first N-channel transistor Precharge voltage supply means, and means for maintaining and supplying the precharge voltage using a reference wiring connected to the first terminal as a reference voltage to the first terminal, and to the second terminal By connecting the connected inspection wiring and the source line, the potential signal written to the pixel electrode is read and the second terminal is supplied as the second potential signal through the source line and the inspection wiring. And a second P-channel transistor connected to the first and second terminals, and a second P-channel transistor connected to the first and second terminals. And equalizing means constituted by two N-channel transistors.

  The substrate for an electro-optical device according to the present invention is arranged in a matrix corresponding to a plurality of scanning lines and a plurality of source lines intersecting each other, and corresponding to the intersection of the plurality of scanning lines and the plurality of source lines. A plurality of pixel electrodes; first and second terminals; comparing a potential of a potential signal supplied to the first terminal with a potential signal supplied to the second terminal; When the potential signal supplied to one terminal is low, the potential of the first terminal is made lower, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is set lower. An amplifier that outputs a higher voltage, and a precharge voltage is applied to the first and second terminals, and then a reference voltage is supplied to one of the first and second terminals. And a first P-channel transistor connected to the second terminal The pixel electrode is connected by connecting a precharge voltage supply means configured by a star and a first N-channel transistor, a test line connected to the other of the first and second terminals, and the source line. A connection means for reading out the potential signal written to the other and supplying the other to the other of the first and second terminals, and the potentials of the first and second terminals being the same potential, And an equalizing means including a second P-channel transistor and a second N-channel transistor connected to the first and second terminals.

  According to these configurations, the precharge voltage supply means and the equalizing means are constituted by a P-channel transistor and an N-channel transistor. Thereby, when the operation of the precharge voltage supply means and the equalizing means is stopped, push-down and push-up occur, and potential fluctuations at the first and second terminals of the amplifier are suppressed. As a result, the amplifier is prevented from malfunctioning, and an accurate comparison result can be obtained.

  The electro-optical device according to the present invention is an electro-optical device in which an electro-optical material is sandwiched between a pair of substrates, wherein the electro-optical device substrate is used for one of the pair of substrates.

  Further, an electronic apparatus according to the present invention is characterized by using the electro-optical device.

  According to such a configuration, it is possible to realize an electro-optical device or an electronic apparatus using an electro-optical device substrate that can be inspected with sufficient measurement accuracy without requiring contact with an external probe.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  Here, as an example of the electro-optical device substrate of the present invention, an active matrix display device substrate used in a liquid crystal display device will be described as an example.

  In the present invention, an inspection circuit including a differential amplifier is mounted on a substrate, and a signal potential read from a pixel to be inspected is compared with a reference potential (reference voltage) by using a differential amplifier. Good or bad is judged.

  By the way, depending on how the reference is supplied to the differential amplifier and how the inspection target pixel is selected, three classifications of <pixel reference type>, <external reference type>, and <test column switching external reference type> can be considered. .

  In the pixel reference type, a reference potential is written to one pixel of a pair of pixels, and potentials read from both pixels are compared by a differential amplifier to determine whether the other pixel is good or defective.

  The external reference type applies a reference potential (reference) from the outside, and compares the reference from the outside in the differential amplifier with the potential read from the pixel to be inspected to determine whether the pixel is good or bad. .

  The test column switching external reference type supplies an external reference to one of the two input terminals of the differential amplifier and supplies a potential read from the pixel to the other input terminal. The terminal and the input terminal that supplies the potential read from the pixel are switched to each other.

  Further, these <pixel reference type>, <external reference type>, and <examination column switching external reference type> have a plurality of differential amplifier terminals (inspection terminals) to which potentials read from pixels from the inspection target are applied. It is possible to configure a shared type to which a configuration in which one of the source lines is selected and connected is added.

First Embodiment <External Reference Type>
FIG. 1 is a circuit diagram showing an external reference type electro-optical device substrate according to a first embodiment of the present invention. This embodiment is an example in which a precharge process and an equalization process, which will be described later, are terminated at different timings.

  As an element substrate 1B of the liquid crystal display device of FIG. 1 which is an electro-optical device substrate, a TFT substrate which is an active matrix display device substrate will be described as an example. The element substrate 1 </ b> B includes a display element array unit 2, a precharge / reference circuit unit 13, and a display data read circuit unit 4. The display element array unit 2 serving as a display unit has a plurality of pixels 2a of m rows × n columns arranged two-dimensionally in a matrix. Here, m and n are integers.

  The display element array unit 2 is a matrix of the first column, the second column,..., The nth column from the right in FIG. 1 and the first row, the second row,. In order to simplify the description, an example of a circuit including pixels of a matrix of 4 (rows) × 6 (columns) is shown.

  FIG. 2 is an equivalent circuit diagram of the pixel 2a in FIG. The display element array unit 2 is configured, for example, by sealing liquid crystal between both substrates. The display element array section 2 includes pixels 2a that are unit display elements corresponding to the intersections of the source lines S (S1, S2,...) And the scanning lines G (G1, G2,...). Each pixel 2a has a thin film transistor (hereinafter referred to as TFT) 11 which is a switching element. A pixel signal is supplied from the source line to the pixel electrode through the TFT, and the state of the liquid crystal between the pixel electrode and the common electrode is changed by the pixel signal. Thus, the light transmittance of the display element array unit 2 can be changed by the pixel signal, and image display is possible.

  In order to hold the pixel signal in the pixel for a long time, an additional capacitor Cs is connected in parallel to a pixel electrode, a common electrode, and a capacitor (hereinafter referred to as a liquid crystal capacitor) Clc of each pixel 2a. The drain of the TFT 11 is connected to one end of each of the liquid crystal capacitor Clc and the additional capacitor Cs, and a common fixed potential CsCOM is applied to the other end of the additional capacitor Cs. The gate terminal g of the TFT 11 is connected to the scanning line G. When a predetermined voltage signal is input to the gate terminal g of the TFT 11 and the TFT 11 is turned on, the voltage applied to the source terminal s of the TFT 11 connected to the source line S is applied to the liquid crystal capacitor Clc and the additional capacitor Cs for supply. The predetermined potential is maintained.

  The element substrate 1B includes an X driver unit 5a, a Y driver unit 5b, and a transmission for driving a plurality of pixels 2a arranged in the X direction (horizontal direction) and the Y direction (vertical direction) of the display element array unit 2. A gate portion 6 and a video signal line 7 are included. Data writing and data reading are performed by the X driver unit 5a, the Y driver unit 5b, the transmission gate unit 6 and the video signal line 7.

  The transmission gate unit 6 supplies pixel signals input from the video signal line 7 to the source lines S1, S2,... According to the output timing signal from the X driver unit 5a. The video signal line 7 includes a signal line that supplies a signal to an odd-numbered column of the matrix-shaped display element array unit 2 and a signal line that supplies a signal to an even-numbered column, and is connected to the respective terminals ino and ine. ing. The source lines S1, S2,... Are connected to n pixels in each column, and the pixel signals from the source lines S1, S2,. Although an out terminal and an out terminal are provided as output terminals from the video line, there is no problem even if the input terminals ino and ine are common terminals.

  In the present embodiment, a display data reading circuit unit 4 is formed on an element substrate 1B of an active matrix driving type liquid crystal display panel for pixel inspection. Between the display element array section 2 and the display data reading circuit section 4, a transmission gate section 9 'is provided as a connecting means.

  The display data reading circuit unit 4 includes a plurality of differential amplifiers 4a, and the potential read from the pixel to be inspected and the reference potential serving as a reference for inspection at two input terminals se and so of the differential amplifier 4a. (Reference) is given.

  FIG. 3 is a circuit diagram showing a specific configuration of the differential amplifier 4a of the display data reading circuit unit 4 in FIG.

  Each differential amplifier 4a includes two P-channel transistors Tr1 and Tr2, and two N-channel transistors Tr3 and Tr4. The gates of the transistors Tr1 and Tr3 are connected to the terminal so, and the gates of the transistors Tr2 and Tr4 are connected to the terminal se. The source / drain paths of the transistors Tr1 and Tr2 are connected in series, and the source / drain paths of the transistors Tr3 and Tr4 are also connected in series. A source / drain path between the transistors Tr1 and Tr2 and a source / drain path between the transistors Tr3 and Tr4 are connected in parallel between the terminals so and se.

  The terminals se and so are respectively connected to the se wiring 4f or the so wiring 4g that supplies a potential to these terminals. One of the se wiring 4f and the so wiring 4g is supplied with a signal potential read from the pixel to be inspected, and the other is supplied with a reference. The connection point between the source and drain of the transistors Tr1 and Tr2 is connected to the power supply terminal sp, and the connection point between the source and drain of the transistors Tr3 and Tr4 is connected to the power supply terminal sn. As shown in FIG. 1, a power supply voltage Vdd is supplied to the power supply terminal sp via the power supply transistor 4d, and a ground potential is supplied to the power supply terminal sn from the reference potential point via the power supply transistor 4e. The power supply transistors 4d and 4e are controlled to be turned on and off by drive pulses SAp-ch and SAn-ch supplied via terminals 4b and 4c, respectively.

  In the differential amplifier 4a configured as described above, one of the potentials supplied to the terminals se and so is raised to the power supply potential, and the other is lowered to the potential of the reference potential point (ground potential). For example, it is assumed that a slightly higher potential is supplied to the terminal se than the terminal so. Then, the transistor Tr4 is turned on first among the transistors Tr1 to Tr4. Since the transistor Tr4 is turned on, the potential of the terminal so drops to the low ground potential of the terminal sn. Then, since the terminal so falls to the low ground potential of the terminal sn, the transistor Tr1 whose gate end is connected to the terminal so is turned on. As a result, the terminal se rises to the high power supply voltage Vdd of the power supply terminal sp.

  As described above, the differential amplifier 4a functions to increase the higher potential among the potentials applied to the terminals se and so, and lower the lower potential.

  The transmission gate portion 9 'is constituted by transistors 9a provided corresponding to the source lines S1, S2,. The so wiring 4g connected to the terminal so of the differential amplifier 4a is connected to the source of the transistor 9a, and the drain of the transistor 9a is connected to each source line S1, S2,. The gate of the transistor 9a is connected to the control terminal 9b. The transistor 9a is turned on by a HIGH connection control signal input via the control terminal 9b, and a test circuit is connected to the source lines S1, S2,.

  The control terminal 9b is connected to a pull-down circuit composed of a transistor 9d, and is normally kept LOW. As a result, normally, the transistor 9a is off, and the display data read circuit section 4 is disconnected from each source line. At the time of the test, by supplying a HIGH connection control signal to the connection control terminal 9b, the transistor 9a is turned on, and the display data reading circuit unit 4 is connected to the source line.

  Between the display element array unit 2 and the display data read circuit unit 4, a precharge and reference circuit unit 13 and an equalize circuit unit 8 are also provided as supply means. The precharge and reference circuit unit 13 has two transistors 3co and 3ce corresponding to each differential amplifier 4a. The transistor 3co has a source connected to the voltage application terminal 3a and a drain connected to the terminal so of the differential amplifier 4a via the so wiring 4g. The source of the transistor 3ce is connected to the voltage application terminal 3a, and the drain is connected to the terminal se of the differential amplifier 4a via the se wiring 4f. A precharge voltage is supplied to the voltage application terminal 3a.

  The HIGH precharge control signal is applied to the gates of the transistors 3co and 3ce via the control terminal 3b, whereby the transistors 3co and 3ce are turned on, and the precharge voltage supplied to the voltage application terminal 3a is applied to the se wiring 4f. Alternatively, it is supplied to the so wiring 4g.

  That is, the se wiring 4f connected to the terminal se of the differential amplifier 4a is used as a reference wiring for maintaining the precharge voltage from the outside as a reference voltage and supplying it to the terminal se. On the other hand, the so wiring 4g is connected to each source line S by the transistor 9a, and is used as an inspection wiring for supplying data from the pixel to be inspected to the terminal so.

  That is, in this embodiment, the inspection wiring connected to one terminal of the differential amplifier 4a and the source line are connected, and the pixel connected to one source line S by one differential amplifier 4a is connected. Inspection is possible. The number of differential amplifiers 4a is the same as the number n of columns of the display element array unit 2.

  In the precharge period, a precharge voltage is supplied to the so wiring 4g and the se wiring 4f. The precharge process is for applying a precharge voltage to the source line S and the so and se wirings 4g and 4f in order to inspect various characteristics. Various voltages can be selected as the precharge voltage. For example, the power supply voltage Vdd, the ground potential, or an intermediate potential thereof may be used. In the example of FIG. 1, the precharge voltage is set to an intermediate potential, for example.

  The equalize circuit unit 8 has a gate circuit 8a in which a source and a drain are respectively connected to a so wiring 4g. The gate circuit 8a is configured by connecting an N-channel transistor and a P-channel transistor in parallel. The equalization control signal EQ is supplied from the output terminal o1 of the control unit 20 or 21 to the gate of the N-channel transistor constituting the gate circuit 8a. Further, an inverted signal of the equalize control signal EQ is given to the gate of the P channel transistor constituting the gate circuit 8a from the output terminal o2 of the control unit 20 or 21.

  The control unit 20 or 21 receives the equalization control signal EQ from the control terminal 8b at the input terminal in. The control unit 20 or 21 outputs the input equalization control signal EQ as it is from the output terminal o1, and also inverts the input equalization control signal EQ and outputs an inverted signal from the output terminal o2.

  6 and 7 are circuit diagrams each showing a specific configuration of the control unit 20 or 21 that can be employed in FIG.

  In FIG. 6, the input terminal in is directly connected to the output terminal o1. As a result, the equalization control signal EQ supplied to the input terminal in is output as it is from the output terminal o1. The equalize control signal EQ supplied to the input terminal in is also supplied to the inverter 20a. The inverter 20a inverts the input equalization control signal EQ and outputs it from the output terminal o2.

  The control unit 20 in FIG. 6 can output a positive phase output and an inverted output of the equalize control signal EQ. However, the inverted output is slightly delayed compared to the positive phase output. On the other hand, the control unit 21 of FIG. 7 constitutes a phase compensation circuit that compensates for this delay.

  In FIG. 7, the input terminal in is connected to the output terminal o1 via inverters 21a and 21b connected in series. The output of the inverter 21a is also given to the inverter 21c, and the output of the inverter 21c is given to the inverter 21d and the inverter 21a. The output of the inverter 21d is given to the output terminal o2.

  As a result, the equalization control signal EQ supplied to the input terminal in is output as it is from the output terminal o1. The equalize control signal EQ supplied to the input terminal in is also supplied to the inverter 20a. The inverter 20a inverts the input equalization control signal EQ and outputs it from the output terminal o2. The inverters 21a to 21d constitute a flip-flop, the inverter 21b outputs an output in phase with the equalize control signal EQ to the output terminal o1, and the inverter 21d outputs an output opposite in phase to the equalize control signal EQ to the output terminal o2. Is done. There is no delay between the equalization control signal EQ output from the output terminals o1 and o2 and its inverted signal.

  The gate circuit 8a is supplied with the equalization control signal and its inverted signal from the control units 20 and 21. The gate circuit 8a is turned on when a HIGH equalize control signal is supplied from the control units 20 and 21 to the gate of the N-channel transistor and a LOW equalize control signal is supplied to the gate of the P-channel transistor. 4g and se wiring 4f are set to the same potential.

  When the element substrate of the liquid crystal display device, which is an active matrix display device having the above-described configuration, is manufactured in the manufacturing process, the electrical characteristics of the element substrate itself before the liquid crystal is sealed by being bonded to the counter substrate are evaluated or inspected. can do. In addition, as a defect to be inspected for electrical characteristics, a defect in which a pixel is fixed to LOW due to leakage of a data holding capacitor (additional capacitor Cs) of each pixel of the element substrate (hereinafter referred to as a LOW fixing defect), There is a defect that the pixel is fixed to HIGH due to leakage between the source and drain of the TFT as a switching element (hereinafter referred to as HIGH fixing defect).

  Next, inspection and operation of the substrate configured as described above will be described.

  Before explaining the method of inspecting the element substrate 1B in the manufacturing process, the liquid crystal display device in which the TFT substrate shown in FIG. 1 is bonded to the counter substrate and liquid crystal is sealed is used to perform normal image display. The operation will be described.

  First, pixel signals that are odd-numbered and even-numbered pixel signals are respectively input to the two video signal lines 7 to the input terminals ine and ino of the video signal line 7. Each pixel signal is supplied to each source line S via each transistor TG1, TG2,... Of the transmission gate unit 6 in accordance with a column selection signal from the X driver 5a.

  The pixel signal supplied to each source line S is written to each pixel 2a in the selected row when the scanning line G from the Y driver 5b is HIGH. That is, in the selected scanning line G, the pixel signal supplied to the source line S is supplied and held as a display pixel signal to the corresponding pixel 2a. By performing this operation in row order, a desired image is displayed on the display element array unit 2 of the liquid crystal display device.

  The precharge and reference circuit unit 13 applies a precharge voltage Vpre to each source line S before the scanning line G becomes HIGH. The precharge voltage Vpre is supplied to the voltage application terminal 3 a of the precharge and reference circuit unit 13. The timing for supplying the precharge voltage Vpre is determined by a precharge control signal PCG given to the control terminal 3b.

  When an image is displayed as a liquid crystal display device as a product or a prototype, the transistor 9a of the transmission gate portion 9 ′ is off, and the display data reading circuit portion 4 of the element substrate 1B does not operate and is not used. .

  Next, in the element substrate 1B, referring to FIG. 4, FIG. 5, and FIG. 8 to FIG. 10 for the inspection procedure performed in the state of the element substrate 1B after the circuit portion shown in FIG. To explain. In the inspection of the element substrate 1B, the display data reading circuit unit 4 operates and is used.

  First, an inspection system for realizing the inspection method will be described. FIG. 4 is a configuration diagram of the inspection system. The element substrate 1 </ b> B and a test apparatus 15 that can write and read pixel data are connected via a connection cable 16. The connection cable 16 tests the terminals ino and ine of the video signal line 7 of the element substrate 1B, the terminals 4b and 4c of the signal line of the display data reading circuit unit 4, the terminals 3a and 3b of the precharge and reference circuit unit 13, etc. Electrically connected to the device 15.

  The electrical characteristics of the element substrate 1B can be inspected by supplying a predetermined voltage to each terminal in a predetermined order described later from the test apparatus 15. In the following, a procedure for inspecting whether or not there is a LOW fixing defect among the above-described defects will be described as the contents of the inspection.

  FIG. 5 is a flowchart showing an example of the entire flow of inspection. FIG. 8 is a timing chart for explaining the read operation in step ST2 of FIG. In FIG. 8, the operation when the pixel is defective is indicated by a broken line.

  In step ST1 of FIG. 5, a predetermined pixel signal is input from the input terminals ino and ine of the video signal line 7 to each pixel which is a cell. The pixel inspection is performed by determining whether or not the pixel in the inspection target column is normal with respect to the pixel in the reference column. Each timing signal shown in FIG. 8 is generated by the test apparatus 15 and supplied to each terminal.

  In the present embodiment, the reference is supplied from the outside and does not need to be written in the pixel. Each pixel is written for inspection. For example, when an inspection for a LOW fixing defect is performed, all the scanning lines G of the element array unit 2 are turned on, and HIGH is written in all the pixels.

  In addition, when LOW is written in each pixel, it is possible to inspect a HIGH fixing defect. Hereinafter, an example will be described in which HIGH is written in all pixels and the substrate 1B is inspected, but only some pixels may be inspected. After writing, the gate of the scanning line G is turned off.

  At this time, the drive wiring SAp-ch is at the power supply potential Vdd, the drive wiring SAn-ch is at the ground potential, and the differential amplifiers 4a of the display data reading circuit unit 4 are not operating.

  Next, in step ST2, pixel data is read out. By supplying a high connection control signal TE to the connection control terminal 9b, each transistor 9a of the transmission gate portion 9 'is turned on. Thereby, the transistor 9a is turned on, and the source lines S1, S2,... Are connected to the respective so wirings 4g. Thus, the written pixel data is read for each row and supplied to the display data reading circuit unit 4.

  Immediately before reading in step ST2, precharge processing and equalization processing are performed. That is, after the above-described predetermined pixel data is written to all the pixels, first, the precharge control signal PCG (see FIG. 8) supplied to the control terminal 3b of the precharge and reference circuit unit 13 becomes HIGH.

  In order to secure the data holding time t1, the precharge control signal PCG supplied to the terminal 3a of the precharge circuit unit 13 is HIGH for the period t1.

  Thereby, the precharge voltage supplied to the voltage application terminal 3a is applied to the so wiring 4g and the source lines S and se wiring 4f via the transistors 3co and 3ce, respectively. In the se wiring, when the differential amplifier 4a operates, this precharge voltage functions as a reference voltage. For example, an intermediate potential is selected as the precharge voltage Vpre.

  In the present embodiment, as shown in FIG. 8, the equalization control signal EQ for controlling the equalization process is obtained by delaying the precharge control signal PCG for controlling the precharge process. It starts with a slight delay in processing.

  That is, as shown in FIG. 8, after the precharge process is started, the equalization control signal changes from LOW to HIGH, the gate circuit 8a of the equalization circuit unit 8 is also turned on, and the so wiring 4g and se wiring 4f. And have the same potential. Thereby, at this time, the source lines S and the terminals so and se of the differential amplifier 4a are in an intermediate potential state. Note that the start timing of the precharge process may coincide with the start timing of the precharge process.

  Note that the precharge potential (voltage applied to the voltage application terminal 3a) Vpre of each source line S is set to an intermediate potential between HIGH and LOW, and the CsCOM potential shown in FIG. 2 is set to the LOW potential. The reason why the CsCOM potential is set to the LOW potential is that when the data holding capacitor Cs has a leak failure, the CsCOM potential at the leak destination is the Low potential, so that the read potential is lower than the intermediate potential on the reference side. is there. Then, a slightly long time is set for the first precharge period so that a voltage change due to a leak failure appears.

  Next, immediately before reading out the pixel data, the precharge process and the equalize process are stopped. That is, first, the precharge control signal PCG is set to LOW. As a result, the transistors 3co and 3ce are turned off.

  By the way, since the transistors 3co and 3ce have a parasitic capacitance, the gates of the transistors 3co and 3ce change from HIGH to LOW, and push-down occurs at the terminals so and se. In particular, when thin film transistors are employed as the transistors 3co and 3ce, the influence of pushdown is large.

  At the time of pixel inspection, the transistor 9a is on, and the so wiring 4g and the source line S are connected to the terminal so of the differential amplifier 4a. On the other hand, only the se wiring 4f is connected to the terminal se of the differential amplifier 4a. The wiring capacity of the so wiring 4g and the source line S is sufficiently larger than the wiring capacity of only the se wiring 4f. For this reason, the push-down (potential drop) generated at the terminal so is relatively small, whereas the terminal se has a relatively large push-down. That is, there is a possibility that the differential amplifier 4a malfunctions due to the difference in capacitance between the wirings connected to the terminals so and se of the differential amplifier 4a, and an error occurs in the determination of whether the pixel is good or bad.

  Therefore, in the present embodiment, at the end of the precharge process, the equalize process is continued, and the gate circuit 8a for the equalize process is configured by a parallel connection body of a P-channel transistor and an N-channel transistor. Thus, the effect of pushdown is avoided.

  FIG. 9 is a waveform diagram showing how potential fluctuations due to pushdown are eliminated. FIG. 9 shows a waveform when the control unit 20 shown in FIG. 6 is adopted as the control unit of FIG.

  FIG. 9 shows the precharge control signal PCG, the equalize control signal EQ, the scanning signal supplied to the scanning line G1, the potential of the terminal so, and the potential of the terminal se.

  As described above, before supplying the signal potential from the pixel to the terminal so of the differential amplifier 4a, the precharge voltage is supplied to the so wiring 4g as the inspection wiring, the se wiring 4f as the reference wiring, and the source line S. At the same time, the terminals se and so are surely set to the same potential. For this precharge and equalization processing, a HIGH precharge control signal PCG is applied to the gates of the transistors 3ce and 3co, and a HIGH equalize control signal EQ is applied to the gate of the gate circuit 8a (see FIG. 9).

  Immediately before supplying the signal potential from the pixel to the terminal so of the differential amplifier 4a, the precharge control signal PCG is first switched from HIGH to LOW in order to stop the precharge and equalization processing (see FIG. 9). With this switching from HIGH to LOW, push-down (potential drop due to field through) occurs at the terminals so and se due to the parasitic capacitances of the transistors 3co, 3ce, and 8a.

  At the time of pixel inspection, the transistor 9a is on, and the so wiring 4g and the source line S are connected to the terminal so of the differential amplifier 4a. On the other hand, only the se wiring 4f is connected to the terminal se of the differential amplifier 4a. The wiring capacity of the so wiring 4g and the source line S is sufficiently larger than the wiring capacity of only the se wiring 4f. Therefore, as shown by the potential of the terminal so in FIG. 9 (thin line), the push-down generated at the terminal so is relatively small at the timing when the precharge control signal PCG is switched from HIGH to LOW, whereas the push-down at the terminal se is relatively small. Causes a relatively large pushdown (the potential at the terminal se in FIG. 9).

  However, the equalization control signal EQ is a delayed version of the precharge control signal PCG, and the equalization process is continued even when the precharge process ends. That is, the gate circuit 8a controls the terminals se and so to have the same potential. In this case, the potential of the terminal so is hardly changed by the so wiring 4g and the source line S connected to the terminal so. Accordingly, the decrease in the potential of the terminal se caused by the push-down at the end of the precharge rises to the relatively stable potential of the terminal so, and eventually the potentials of the terminals so and se become the same potential (see FIG. 9). ).

  After the precharge control signal PCG changes from HIGH to LOW, the equalization control signal EQ supplied to the control terminal 8b also changes from HIGH to LOW. As a result, the gate circuit 8a is turned off and the equalization process is also stopped. Push-down occurs when the gate circuit 8a is turned off.

  However, since the transistors 3co and 3ce need to have sufficient driving capability for precharging the so wiring 4g and the source line S, they have a large occupied area, a large gate width, and a large gate capacitance. On the other hand, the gate circuit 8a does not require a large driving capability and has a small occupied area, so the gate capacitance is small. Therefore, the push-down amount when the transistors 3co and 3ce are off is large, while the push-down amount when the gate circuit 8a is off is sufficiently small. That is, the pushdown amount at the end of the equalization process is small.

  Further, in the present embodiment, the gate circuit 8a is configured by connecting a P-channel transistor and an N-channel transistor in parallel, so that the pushed-down potential is pushed up to return to the original potential. That is, when the N-channel transistor to which the positive phase output of the equalize control signal EQ is supplied first is turned on, push-down occurs, but immediately, the inverted signal of the equalize control signal EQ is supplied to the P-channel transistor. Thus, the reference is restored to the original potential by the push-up of the P-channel transistor.

  FIG. 10 shows waveforms when the control unit 21 shown in FIG. 7 is adopted as the control unit of FIG.

  In this case, as described above, the positive-phase output and the inverted output of the equalization control signal EQ are respectively supplied to the P-channel transistor and the N-channel transistor of the gate circuit 8a at the same timing. Therefore, push-down by the N-channel transistor and push-up by the P-channel transistor occur at the same time, and the reference potential does not fluctuate (bold line at terminal so in FIG. 10).

  Next, after elapse of the data holding time t1, the scanning line G1 is set to HIGH, and reading of pixel data is started. At this time, the drive wiring SAp-ch is at the power supply potential Vdd, the drive wiring SAn-ch is at the ground potential, and each differential amplifier 4a is not yet operated.

  When the scanning line G1 is set to HIGH, data is output simultaneously from the pixels connected to the scanning line G1. That is, the charges written and held in the capacitor Cs move to the corresponding source line S all at once.

  When HIGH is supplied to the scanning line G1 and the pixel signal is transferred to the terminal so, the potential of the terminal so changes in accordance with the potential written to the pixel. When HIGH is written to the pixel, the potential of the terminal so increases slightly, and when LOW is written to the pixel, the potential of the terminal so decreases slightly.

  The differential amplifier 4a compares the potentials of the terminals so and se. In this case, as shown in FIG. 9 or FIG. 10, the influence of pushdown is extremely small, the potential of the terminal se is substantially equal to the potential of the terminal so, and the reference potential of the terminal se where the precharge potential is maintained is This is a potential between the potential of the terminal so when LOW is written to the pixel and the potential of the terminal so when HIGH is written to the pixel. Accordingly, in the differential amplifier 4a, the potential of the terminal so becomes the power supply voltage Vdd or the ground potential according to the signal level written to the pixel.

  In this way, when HIGH is written in each pixel, as shown by the solid line in FIG. 8, if the pixel is normal, the potentials of the source line S and the so wiring 4g slightly increase. If the data of each pixel changes to LOW due to leakage of the capacitor Cs or the like, the potential of each source line S slightly decreases as shown by the broken line. On the other hand, the potential of the terminal se to which the reference is supplied remains the intermediate potential (see FIG. 8). Note that the potential drop of the terminals so and se due to pushdown is sufficiently small, and is not shown in FIG.

  In order to operate each differential amplifier 4a after a predetermined time has elapsed after opening the gate line G1, first, the potential of the drive wiring SAn-ch is changed from LOW to HIGH. The connection control signal TE is set to LOW at the same time as or before and after the moment when the potential of the drive wiring SAn-ch changes to HIGH, and the transistor 9a of the transmission gate portion 9 ′ is turned off for a predetermined period t2. That is, the transistors 9a, 8a, 3co, and 3ce are turned off, and the so wiring 4g and the se wiring 4f are in a floating state. As a result, the intermediate potential of the se wiring 4f and the slightly increased potential of the so wiring 4g are maintained in the wirings so and se, respectively, and are not affected by other wiring such as the source line S.

  In this state, the drive wiring SAn-ch is changed from LOW to HIGH, and the drive wiring Ap-ch is changed from HIGH to LOW. When the drive wiring SAn-ch becomes HIGH, the ground potential is applied to the power supply terminal sn of the differential amplifier 4a, and the terminal se which is the lower potential among the terminals se and so falls to the ground potential (FIG. (See 8 se). Further, since the drive wiring SAp-ch becomes LOW, the power supply voltage Vdd is applied to the power supply terminal sp of the differential amplifier 4a, and the terminal so, which has a higher potential among the terminals se and so, rises to the power supply potential. (See so in FIG. 8). Thus, the potentials of the terminals se and so are determined. This operation is performed simultaneously for all the pixels connected to the scanning line G1.

  As described above, each differential amplifier 4a of the display data reading circuit unit 4 makes the two potential levels appearing at the two terminals so and se change to the voltage of the power supply terminal sp or sn to clarify. Thus, the potentials of the terminals so and se of the differential amplifier 4a are determined to be LOW or HIGH.

  Here, it is assumed that, for example, a leak of the data holding capacitor Cs occurs in the odd-numbered pixel to be inspected, and a LOW fixing defect occurs. In this case, it is assumed that the potential of the source line S is slightly lower than the reference (intermediate potential) as indicated by the broken line S in FIG. Thereby, when the drive wiring SAn-ch becomes HIGH and the power supply terminal sn becomes the ground potential, the terminal so of the differential amplifier 4a is lowered to the ground potential (see the broken line of the terminal so in FIG. 8). When the drive wiring SAp-ch becomes LOW and the power supply terminal sp becomes the power supply voltage Vdd, the terminal se of the differential amplifier 4a rises to the power supply voltage Vdd (see the broken line of the terminal se in FIG. 8).

  That is, in this case, the potentials of the terminals so and se have a logical value opposite to that when the pixel is normal.

  In step ST3, the determined potentials of the terminals se and so are compared. That is, when the potentials of the terminals so and se are determined to be LOW or HIGH, in order to output the potential of the terminal so, the connection control signal TE is set to HIGH to turn on the transistor 9a of the transmission gate unit 9 '.

  The determined logical data of the terminal so of the differential amplifier 4a is supplied to the corresponding source line S from the so wiring 4g. The gates TG1 to TGn of the transistors of the transmission gate unit 6 are opened in order (set to HIGH), and the pixel data of each pixel in the first row is read in order from the video signal line 7 and output to the output terminals outo and oute.

  When the data of all the pixels connected to the gate line G1 is read, the differential amplifier 4a is operated by setting the gate line G1 to LOW, the drive wiring SAn-ch to the ground potential, and the drive wiring SAp-ch to the power supply potential. Stop. Next, as shown in FIG. 8, the precharge control signal PCG is set to HIGH, and then the equalize control signal EQ is set to HIGH, so that all the source lines S are precharged and equalized. The precharge time after the second time does not need to be as long as the first time. After the precharge operation is stopped, the potential of the second scanning line G2 is set to HIGH to turn on the TFT 11 of each pixel in the second row. Thereafter, the same operation is repeated up to the pixels connected to the last scanning line Gm (each pixel in the m-th row) to read out all pixel data.

  The determined potentials of the terminals se and so are output from the output terminals outu and oute to the test apparatus 15. The test device 15 compares the pixel data read in the reading process with the pixel data written in the writing process. When the pixel is normal, a HIGH output is obtained as indicated by the solid lines of outo and out in FIG. When a LOW fixing defect occurs in a pixel, a LOW output is obtained as shown by the broken lines of outo and oute in FIG. Thus, the test apparatus 15 can detect whether or not a LOW fixing defect has occurred in the pixel to be inspected.

  The test device 15 identifies a cell (pixel) whose data read from the pixel to be inspected is not HIGH, and outputs, as an abnormal cell, for example, data such as a cell number to be displayed on a monitor screen (not shown) ( Step ST4).

  In this way, each differential amplifier 4a compares the reference potential, which is an intermediate potential applied from the outside, with the potential of each source line S, and determines a pixel defect based on the comparison result.

  It is obvious that the HIGH fixed defect can be inspected by setting the reference to an intermediate potential and writing LOW to the inspection target pixel.

  As described above, since the defect of the element substrate can be detected after the element substrate process in the product or the prototype is completed, the yield reduction period can be shortened, and it is not rare to assemble defective products, thereby reducing the cost. be able to. In particular, in the case of a prototype, it can be expected to shorten the development period and the development cost. Furthermore, since defects can be detected at the stage of the element substrate, so-called repair is facilitated.

  Further, in the present embodiment, the equalizing process is continued even at the end of the precharge process, and the gate circuit 8a constituting the equalizing circuit unit 8 is configured by a P-channel transistor and an N-channel transistor, so that the terminal The potential fluctuations of se and so are suppressed, no malfunction occurs in the differential amplifier 4a, and highly accurate pixel inspection is possible.

Second Embodiment <External Reference, Shared Type>
FIG. 11 is a circuit diagram showing a shared type electro-optical device substrate belonging to the external reference type. Also in the present embodiment, an example in which the precharge process and the equalize process are ended at different timings is shown.

  In FIG. 11, the same components as those in FIG. In FIG. 11, for simplification of the drawing, the X driver unit 5a, the Y driver unit 5b, the video signal line 7 and the like for driving the display element array unit 2 are not shown. The element substrate 11B of FIG. 11 enables inspection of pixels connected to four source lines with one differential amplifier 4a. That is, one differential amplifier 4a can be formed at intervals of four source lines, and the area of the differential amplifier 4a can be widened to improve the driving capability and reduce the variation of the differential amplifier 4a. Thus, it is possible to improve the inspection accuracy.

  The substrate 11B of FIG. 11 has the configuration of the display element array unit 2, the X driver unit 5a, the Y driver unit 5b, the transmission gate unit 6, the video signal line 7, the differential amplifier 10, and the display data reading circuit unit 4 shown in FIG. The same as the substrate 1B. The configurations of the equalize circuit unit 8 and the precharge / reference circuit unit 13 provided between the display data reading circuit unit 4 and the display element array unit 2 are the same as those of the substrate 1B in FIG.

  This embodiment is different from the first embodiment in that a transmission gate portion 22 is used instead of the transmission gate portion 9 '. The transmission gate portion 22 selectively connects the so wiring 4g to one of the four source lines. That is, in the example of FIG. 11, the differential amplifier 4a is provided for each of the four source lines, and the so wiring 4g connected to the terminal so of each differential amplifier 4a is connected to the first through the transistors 23a to 23d. The (4u + 1) (u = 0, 1, 2,...) Column to the (4u + 4) th column source lines are connected.

  Transistors 23a-23d have their gates connected to TE gate decode circuit 25 via transfer gates 24a-24d, respectively. The transfer gates 24a to 24d are configured by complementary connection of n-channel transistors and p-channel transistors, and outputs TE1 to TE4 of the TE gate decode circuit 25 are supplied to the input terminals, respectively. In the transfer gates 24a to 24d, the control signal from the terminal 27 is input to the gate of the n-channel transistor. The inverter 26 inverts the output of the terminal 27 and supplies it to the gates of the p-channel transistors of the transfer gates 24a to 24d.

  Due to the pull-down circuit connected to the terminal 27, the terminal 27 is LOW during non-test, the output of the inverter 26 is HIGH, and the transfer gates 24a to 24d are off. During the test, a HIGH control signal is applied to the terminal 27, and the transfer gates 24a to 24d are turned on.

  When the HIGH control signal is input to the terminal 27, the transfer gate 24a applies the connection control signal TE1 from the TE gate decode circuit 25 to the gate of the transistor 23a. Similarly, when the HIGH control signal is input to the terminal 27, the transfer gates 24b to 24d supply the connection control signals TE2 to TE4 from the TE gate decode circuit 25 to the gates of the transistors 23b to 23d, respectively.

  The TE gate decode circuit 25 determines which of the four source lines S is connected to each so wiring 4g of the differential amplifier 4a based on the data A0 and A1 input to the terminals 28 and 29. Connection control signals TE1 to TE4 are output. The transistors 23a to 23d to which the LOW connection control signals TE1 to TE4 are applied to the gates are turned off, and the connection between the so wiring and the source line is disconnected. Conversely, the transistors 23a to 23d to which the high connection control signals TE1 to TE4 are applied to the gates are turned on to connect the so wiring and the source line.

  Also in this embodiment, the equalization control signal EQ from the control units 20 and 21 and its inverted signal are supplied to the gate circuit 8a of the equalize circuit unit 8.

  In the embodiment configured as described above, when the HIGH connection control signal TE1 is output from the TE gate decode circuit 25, the transistor 23a is turned on, and the source line of the (4u + 1) th column is connected to the so wiring 4g. Is done. In this way, the quality of the pixels connected to the source lines S1, S5,...

  Similarly, when the high connection control signals TE2 to TE4 are output from the TE gate decode circuit 25, the corresponding transistors 23b to 23d are turned on, and 1 of the source lines of the (4u + 2) th column to the (4u + 4) th column. One is connected to the so wiring 4g. As a result, whether the pixel corresponding to the connected source line is good or bad is inspected.

  As for the connection control signals TE1 to TE4, only one connection control signal corresponding to the column to be inspected is switched to HIGH according to the inspection flow, and the other three connection control signals are kept LOW. The switching of LOW and HIGH of one connection control signal corresponding to the column to be inspected is the same as, for example, the connection control signal TE of FIG.

  At the end of the precharge process, the equalizing process is continued, and the gate circuit 8a of the equalizing circuit unit 8 causes the terminals so and se to push down and push up, so that the terminals so and se The push-down amount is a sufficiently small value substantially equal to each other, and the reference of the terminal se after the push-down does not become higher than the potential of the terminal so at the time of LOW writing, and the determination result of the differential amplifier 4a is incorrect. It can be prevented from occurring.

  Other operations and effects are the same as those of the embodiment of FIG.

(Third embodiment) <Examination column switching external reference type>
FIG. 12 is a circuit diagram showing an inspection column switching external reference type electro-optical device substrate according to a third embodiment of the present invention. Also in the present embodiment, an example in which the precharge process and the equalize process are ended at different timings is shown. In FIG. 12, the same components as those of FIG. In the present embodiment, it is possible to inspect pixels connected to two source lines with one differential amplifier 4a.

  In FIG. 12, the substrate 1C shows the display element array section 2 with 4 rows × 6 columns of pixels, but the display element array section 2, X driver section 5a, Y driver section 5b, transmission gate section 6, video signal The configurations of the line 7, the differential amplifier 10, and the display data reading circuit unit 4 are the same as those in the first embodiment. Between the display data read circuit unit 4 and the display element array unit 2, an equalize circuit unit 8, a precharge and reference circuit unit 13, and a transmission gate unit 19 are provided. The precharge / reference circuit unit 13, the equalize circuit unit 8, and the display data read circuit unit 4 constitute a test circuit.

  In the first embodiment, the pixel signal read from the pixel is applied to the terminal so of the differential amplifier 4a using the so wiring 4g as the inspection wiring, the se wiring 4f as the reference wiring, and the precharge potential from the outside as the reference potential. This was maintained and applied to the terminal se of the differential amplifier 4a.

  On the other hand, in the present embodiment, the inspection wiring and the reference wiring can be switched to each other, and inspection of pixels connected to two columns of the odd number column and the even number column can be performed by one differential amplifier 4a. Is. This switching is performed by the transmission gate unit 19.

  The transmission gate unit 19 includes n / 2 transistors 9ao provided corresponding to the odd-numbered source lines S1, S3,... And n / provided corresponding to the even-numbered source lines S2, S4,. It has two transistors 9ae. The so wiring 4g connected to the terminal so of the differential amplifier 4a is connected to the odd-numbered source lines S1, S3,... Via the source / drain paths of the transistor 9ao. Further, the se wiring 4f connected to the terminal se of the differential amplifier 4a is connected to the source lines S2, S4,... Of the even columns through the source / drain paths of the transistor 9ae.

  The gates of the transistors 9ao and 9ae are connected to the TE gate decoding circuit 9d via transfer gates 9bo and 9be, respectively. In the transfer gates 9bo and 9be, a test circuit connection control signal from the terminal 9f is given to the gate via the inverter 9e. By the pull-down circuit connected to the terminal 9f, the terminal 9f is LOW at the time of non-test, the output of the inverter 9e is HIGH, and the transfer gates 9bo and 9be are off. During the test, a HIGH test circuit connection control signal is applied to the terminal 9f, and the transfer gates 9bo and 9be are turned on.

  The TE gate decode circuit 9d outputs selection signals TEo and TEe for determining the inspection wiring. When the transfer gates 9bo and 9be are turned on, the selection signals TEo and TEe from the TE gate decode circuit 9d are supplied to the gates of the transistors 9ao and 9ae. One of the selection signals TEo and TEe is always HIGH, and the other is always LOW. The TE gate decode circuit 9d sets the selection signal TEe to LOW and switches the selection signal TEo to HIGH when testing odd-numbered columns of pixels. According to the inspection flow, the test circuit connection control signal 9f is switched to HIGH and LOW, whereby the selection signal TEo ′ is switched to HIGH and LOW, and the opening and closing of the transistor 9ao is switched. That is, during the test, the test circuit connection control signal 9f becomes HIGH, the output of the inverter 9e becomes LOW, the transfer gate 9bo is turned on, and the HIGH signal of the selection signal TEo is transmitted to TEo ′. On the other hand, at the time of non-test, the test circuit connection control signal 9f becomes LOW, the output of the inverter 9e becomes HIGH, the transfer gate 9bo is turned off, the HIGH signal of TEo is not transmitted to TEo ', and TEo' becomes LOW by the pull-down circuit. Become. The TE gate decode circuit 9d sets the selection signal TEo to LOW and switches the selection signal TEe to HIGH when testing even-numbered columns of pixels. As in the case of the selection signal TEo, the test circuit connection control signal 9f is switched between HIGH and LOW according to the inspection flow, whereby the selection signal TEe ′ is switched between HIGH and LOW, and the opening and closing of the transistor 9ae is switched.

  Also in this embodiment, the equalization control signal EQ from the control units 20 and 21 and its inverted signal are supplied to the gate circuit 8a of the equalize circuit unit 8. The equalizing circuit unit 8 is turned on by the equalizing control signal EQ from the control units 20 and 21 and its inverted signal, so that the terminals so and se have the same potential. In the equalizing circuit unit 8, the gate circuit 8a is composed of a P-channel transistor and an N-channel transistor, and at the end of the equalizing process, the push-down and the push-up are generated substantially simultaneously. As a result, the terminal so , Se does not fluctuate.

  Next, the inspection method will be described with reference to the timing chart of FIG. Also in this embodiment, the entire flow of the inspection is the same as the flow of FIG. FIG. 13 shows a read operation in the present embodiment.

  The present embodiment is different from the first embodiment only in that the inspection wiring and the reference wiring can be switched to each other. In the example of FIG. 13, the TE gate decode circuit 9d sets the selection signal TEe 'to LOW, and the selection signal TEo' is switched to LOW and HIGH according to the inspection flow. That is, in this case, the transistor 9ao is turned on, the transistor 9ae is turned off, the odd-numbered source lines S1, S3,... Are connected to the so-wiring 4g, and the odd-numbered source lines S2, S4,. The connection with the wiring 4f is disconnected. That is, the example of FIG. 13 is in the same state as in the first embodiment, and the same inspection as in FIG. 8 is performed.

  Also in this case, at the time when the precharge control signal is changed from HIGH to LOW and the precharge process ends, the equalize control signal EQ remains HIGH and the equalization process is continued. Accordingly, the push-down generated at the terminal se is raised to the potential of the terminal so and returns to the substantially original intermediate potential.

  Further, when the equalization control signal EQ is changed from HIGH to LOW and the equalization process is completed, pushdown and pushup occur almost simultaneously, and as a result, the pushdown amounts of the terminals se and so are sufficiently equal. It becomes a small value. Thereby, the reference of the terminal se after the push-down does not become higher than the potential of the terminal so at the time of LOW writing, and an error does not occur in the determination result of the differential amplifier 4a.

  As shown in FIG. 13, the data read from the terminal so via the so wiring 4g and the odd-numbered source lines S1, S3,... Are output only from the odd-numbered outo.

  When inspecting even-numbered columns of pixels, the TE gate decode circuit 9d sets the selection signal TEo 'to LOW and switches the selection signal TEe' to LOW or HIGH according to the inspection flow. As a result, the transistor 9ao is kept off, the connection between the odd-numbered source lines S1, S3,... And the so-wiring 4g is disconnected, and the transistor 9ae is switched on and off, and the even-numbered source lines S2, S4 Are connected to the se wiring 4f.

  In this case, the intermediate precharge potential supplied from the voltage application terminal 3a to the so wiring, se wiring, and even-numbered source lines S2, S4,... Functions as a reference potential in the so wiring.

  Further, in this case, when the precharge is turned off, the potential of the terminal so is once relatively lowered by the push-down. However, equalization processing is continued at the time of precharge off, and the potential of the terminal so returns to the stable potential of the terminal se. Further, at the end of the equalization process, the push-down of the terminal so is suppressed by the push-down and push-up, and the push-down amounts of the terminals se and so become substantially equal and sufficiently small values. As a result, the reference of the terminal so after the push-down does not become higher than the potential of the terminal se at the time of LOW writing, and an error does not occur in the determination result of the differential amplifier 4a.

  Other operations and effects are the same as those of the first embodiment.

(Fourth embodiment) <Examination column switching external reference, shared type>
FIG. 14 is a circuit diagram showing a shared type electro-optical device substrate type belonging to the inspection column switching external reference type. Also in the present embodiment, an example in which the precharge process and the equalize process are ended at different timings is shown. In FIG. 14, the same components as those in FIG. 12 or FIG.

  In FIG. 14, the X driver unit 5a, the Y driver unit 5b, the video signal line 7 and the like for driving the display element array unit 2 are omitted for simplification of the drawing. The embodiment of FIG. 14 enables inspection of pixels connected to four source lines with one differential amplifier 4a. That is, one differential amplifier 4a can be formed at intervals of four source lines, and the area of the differential amplifier 4a can be widened to improve the driving capability and reduce the variation of the differential amplifier 4a. Thus, it is possible to improve the inspection accuracy.

  The substrate 11C in FIG. 14 has the configuration of the display element array unit 2, the X driver unit 5a, the Y driver unit 5b, the transmission gate unit 6, the video signal line 7, the differential amplifier 10, and the display data reading circuit unit 4 in FIG. It is the same as the substrate 1C. Further, the configuration of the equalizing circuit unit 8, the precharge and reference circuit unit 13 provided between the display data reading circuit unit 4 and the display element array unit 2 is the same as that of the substrate 1C in FIG.

  Further, the equalization control signal EQ from the control units 20 and 21 is given to the gate circuit 8a of the equalization circuit unit 8, and the gate circuit 8a is composed of a P-channel transistor and an N-channel transistor. It is the same.

  The present embodiment is different from the third embodiment in that a transmission gate portion 31 is employed instead of the transmission gate portion 19. The transmission gate unit 31 selectively connects the so wiring 4g to one of the two source lines, and selectively connects the se wiring 4g to one of the two source lines. That is, in the example of FIG. 14, the differential amplifier 4a is provided for every four source lines. The so wiring 4g connected to the terminal so of the differential amplifier 4a is connected to the source line of the (4u + 1) th column or the (4u + 2) th column via the transistors 32a and 32b, respectively. The se wiring 4f connected to the terminal se of the differential amplifier 4a is connected to the source line of the (4u + 3) th column or the (4u + 4) th column via the transistors 32c and 32d, respectively.

  The gates of the transistors 32a to 32d are connected to the TE gate decoding circuit 25 via transfer gates 24a to 24d, respectively. When the HIGH control signal is input to the terminal 27, the transfer gate 24a applies the selection signal TE1 from the TE gate decode circuit 25 to the gate of the transistor 32a. Similarly, the transfer gates 24b to 24d receive selection signals TE2 to TE4 from the TE gate decode circuit 25 to the gates of the transistors 32b to 32d, respectively, when a HIGH control signal is input to the terminal 27f.

  The TE gate decode circuit 25 outputs selection signals TE1 to TE4 for determining which of the four source lines the so wiring 4g or the so wiring 4f of the differential amplifier 4a is connected to. The transistors 32a to 32d to which the LOW selection signals TE1 to TE4 are applied to the gates are turned off, and the connection between the so wiring and the se wiring and the source line is disconnected. Conversely, the transistors 32a to 32d to which the HIGH selection signals TE1 to TE4 are applied to the gates are turned on to connect the so wiring and se wiring to the source lines.

  In the embodiment configured as described above, when the HIGH selection signal TE1 is output from the TE gate decoding circuit 25, the transistor 32a is turned on, and the source line of the (4u + 1) th column is connected to the so wiring 4g. The In this way, the quality of the pixels connected to the source lines S1, S5,...

  In this case, the equalization process is continued at the end of the precharge process, and then the equalization process is terminated. Therefore, the potentials of the pushed-down terminals se and so return to the original potential. Furthermore, at the end of the equalization process, push-down and push-up occur almost simultaneously. As a result, the push-down amount becomes a substantially equal and sufficiently small value, and the reference of the terminal se after push-down becomes LOW write It does not become higher than the potential of the terminal so at the time, and an error does not occur in the determination result of the differential amplifier 4a.

  Similarly, when the HIGH selection signals TE2 to TE4 are output from the TE gate decode circuit 25, the transistors 32b to 32d are turned on, and the (4u + 2) th column to the (4u + 4) source line are connected to the se wiring 4f. The In this way, good and bad inspection of the pixels connected to each source line S is performed.

  Also in this case, immediately before the data read from the pixel is supplied to the terminals so and se, the push-down amounts of the terminals se and so become substantially equal and sufficiently small values, and the reference of the terminals se and so after the push-down is performed. However, it does not become higher than the potential of the inspection terminal at the time of LOW writing, and an error does not occur in the determination result of the differential amplifier 4a.

  In the selection signals TE1 to TE4, only one selection signal corresponding to the column to be inspected is switched to HIGH according to the inspection flow, and the other three selection signals are kept LOW. The operation of setting one selection signal corresponding to the column to be inspected HIGH and switching the gate signals 32a to 32d to HIGH and LOW according to the inspection flow is the same as the selection signals TEo ′ and TEe ′ in FIG.

  Other operations and effects are the same as those of the embodiment of FIG.

(Fifth embodiment) <External reference type>
In the first to fourth embodiments, the example in which the precharge process and the equalize process are ended at different timings has been described. However, in order to perform the precharge process and the equalize process at different timings, it is necessary to generate the precharge control signal and the equalize control signal independently. The present embodiment is applied to an example in which a precharge control signal and an equalize control signal are shared and the precharge process and the equalize process are started and ended simultaneously.

  FIG. 15 is a circuit diagram illustrating an electro-optical device substrate according to a fifth embodiment, which is an external reference type. In FIG. 15, the same components as those in FIG.

  The substrate 41B in the present embodiment is different from the substrate 1B in FIG. 1 in that the control terminal 8b for inputting the precharge control signal is omitted. The control unit 20 or 21 is supplied with the precharge control signal PCG from the control terminal 3b.

  Further, the present embodiment is different from the first embodiment of FIG. 1 in that a precharge and reference circuit unit 42 is employed instead of the precharge and reference circuit unit 13. The precharge and reference circuit section 42 has two gate circuits 42co and 42ce corresponding to each differential amplifier 4a. The gate circuits 42co and ce are configured by connecting an N-channel transistor and a P-channel transistor in parallel. The gates of the N channel transistors constituting the gate circuits 42co and 42ce are supplied with the precharge control signal PCG as the equalize control signal EQ from the control terminal 3b. The gates of the P-channel transistors constituting the gate circuits 42co and 42ce are supplied with an inverted signal of the precharge control signal PCG as an inverted signal of the equalize control signal EQ from the output terminal o2 of the control unit 20 or 21.

  In each gate circuit 8a of the equalize circuit unit 8, the precharge control signal PCG is supplied as the equalize control signal EQ from the output terminal o1 of the control unit 20 or 21 to the gate of the N channel transistor. Further, the inverted signal of the precharge control signal PCG is supplied as the inverted signal of the equalize control signal EQ from the output terminal o2 of the control unit 20 or 21 to the gate of the P channel transistor constituting the gate circuit 8a.

  Next, the inspection method of the embodiment configured as described above will be described with reference to FIG. FIG. 16 is a timing chart corresponding to FIG. The timing chart of FIG. 16 is different from FIG. 8 in that the equalization control signal EQ is omitted and the precharge control signal PCG and the equalization control signal EQ are shared. That is, in the present embodiment, the timing for starting and ending the equalization process is only different from that in the first embodiment.

  In the present embodiment, the equalization process ends simultaneously with the end of the precharge process (see FIG. 16). In this case, it is conceivable that a large level of pushdown occurs at the terminals so and se at the end of the precharge process. However, in this embodiment, since the gate circuits 42co and 42ce of the reference circuit unit 42 are configured by P-channel transistors and N-channel transistors, it is possible to avoid the adverse effect of pushdown.

  FIG. 17 is a waveform diagram showing how potential fluctuations due to pushdown are eliminated. FIG. 17 shows a waveform when the control unit 20 shown in FIG. 6 is adopted as the control unit of FIG. FIG. 17 shows the precharge control signals PCG and EQ, the scanning signal supplied to the scanning line G1, the potential of the terminal so, and the potential of the terminal se.

  As described above, before supplying the signal potential from the pixel to the terminal so of the differential amplifier 4a, the precharge voltage is supplied to the se wiring 4f, the so wiring 4g as the inspection wiring, and the source line S, and the terminal se. , So are set to the same potential. For this precharge and equalization processing, a HIGH precharge control signal PCG is applied to the gates of the N-channel transistors of the gate circuits 42ce and 42co, and a LOW precharge control signal is applied to the gates of the P-channel transistors. . Further, a HIGH precharge control signal PCG (equalize control signal EQ) is applied to the gate of the N-channel transistor of the gate circuit 8a, and a LOW equalize control signal is applied to the gate of the P-channel transistor (see FIG. 17). .

  Immediately before the signal potential from the pixel is supplied to the terminal so of the differential amplifier 4a, the precharge control signal PCG (equalization control signal EQ) supplied to the control terminal 3b is stopped from HIGH in order to stop the precharge and equalization processing. Switch to LOW (see FIG. 17). With the switching from HIGH to LOW, push-down occurs at the terminals so and se due to the parasitic capacitance of the N-channel transistors of the gate circuits 42ce, 42co, and 8a. In this case, the push-down amount of the terminal se is relatively large as shown in FIG.

  However, in the present embodiment, the gate circuits 42ce, 42co, and 8a are configured by connecting an N-channel transistor and a P-channel transistor in parallel, and the HIGH pre-circuit from the terminal o2 of the control unit 20 is configured. The charge control signal PCG (equalize control signal EQ) causes push-up by each P-channel transistor. As a result, the potentials of the terminals so and se return to the original potential before the push-down (the potentials of the terminals so and se in FIG. 17).

  FIG. 18 shows a waveform when the control unit 21 shown in FIG. 7 is adopted as the control unit of FIG.

  In this case, as described above, the P channel type transistors and the N channel type transistors of the gate circuits 42co, 42ce, 8a output the positive charge control signal PCG (equalize control signal EQ) at the same timing. And an inverted output are supplied respectively. Therefore, the push-down by the N-channel transistor and the push-up by the P-channel transistor occur at the same time, and the reference does not fluctuate even at the end of the precharge process and the equalize process (the terminal so in FIG. 18). Thick line).

  Thus, also in the present embodiment, potential fluctuations at the terminals se and so at the end of the precharge process are suppressed, and no malfunction occurs in the differential amplifier 4a, so that highly accurate pixel inspection is possible.

(Sixth embodiment) <External reference, shared type>
FIG. 19 is a circuit diagram showing a shared type electro-optical device substrate belonging to the external reference type according to the sixth embodiment. Also in this embodiment, an example in which the precharge control signal and the equalize control signal are shared is shown. 19, the same components as those in FIGS. 11 and 15 are denoted by the same reference numerals, and description thereof is omitted.

  The substrate 43B in the present embodiment is different from the substrate 11B in FIG. 11 in that the control terminal 8b for inputting the precharge control signal is omitted. The control unit 20 or 21 is supplied with the precharge control signal PCG from the control terminal 3b.

  Further, the present embodiment is different from the second embodiment of FIG. 11 in that a precharge and reference circuit section 42 is employed instead of the precharge and reference circuit section 13.

  The embodiment configured as described above is different from the second embodiment shown in FIG. 11 in that the precharge process and the equalize process are performed almost at the time.

  Even in this case, in the embodiment, since the gate circuits 42co and 42ce of the reference circuit unit 42 are configured by the P-channel transistor and the N-channel transistor, it is possible to avoid the adverse effect of pushdown.

  Other operations and effects are the same as those of the second embodiment.

(Seventh embodiment) <Examination column switching external reference type>
FIG. 20 is a circuit diagram showing a test row switching external reference type electro-optical device substrate according to the seventh embodiment. Also in this embodiment, an example in which the precharge control signal and the equalize control signal are shared is shown. 20, the same components as those in FIGS. 12 and 15 are denoted by the same reference numerals, and description thereof is omitted.

  Substrate 41C in the present embodiment is different from substrate 1C in FIG. 20 in that control terminal 8b for inputting a precharge control signal is omitted. The control unit 20 or 21 is supplied with the precharge control signal PCG from the control terminal 3b.

  Further, the present embodiment is different from the third embodiment in FIG. 12 in that a precharge and reference circuit section 42 is employed instead of the precharge and reference circuit section 13.

  The embodiment configured as described above is different from the third embodiment shown in FIG. 12 in that the precharge process and the equalize process are performed at that time. FIG. 21 shows the inspection method of the present embodiment. FIG. 21 is a timing chart corresponding to FIG. 13 and is different from FIG. 13 in that the equalize control signal EQ is omitted and the precharge control signal PCG and the equalize control signal EQ are shared.

  Even in this case, in the embodiment, since the gate circuits 42co and 42ce of the reference circuit unit 42 are configured by the P-channel transistor and the N-channel transistor, it is possible to avoid the adverse effect of pushdown.

  Other operations and effects are the same as those of the third embodiment.

(Eighth embodiment) <Examination column switching external reference, shared type>
FIG. 22 is a circuit diagram showing a shared type electro-optical device substrate belonging to the inspection column switching external reference type according to the eighth embodiment. Also in this embodiment, an example in which the precharge control signal and the equalize control signal are shared is shown. In FIG. 22, the same components as those in FIGS. 14 and 15 are denoted by the same reference numerals, and description thereof is omitted.

  The substrate 43C in the present embodiment is different from the substrate 11C in FIG. 14 in that the control terminal 8b for inputting the precharge control signal is omitted. The control unit 20 or 21 is supplied with the precharge control signal PCG from the control terminal 3b.

  Further, the present embodiment is different from the fourth embodiment in FIG. 14 in that a precharge and reference circuit section 42 is employed instead of the precharge and reference circuit section 13.

  The embodiment configured as described above is different from the fourth embodiment shown in FIG. 14 in that the precharge process and the equalize process are performed almost at that time.

  Even in this case, in the embodiment, since the gate circuits 42co and 42ce of the reference circuit unit 42 are configured by the P-channel transistor and the N-channel transistor, it is possible to avoid the adverse effect of pushdown.

  Other operations and effects are the same as those of the fourth embodiment.

  As described above, in the above three embodiments, the electro-optical device substrate of the present invention has been described by taking the active matrix display device substrate as an example, but the present invention is limited to the above-described embodiments. However, various changes and modifications can be made without departing from the scope of the present invention.

  For example, by providing an optical sensor in the display portion, it can be applied to a display device substrate having an input function. In each of the above embodiments, the example in which the same number of source lines are connected to the two terminals of the differential amplifier has been described. However, a different number of source lines may be connected to each other.

  An electro-optical device using the substrate for an electro-optical device of the present invention is also included in the present invention.

  For example, an electro-optical device in which an electro-optical material is sandwiched between a pair of substrates, and the substrate for an electro-optical device of the present invention is used for one of the pair of substrates.

  The present invention can also be applied to the liquid crystal device LCOS using a silicon substrate by the same means as in the above embodiment.

The present invention can also be applied as a test circuit for a memory in a pixel in various electro-optical devices in which a memory element such as an SRAM is formed in the pixel, and the effects as described above can be achieved. In this case, applicable electro-optical devices include an organic EL display, a plasma display, a field emission display (FED, SED), a digital micromirror device, and the like in addition to the liquid crystal device.

  Further, an electronic apparatus using the above electro-optical device is also included in the present invention. 23 and 24 are diagrams illustrating examples of electronic devices. FIG. 23 is an external view of a personal computer according to one example. FIG. 24 is an external view of a mobile phone according to one example. As shown in FIG. 23, the above-described electro-optical device, for example, a liquid crystal display device is used for the display unit 101 of a personal computer 100 as an electronic apparatus. As shown in FIG. 24, the above-described electro-optical device, for example, a liquid crystal display device, is used for the display unit 201 of the mobile phone 200 as an electronic device.

  In addition, as an electronic device, for example, a projection display device including a light source, a light valve that modulates light emitted from the light source, and an optical system for projecting light modulated by the light valve It is. Furthermore, other electronic devices include televisions, viewfinder type / monitor direct view type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, digital Examples include a still camera and a device equipped with a touch panel. Needless to say, the display panel according to the present invention is applicable to these various electronic devices.

  The present invention is not limited to the liquid crystal display device including the TFT described above, and can be applied to an active matrix drive display device.

1 is a circuit diagram illustrating an external reference type electro-optical device substrate according to a first embodiment of the present invention; FIG. FIG. 2 is an equivalent circuit diagram of a pixel 2a in FIG. FIG. 2 is a circuit diagram showing a specific configuration of a differential amplifier 4a of a display data reading circuit unit 4 in FIG. The block diagram of an inspection system. The flowchart which shows the example of the whole flow of a test | inspection. FIG. 2 is a circuit diagram illustrating a specific configuration of a control unit 20 that can be employed in FIG. 1. FIG. 2 is a circuit diagram showing a specific configuration of a control unit 21 that can be employed in FIG. 1. 6 is a timing chart for explaining a read operation in step ST2 of FIG. The wave form diagram which shows a mode that the electric potential fluctuation | variation by pushdown is eliminated. The wave form diagram which shows a mode that the electric potential fluctuation | variation by pushdown is eliminated. FIG. 6 is a circuit diagram illustrating a shared type electro-optical device substrate belonging to an external reference type according to a second embodiment of the present invention. The circuit diagram which shows the board | substrate for electro-optical apparatuses of a test | inspection row switching external reference type | mold concerning the 3rd Embodiment of this invention. The timing chart for demonstrating the inspection method of 3rd Embodiment. The circuit diagram which shows the substrate type | mold for shared type electro-optical apparatuses which concerns on the 4th Embodiment of this invention and belongs to a test | inspection row switching external reference type | mold. FIG. 9 is a circuit diagram illustrating an external reference type electro-optical device substrate according to a fifth embodiment of the present invention. 10 is a timing chart for explaining a read operation according to the fifth embodiment. The wave form diagram which shows a mode that the electric potential fluctuation | variation by pushdown is eliminated. The wave form diagram which shows a mode that the electric potential fluctuation | variation by pushdown is eliminated. The circuit diagram which shows the board | substrate for shared type electro-optical apparatuses which concerns on the 6th Embodiment of this invention and belongs to an external reference type | mold. The circuit diagram which shows the board | substrate for electro-optical apparatuses of a test | inspection row switching external reference type | mold concerning the 7th Embodiment of this invention. The timing chart for demonstrating the inspection method of 7th Embodiment. The circuit diagram which shows the board | substrate type | mold for a shared type electro-optical apparatus which concerns on the 8th Embodiment of this invention and belongs to a test | inspection row switching external reference type. It is a perspective view which shows the example of an electronic device. It is a perspective view which shows the example of an electronic device.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1B Element board | substrate, 2 Display element array part, 4 Display data read-out circuit part, 4a Differential amplifier, 9 '... Transfer gate part, 13 ... Precharge and reference circuit part, 20, 21 ... Control part.

Claims (11)

A plurality of scanning lines and a plurality of source lines intersecting each other;
A plurality of pixels arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines;
The first and second terminals are provided, and the potential signal supplied to the first terminal is compared with the potential signal supplied to the second terminal, and then supplied to the first terminal. When the potential signal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is raised and output. An amplifier;
After supplying a precharge voltage to the first and second terminals, a reference voltage is supplied to one of the first and second terminals, and a potential signal written to the pixel is read and supplied to the other. Supply means;
A P channel connected to the first and second terminals, wherein the first and second terminals have the same potential at least when the supply of the precharge voltage by the supply means is completed. An electro-optical device substrate, comprising: an equalizing unit including a n-channel transistor and an n-channel transistor.   2. The electro-optical device substrate according to claim 1, wherein the equalizing means includes a P-channel transistor and an N-channel transistor connected in parallel. A plurality of scanning lines and a plurality of source lines intersecting each other;
A plurality of pixels arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines;
A first potential signal supplied to the first terminal and a second potential signal supplied to the second terminal; An amplifier that lowers the potential of the first terminal when the potential signal of 1 is low, and outputs a higher potential of the first terminal when the first potential signal is high;
Supply means for supplying a precharge voltage to the first and second terminals via a precharge power supply line;
Means for maintaining and supplying the precharge voltage to the first terminal as the first potential signal;
By connecting the inspection line connected to the second terminal and the source line, the potential signal written to the pixel is read out and used as the second potential signal through the source line and the inspection line. Connecting means for supplying to the second terminal;
A P channel connected to the first and second terminals, wherein the first and second terminals have the same potential at least when the supply of the precharge voltage by the supply means is completed. An electro-optical device substrate, comprising: an equalizing unit including a n-channel transistor and an n-channel transistor.   The electro-optical device substrate according to claim 3, wherein the connection unit selects one source line from the plurality of source lines and connects the selected source line to the inspection wiring. A plurality of scanning lines and a plurality of source lines intersecting each other;
A plurality of pixels arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines;
The first and second terminals are provided, and the potential signal supplied to the first terminal is compared with the potential signal supplied to the second terminal, and then supplied to the first terminal. When the potential signal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is raised and output. An amplifier;
Supply means for supplying a reference voltage to one of the first and second terminals after applying a precharge voltage to the first and second terminals;
By connecting the inspection wiring connected to the other of the first and second terminals and the source line, the potential signal written to the pixel is read and the other of the first and second terminals is read. Connecting means to supply;
A P channel connected to the first and second terminals, wherein the first and second terminals have the same potential at least when the supply of the precharge voltage by the supply means is completed. An electro-optical device substrate, comprising: an equalizing unit including a n-channel transistor and an n-channel transistor.   The electro-optical device substrate according to claim 5, wherein the connection unit selects one source line from the plurality of source lines and connects the selected source line to the inspection wiring. A plurality of scanning lines and a plurality of source lines intersecting each other;
A plurality of pixels arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines;
The first and second terminals are provided, and the potential signal supplied to the first terminal is compared with the potential signal supplied to the second terminal, and then supplied to the first terminal. When the potential signal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is raised and output. An amplifier;
After applying a precharge voltage to the first and second terminals, a reference voltage is supplied to one of the first and second terminals, and a potential signal written to the pixel is read and supplied to the other. Precharge voltage supply means comprising a first P-channel transistor and a first N-channel transistor connected to the first and second terminals,
The potentials of the first and second terminals are the same, and the second P-channel transistor and the second N-channel transistor are connected to the first and second terminals. An electro-optical device substrate comprising equalizing means. A plurality of scanning lines and a plurality of source lines intersecting each other;
A plurality of pixels arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines;
A first potential signal supplied to the first terminal and a second potential signal supplied to the second terminal; An amplifier that lowers the potential of the first terminal when the potential signal of 1 is low, and outputs a higher potential of the first terminal when the first potential signal is high;
A precharge voltage is supplied to the first and second terminals via a precharge power supply line, and a first P-channel transistor connected to the first and second terminals and a first Precharge voltage supply means comprising N-channel transistors;
Means for maintaining and supplying the precharge voltage as the first potential signal to the first terminal;
By connecting the inspection line connected to the second terminal and the source line, the potential signal written to the pixel is read out and used as the second potential signal through the source line and the inspection line. Connecting means for supplying to the second terminal;
The potentials of the first and second terminals are the same, and the second P-channel transistor and the second N-channel transistor are connected to the first and second terminals. An electro-optical device substrate comprising equalizing means. A plurality of scanning lines and a plurality of source lines intersecting each other;
A plurality of pixels arranged in a matrix corresponding to the intersection of the plurality of scanning lines and the plurality of source lines;
The first and second terminals are provided, and the potential signal supplied to the first terminal is compared with the potential signal supplied to the second terminal, and then supplied to the first terminal. When the potential signal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is raised and output. An amplifier;
After applying a precharge voltage to the first and second terminals, a reference voltage is supplied to one of the first and second terminals, and is connected to the first and second terminals Precharge voltage supply means comprising a first P-channel transistor and a first N-channel transistor;
By connecting the inspection wiring connected to the other of the first and second terminals and the source line, the potential signal written to the pixel is read and the other of the first and second terminals is read. Connecting means to supply;
The potentials of the first and second terminals are the same, and the second P-channel transistor and the second N-channel transistor are connected to the first and second terminals. An electro-optical device substrate comprising equalizing means.   An electro-optical device in which a pair of substrates are bonded to each other, and the electro-optical device substrate according to claim 1 is used as one of the pair of substrates. apparatus.   An electronic apparatus using the electro-optical device according to claim 10.

Images