JP2007156432A - Electrooptical apparatus and electronic apparatus provided with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To judge the quality or the like of pixels in each pixel in an electrooptical apparatus such as a liquid crystal apparatus. <P>SOLUTION: The electrooptical apparatus having a plurality of scanning lines, a plurality of data lines, a plurality of pixel parts, and first and second nodes, which are formed on a substrate, includes an amplifier for comparing the potential of a potential signal supplied to the first node with that of a potential signal supplied to the second node, further lowering the potential of the first node when the potential of the potential signal supplied to the first node is low, and further increasing the potential of the first node when the potential of the potential signal supplied to the first node is high. Further, the electrooptical apparatus has a portion electrically connected to the first node and wired along a direction in which the data lines are extended, a reference potential signal line for supplying reference potential to the first node and a supply means for reading out a potential signal input to a pixel part and supplying the potential signal to the second node. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In an electro-optical device such as a liquid crystal device, a step of inspecting an electro-optical device substrate such as an element substrate on which a transistor or the like is formed, and a counter electrode for driving the element substrate and an electro-optical element such as a liquid crystal are formed. The liquid crystal is manufactured through a process of encapsulating liquid crystal between the opposing substrates. The inspection of whether or not the finished liquid crystal device operates normally is performed based on whether or not the image displayed by the completed liquid crystal device is correctly displayed. In such an electro-optical device, if a defect of the transistor formed on the element substrate is not detected in the step of inspecting the element substrate, the defect is detected by an inspection performed on the liquid crystal device which is a finished product. It will be.

  As countermeasures when a defect is detected in the finished liquid crystal device, measures such as exchanging the element substrate after the liquid crystal is extracted from the liquid crystal device or repairing the defective part can be considered. Considering the decrease in production yield and the increase in cost, it is substantially difficult to adopt these measures. In addition, the process after forming the element substrate becomes a useless process, resulting in a decrease in yield and an increase in cost when manufacturing an electro-optical device such as a liquid crystal device.

  As one means for solving such a problem, for example, in Patent Document 1, a pixel is associated with all intersections of two signal lines and scanning lines electrically connected to a comparator in a pixel array. Disclosed is a technique for inspecting whether a pixel has a defect by comparing potential information supplied to two pixels when the electro-optical device substrate is formed.

JP 2004-226551 A

  However, according to the technique disclosed in Patent Document 1, when a pixel arranged in a region where one signal line and a scanning line intersect between two signal lines electrically connected to a comparator is inspected The potentials of the signals supplied to the pixels arranged in the region where the other signal line and the scanning line intersect with each other become the reference potential, and the reference potential fluctuates due to a defect in the pixel on the reference potential side. As a result, it is determined that there is a defect in a normal pixel to be inspected, and there is a technical problem that a defect of one pixel is detected as a defect of two pixels. In addition, there is a technical problem that it is difficult to electrically detect what kind of trouble occurs in which part of a semiconductor element or capacitor such as a transistor included in one pixel.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device that can determine whether each pixel is good or bad, and an electronic apparatus including the electro-optical device. To do.

  In order to solve the above problems, the electro-optical device of the present invention corresponds to a plurality of scanning lines and a plurality of data lines intersecting each other on the substrate, and the intersection of the plurality of scanning lines and the plurality of data lines. A plurality of pixel portions arranged in a matrix and first and second nodes, and a potential of a potential signal supplied to the first node and a potential signal supplied to the second node When the potential signal supplied to the first node is low, the potential of the first node is made lower, and when the potential signal supplied to the first node is high, An amplifier that outputs the first node with a higher potential; a portion that is electrically connected to the first node and that extends along the direction in which the data line extends; Reference potential signal for supplying a reference potential to one node Comprising lines and, and a supply means for supplying read the potential signal input to the pixel portion on the second node.

  According to the electro-optical device of the present invention, during the operation, an image signal is supplied to each pixel unit via the data line, for example, by an X driver circuit. At the same time, a scanning signal is supplied to each pixel portion via the scanning line by the Y driver circuit. For example, a pixel switching transistor provided for each pixel portion has a gate connected to the scanning line, and selectively supplies an image signal to the pixel electrode in accordance with the scanning signal. Thus, for example, by driving an electro-optical material such as liquid crystal sandwiched between the pixel electrode and the counter electrode in each pixel unit, a plurality of pixel units are arranged in a matrix, for example, a pixel region or Image display is performed in the pixel array region (or also referred to as “image display region”). At this time, the storage capacitor improves the potential holding characteristic in the pixel portion, and the display can have high contrast. For example, a transmissive pixel electrode that transmits incident light or a reflective or transflective pixel electrode that reflects incident light is used as the pixel electrode.

  In particular, the present invention includes a reference potential signal line, supply means, and an amplifier.

  In a test performed prior to the operation of the electro-optical device, a reference potential is supplied to the first node of the amplifier via a reference potential signal line. On the other hand, the potential signal input to, for example, the pixel electrode in the pixel portion is read and supplied to the second node of the amplifier by the supply unit. Such inspection is preferably performed before the electro-optical device is bonded to the pair of substrates, for example, when a substrate called an element array substrate, an element substrate, or a TFT array substrate is completed. Is done. Here, the potential signal read from the pixel portion is a signal reflecting the quality of the pixel portion. More specifically, for example, an inspection signal is supplied to the pixel portion in advance prior to the inspection, and a signal having a potential that varies from the potential of the inspection signal according to the quality of the pixel portion is output as a potential signal. “Possibility of the pixel portion” means whether or not the pixel portion has a defect, and the level relationship between the reference potential and the potential of the potential signal varies depending on the defect occurring in the pixel portion.

  The amplifier compares the potential of the reference potential supplied to the first node and the potential signal supplied to the second node. If the reference potential supplied to the first node is low, the amplifier When the potential of the node is lowered and the reference potential supplied to the first node is high, the potential of the first node is raised and output. That is, at the time of this inspection, for example, the potential signal output from the pixel portion and supplied to the second node has a slightly lower potential than the reference potential supplied to the first node via the reference potential signal line. In some cases, the amplifier is supplied to the second node so that the lower potential of the potential signal supplied to the second node than the reference potential is not obscured by noise applied to the wiring such as the data line. A low potential signal having a lower potential than the potential signal to be output is output. On the other hand, for example, when the potential signal output from the pixel portion and supplied to the second node has a slightly higher potential than the reference potential supplied to the first node via the reference potential signal line. The amplifier is supplied to the second node so that the potential of the potential signal supplied to the first node higher than the reference potential is not obscured by noise applied to the wiring such as the data line. A high potential signal having a higher potential than the potential signal is output.

  The low potential signal or the high potential signal output from the amplifier in this way is a signal reflecting the quality of the pixel portion described above. For example, if the potential signal supplied in advance to the pixel portion is higher than the reference potential and the high potential signal is output from the amplifier, the pixel portion corresponding to the data line electrically connected to the second node is defective. It is determined that it has not occurred. On the other hand, if the potential signal supplied in advance to the pixel portion is higher than the reference potential and the low potential signal is output from the amplifier, there is some problem in the pixel portion corresponding to the signal line electrically connected to the second node. Is determined to have occurred. On the other hand, for example, when the potential signal supplied to the pixel portion in advance is lower than the reference potential, if the low potential signal is output from the amplifier, the pixel portion corresponding to the data line electrically connected to the second node This means that no problem has occurred. On the other hand, if the potential signal supplied in advance to the pixel portion is lower than the reference potential, if a high potential signal is output from the amplifier, it is determined that some trouble has occurred in the pixel portion electrically connected to the data line. The

  Further, particularly in the present invention, the reference potential signal line is electrically connected to the first node and supplied with the reference potential. In other words, the reference potential is supplied to the first node from, for example, an external circuit via the reference potential signal line. Therefore, since the reference potential can be stably supplied from the outside, it is possible to reliably determine the quality of the pixel portion. That is, a defect in the pixel portion can be detected as a defect for each pixel portion. Further, it is possible to electrically detect what kind of trouble occurs in which part of the pixel switching transistor or the storage capacitor included in each pixel portion.

  Further, particularly in the present invention, the reference potential signal line has a portion wired along the direction in which the data line extends. Typically, when viewed in plan on the substrate, the wiring is arranged in line with the data line and extends from the first node to the opposite side to the pixel region where the plurality of pixel portions are arranged. It has the part which was made. That is, the reference potential signal line is wired alternately with the data line in the pixel region. In other words, the reference potential signal line is wired in almost the same pattern as the data line, that is, along the data line or ideally in parallel when viewed in plan on the substrate. At this time, the reference potential signal line may partially or completely overlap the data line when viewed in plan on the substrate, or may be wired side by side. It is desirable that the reference potential signal line and the data line have, for example, almost or completely the same length and width. Therefore, the difference in wiring capacitance between the data line and the reference potential signal line can be eliminated almost or completely in practice. Further, when some electrical noise occurs in the pixel region, the data line and the reference potential signal line are affected almost or completely by the same noise, and are supplied to the first node by the amplifier. It can be reduced or prevented that the level relationship between the reference potential and the potential of the potential signal supplied to the second node is reversed due to the influence of noise. Therefore, the amplifier can be prevented from malfunctioning, and an accurate comparison result can be obtained.

  As described above, according to the electro-optical device according to the invention, it is possible to detect a defect in the pixel unit as a defect for each pixel unit. Further, it is possible to electrically detect what kind of trouble occurs in which part of the pixel switching transistor or the storage capacitor included in each pixel portion. In addition, the quality of the pixel portion can be determined with little or no influence from the difference in wiring capacitance between the data line and the reference potential signal line or the noise in the pixel region.

  In one aspect of the electro-optical device according to the aspect of the invention, each of the plurality of pixel portions includes a reflective or transflective pixel electrode, and the reference potential signal line is interposed between the pixel electrode and an interlayer insulating film. Then, the pixel electrodes are wired so as to overlap each other when viewed in plan on the lower layer side and on the substrate.

  According to this aspect, each pixel unit includes a reflective pixel electrode made of aluminum or the like, or a transflective pixel made of aluminum or the like having a hole or gap for light transmission. The liquid crystal device is provided with an electrode and is a reflective or transflective liquid crystal device such as LCOS (Liquid Crystal On Silicon). Since the reference potential signal line is wired on the lower layer side than such a pixel electrode, it can be relatively freely wired without affecting the display by the reflective or transflective liquid crystal device. That is, the reference potential signal line can be wired with little or no decrease in the aperture ratio as compared with the case of the transmissive liquid crystal device.

  In another aspect of the electro-optical device of the present invention, a potential signal that is electrically connected to the reference potential signal line and the data line and is supplied to the pixel portion and a potential signal supplied to the reference potential signal line, Is supplied to the data line, and a precharge signal for precharging the reference potential signal line and the data line is supplied to the reference potential signal line.

  According to this aspect, a logical sum of, for example, an image signal supplied via an image signal line and a precharge signal supplied via a reference potential signal line is output to the data line by a logic circuit which is an OR circuit, for example. Is done. Therefore, at the time of inspection, for example, after a potential signal is written in advance in the pixel portion, the reference potential signal line and the data line can be precharged via the reference potential signal line. Further, at the time of normal display, the data line can be precharged via the reference potential signal line in the blanking period. That is, the reference potential signal line supplies a reference potential to the amplifier at the time of inspection, and can function as a precharge supply line for precharging the reference potential signal line or the data line at the time of inspection and normal display.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, an active matrix driving type liquid crystal device with a built-in driving circuit, which is an example of the electro-optical device of the present invention, is taken as an example.

<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.
First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, the element substrate 10 and the counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the element substrate 10 and the counter substrate 20, and the element substrate 10 and the counter substrate 20 are mutually connected by a sealing material 52 provided in a seal region located around the image display region 10a. It is glued to.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. An X driver circuit 101 and an external circuit connection terminal 102 are provided along one side of the element substrate 10 in a region located outside the seal region where the sealing material 52 is disposed in the peripheral region. A sampling circuit 77 is provided inside the seal region along one side so as to be covered with the frame light-shielding film 53. The Y driver circuit 104 is provided so as to be covered with the frame light shielding film 53 inside the seal region along two sides adjacent to the one side. On the element substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the element substrate 10 and the counter substrate 20.

  On the element substrate 10, lead wires 90 are formed for electrically connecting the external connection terminals 102 to the X driver circuit 101, the Y driver circuit 104, the vertical conduction terminal 106, and the like.

  In FIG. 2, a stacked structure is formed on the element substrate 10 in which wirings such as pixel switching transistors, scanning lines, and data lines as drive elements are formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching transistor, a scanning line, and a data line. In the present embodiment, a reflective pixel electrode that reflects incident light is used as the pixel electrode 9a. Alternatively, the pixel electrode 9a may be a transflective pixel electrode configured to reflect incident light that is external light and to transmit light source light from a backlight in a dark place. On the other hand, on the surface of the counter substrate 20 facing the element substrate 10, at least a counter electrode 21 made of a transparent material such as ITO (Indium Tin Oxide) is formed facing the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the X driver circuit 101 and the Y driver circuit 104, the element substrate 10 will be described later for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. As described above, the precharge and reference circuit 13 constituting a part of the “supply means” according to the present invention, the differential amplifier circuit 4a as an example of the “amplifier” according to the present invention, and the like are formed.

  Next, the circuit configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 3 is a block diagram showing the main circuit configuration of the liquid crystal device according to this embodiment. FIG. 4 is a circuit diagram showing an electrical configuration of the pixel portion.

  3, the liquid crystal device according to the present embodiment includes a pixel unit 2a, a sampling circuit 77, a Y driver circuit 104, an X driver circuit 101, a display data readout circuit 4, a transmission gate 60, a precharge and reference circuit on an element substrate 10. 13 is provided.

  The pixel portion 2a is two-dimensionally arranged in a matrix of n rows × m columns in the image display area 10a. Here, m and n are natural numbers, respectively. More specifically, as shown in FIG. 3, the pixel unit 2 a includes the first column, the second column,..., The m-th column from the right side in the image display region 10 a, the first row, the second column from the upper side. Are arranged in a matrix of rows,..., N-th row. That is, the pixel portion 2a which is a unit display element is provided corresponding to the intersection of the data line S (ie, S1, S2,... Sm) and the scanning line G (ie, G1, G2,..., Gn). It has been.

  As shown in FIG. 4, the pixel unit 2a includes a transistor 30, a liquid crystal capacitor Clc, and an additional capacitor Cs.

  The liquid crystal capacitance Clc is a capacitance due to the pixel electrode 9a, the counter electrode 21, and the liquid crystal layer 50 (see FIG. 2).

  The additional capacitor Cs is electrically connected in parallel with the liquid crystal capacitor Clc.

  The transistor 30 has a source terminal s electrically connected to the data line S and a gate terminal g electrically connected to the scanning line G. The transistor 30 is turned on and off by a predetermined voltage signal supplied from the Y driver circuit 104.

  The drain of the transistor 30 is electrically connected to one end of each of the liquid crystal capacitor Clc and the additional capacitor Cs, and the other end of the additional capacitor Cs is electrically connected to the common fixed potential CsCOM. When a predetermined voltage signal is input to the gate terminal g of the transistor 30 and the transistor 30 is turned on, the voltage applied to the source terminal s of the transistor 30 electrically connected to the data line S is the liquid crystal capacitance Clc and the additional capacitance. The predetermined potential applied and applied to Cs is maintained. Thereby, it is possible to hold the image signal (or also referred to as “pixel signal”) supplied to the pixel unit 2a for a long time when image display is performed.

  In FIG. 3 again, the sampling circuit 77 includes a plurality of sampling switches 77s, and in response to the output timing signal from the X driver circuit 101, the image signal input from the video signal line 7 is converted into the data lines S1, S2,. ..., supplied to Sm. The video signal line 7 includes a signal line that supplies a signal to an odd column of the plurality of pixel portions 2a in a matrix and a signal line that supplies a signal to the even column, and are electrically connected to terminals ino and ine, respectively. Has been. The data lines S1, S2,..., Sm are electrically connected to the n pixel units 2a in each column, and the image signals from the data lines S1, S2,. The pixel portion 2a (more specifically, the liquid crystal capacitance Clc and the additional capacitance Cs included in each pixel portion 2a) is written.

  As shown in FIG. 3, the video signal line 7 is provided with a differential amplifier 110 including a current mirror amplifier. The differential amplifier 110 prevents a difference between a high level signal (hereinafter referred to as “HIGH signal”) and a low level signal (hereinafter referred to as “LOW signal”) from being reduced due to a capacitance component of the video signal 7 itself. Therefore, the HIGH signal and the LOW signal are clarified and the output signals outo and oute are output at high speed and with high accuracy.

  The display data reading circuit 4 is provided on the element substrate 10 for the inspection of the pixel portion 2a. The display data reading circuit 4 includes a plurality of pixel portions 2a provided in the image display region 10a as viewed in plan on the element substrate 10. Between the display data reading circuit 4, there is provided a transmission gate 60 constituting a part of the “supplying unit” according to the present invention.

  The display data readout circuit 4 has a plurality of differential amplifier circuits 4a, and serves as a reference for inspection and the potential read from the pixel portion to be inspected at the two input nodes se and so of the differential amplifier circuit 4a. A reference potential (also referred to as “reference”) is supplied.

  Here, the differential amplifier circuit included in the display data reading circuit will be described with reference to FIGS. FIG. 5 is a circuit diagram showing the electrical configuration of the differential amplifier circuit.

  In FIG. 5, a differential amplifier circuit 4a is a cross-coupled differential amplifier circuit including p-channel Tr1 and Tr2 and n-channel Tr3 and Tr4. More specifically, a series circuit in which Tr1 and Tr2 are electrically connected in series and a series circuit in which Tr3 and Tr4 are electrically connected in series are electrically connected in parallel. The gates of Tr1 and Tr3 are electrically connected to the node so. The gates of Tr2 and Tr4 are electrically connected to the node se. The connection points of the sources and drains of the transistors Tr1 and Tr2 are electrically connected to the power supply node sp, and the connection points of the sources and drains of the transistors Tr3 and Tr4 are electrically connected to the power supply node sn.

  As shown in FIG. 3 again, the nodes se and so are electrically connected to the se wiring 4f and the so wiring 4g that supply potentials to these nodes, respectively. A signal potential read from the pixel portion 2a to be inspected is supplied to the se wiring 4f, and a reference (that is, a reference potential) is supplied to the so wiring 4g. The power supply node sp is supplied with the power supply voltage VDD through the power supply transistor 4d, and the power supply node sn is supplied with the ground potential from the reference potential point through the power supply transistor 4e. The power supply transistors 4d and 4e are controlled to be turned on and off by drive signals SAp-ch and SAn-ch supplied via terminals 4b and 4c, respectively.

  Note that a pull-up circuit 31 is electrically connected to the terminal 4b. FIG. 6 is a circuit diagram showing an electrical configuration of the pull-up circuit. As shown in FIG. 6, the pull-up circuit 31 includes a p-channel transistor 131 whose gate is grounded. The transistor 31 supplies the power supply VDD to the terminal 4b.

  In FIG. 5, the differential amplifier circuit 4a configured in this way raises the potential supplied to the nodes se and so to one of the power supply potential and the other to the potential of the reference potential point (for example, ground potential). . For example, when a potential slightly higher than the node so is supplied to the node se, the transistor Tr4 is turned on first among the transistors Tr1 to Tr4. Since the transistor Tr4 is turned on, the potential of the node so drops to the low ground potential of the node sn. Then, the node so falls to the low ground potential of the node sn, so that the transistor Tr1 whose gate end is electrically connected to the node so is turned on. As a result, the node se rises to the high power supply voltage VDD of the power supply node sp. On the other hand, when a potential slightly lower than that of the node so is supplied to the node se, the transistor Tr3 is turned on first among the transistors Tr1 to Tr4. Since the transistor Tr3 is turned on, the potential of the node se is lowered to the low ground potential of the node sn. Then, since the node se is lowered to the low ground potential of the node sn, the transistor Tr2 whose gate end is electrically connected to the node se is turned on. As a result, the node so rises to the high power supply voltage VDD of the power supply node sp.

  As described above, the differential amplifier 4a functions to increase the higher potential among the potentials applied to the nodes se and so, and lower the lower potential.

  In FIG. 3 again, the transmission gate 60 is constituted by transistors 60s provided corresponding to the data lines S1, S2,... Sm. The se wiring 4f electrically connected to the node se of the differential amplifier 4a is electrically connected to the source of the transistor 60s, and the gate of the transistor 60s is electrically connected to the control terminal 9b. The transistor 60s is turned on by a HIGH connection control signal input via the control terminal 9b, and a test device provided outside the liquid crystal device is connected to the data lines S1, S2,. ing.

  The control terminal 9b is electrically connected to the pull-down circuit 35. FIG. 7 is a circuit diagram showing an electrical configuration of the pull-down circuit. As shown in FIG. 7, the pull-down circuit 35 includes a transistor 135. By the pull-down circuit 35, the control terminal 9b is normally kept LOW. Thus, during normal display, the transistor 60s is off and the display data read circuit 4 is disconnected from each data line S. At the time of testing (or at the time of inspection), a high connection control signal is supplied to the connection control terminal 9b, so that the transistor 60s is turned on and the display data reading circuit 4 is electrically connected to the data line S. It has become. In FIG. 3, the pull-down circuits 32, 33, 34 e and 34 o are configured similarly to the pull-down circuit 35.

  In FIG. 3, a precharge / reference circuit 13 and an equalize circuit 8 are also provided between the plurality of pixel portions 2 a and the display data readout circuit 4. The equalize circuit 8 constitutes an example of the “supply means” according to the present invention, together with the precharge and reference circuit 13 and the transmission gate 60 described above.

  The precharge and reference circuit 13 includes two transistors 3ce and 3co corresponding to each differential amplifier circuit 4a. The source of the transistor 3co is electrically connected to the voltage application terminal 3a via a reference potential signal line R (that is, a reference potential signal line R1,..., Rm) described later, and the drain is connected via the so wiring 4g. It is electrically connected to the node so of the differential amplifier circuit 4a. The transistor 3ce has a source electrically connected to the voltage application terminal 3a via the reference potential signal line R, and a drain electrically connected to the node se of the differential amplifier circuit 4a via the se wiring 4f. Yes. A precharge voltage is supplied to the voltage application terminal 3a. The precharge voltage is also used as a reference signal as it is.

  The gates of the transistors 3ce and 3co are electrically connected to control terminals 3be and 3bo, respectively, and precharge control signals PCG1 and PCG2 are input to the control terminals 3be and 3bo, respectively. By applying HIGH precharge control signals PCG1 and PCG to the gates of the transistors 3co and 3ce, the transistors 3ce and 3co are turned on, respectively, and the precharge voltage supplied to the control terminal 3a is applied to the se wiring 4f and the so wiring. To supply to each.

  That is, the so wiring 4g electrically connected to the node so of the differential amplifier circuit 4a is used as a reference wiring for maintaining the precharge voltage from the outside as the reference voltage and supplying it to the node so.

  That is, in the liquid crystal device according to the present embodiment, the se wiring 4f as the inspection wiring electrically connected to the node se of the differential amplifier circuit 4a and the data line S are electrically connected, and one differential The pixel portion electrically connected to one data line S can be inspected by the amplifier circuit 4a. Note that the number of differential amplifier circuits 4a is the same as the number m of columns of the plurality of pixel portions 4a arranged in a matrix of n rows × m columns.

  In the precharge period at the time of inspection, a precharge voltage is supplied to the so wiring 4g and the se wiring 4f. The precharge process is for applying a precharge voltage to the data line S, the so wiring 4g, and the se wiring 4f in order to inspect various characteristics. Various voltages can be selected as the precharge voltage. For example, the power supply voltage VDD or the ground potential may be used, or an intermediate potential thereof may be used. In this embodiment, the precharge voltage is set to an intermediate potential, for example.

  In FIG. 3, the equalize circuit 8 has n transistors 8a whose sources and drains are electrically connected to the so wiring 4g and the se wiring 4f, respectively. The transistor 8a has a gate electrically connected to the control terminal 8b and is turned on by a HIGH equalization control signal from the control terminal 8b so that the so wiring 4g and the se wiring 4f have the same potential. .

  By the way, in the inspection of the pixel portion of the liquid crystal device according to the present embodiment, as described later, for example, LOW or HIGH is written in each pixel portion 2a, and the signal written in the pixel portion 2a is read to read the differential amplifier circuit 4a. Is given to the node se. On the other hand, a reference is given to the node so of the differential amplifier circuit 4a from the voltage application terminal 3a via the reference potential signal line R and the so wiring 4g. As described above, the differential amplifier circuit 4a reduces the low level potential of the two inputs (that is, the input to the node so and the node se) to the ground potential and raises the high level potential to the power supply potential. Thus, the subtle level difference between the two inputs is increased to facilitate the determination of the level of the two inputs. However, the differential amplifier circuit 4a malfunctions due to a difference in capacitance between wirings electrically connected to the nodes se and so of the differential amplifier circuit 4a (that is, electrical capacitance or wiring capacitance). An error may occur in the determination. Alternatively, when some electrical noise is generated in the wiring electrically connected to the nodes se and so of the differential amplifier circuit 4a, the differential amplifier circuit 4a malfunctions due to the difference in influence of noise on both wirings. There is also a risk.

  Next, the malfunction of the above-described differential amplifier circuit will be described with reference to FIGS. FIG. 8 is a timing chart for explaining a malfunction of the differential amplifier circuit.

  FIG. 8 shows the precharge control signal PCG1, the equalize control signal EQ supplied to the control terminal 3be, the scanning signal G1 supplied to the scanning line G1, the potential of the node so, and the potential of the node se.

  3 and 8, before supplying the signal potential from the pixel portion 2a to the node se of the differential amplifier circuit 4a, the precharge voltage is applied to the se wiring 4g and the so wiring 4f and the data line S which are inspection wirings. At the same time, the nodes se and so are set to the same potential. At this time, the precharge voltage is supplied from the power supply control terminal 3a via the reference potential signal line R and the transistors 3ce and 3co. For this precharge and equalization processing, HIGH precharge control signals PCG1 and PCG2 are applied to the gates of the transistors 3ce and 3co, respectively, and a HIGH equalize control signal EQ is applied to the gate of the transistor 8a.

  Immediately before the signal potential from the pixel unit 2a is supplied to the node se of the differential amplifier circuit 4a, the precharge control signal PCG1 and the equalize control signal EQ are switched from HIGH to LOW in order to stop the precharge and equalize processing ( (See FIG. 8). Along with the switching from HIGH to LOW, the parasitic capacitances of the transistors 3ce and 8a cause push-down (that is, potential fluctuation or voltage drop due to field through) at the nodes so and se.

  At the time of inspection of the pixel portion 2a, the transistors 60s and 3co are on, and the transistors 8a and 3ce are off. That is, the se wiring 4g and the data line S are electrically connected to the node se of the differential amplifier circuit 4a. On the other hand, the so wiring 4f and the reference potential signal line R are electrically connected to the node so of the differential amplifier circuit 4a.

  Temporarily, at the time of inspection, the wiring capacitance of the wiring electrically connected to the node se (for example, the se wiring 4f and the data line S) is the wiring electrically connected to the node so (for example, the so wiring 4g and the reference line). When the wiring capacity of the signal line R) is sufficiently large, as shown in FIG. 8, the pushdown generated at the node se at the timing when the precharge control signal PCG1 and the equalize control signal EQ are switched from HIGH to LOW. While the push-down amount Δ1 in FIG. 8 is relatively small, there is a high possibility that a relatively large push-down (see push-down amount Δ2 in FIG. 8) occurs in the node so.

  When HIGH is supplied to the scanning line G1 and the signal of the pixel portion 2a is transferred to the node se, the potential of the node se changes according to the potential written in the pixel portion 2a. In FIG. 8, when HIGH is written in the pixel portion 2a, the potential of the node se slightly increases (see the solid line portion indicating the potential of the node se in FIG. 8). On the other hand, when LOW is written in the pixel portion 2a, the potential of the node se slightly decreases (see a one-dot chain line indicating the potential of the node se in FIG. 8). The differential amplifier circuit 4a compares the potentials of the nodes so and se. As shown in FIG. 8, if the push-down of the node so is relatively large and the potential of the node so (ie, the reference) is lower than the potential of the node se when LOW is written in the pixel portion 2a, the differential In the amplifier circuit 4a, the node se always becomes the power supply voltage VDD regardless of the signal level written in the pixel portion 2a. For this reason, the quality of the pixel unit 2a cannot be determined.

  Alternatively, at the time of inspection, a wiring electrically connected to the node se (for example, the se wiring 4f and the data line S) is a wiring electrically connected to the node so (for example, the so wiring 4g and the reference signal line). For example, when the image display region 10a is more susceptible to electrical noise than R), the potential of the node se and the potential of the node so That is, there is a high possibility that the height relationship with the reference) is reversed and the determination of the quality of the pixel portion 2a is erroneous.

  Therefore, as shown in FIG. 3, in the present embodiment, the reference potential signal line R particularly has a portion wired along the direction in which the data line S extends. More specifically, as viewed in plan on the element substrate 10, it has a portion that is aligned with the data line S and wired from the node so to the opposite side of the image display area 10 a from the node so. ing. Since the reference potential signal line R is wired in this way, it is possible to prevent the differential amplifier circuit 4a from malfunctioning as described later.

  Since the liquid crystal device according to the present embodiment is configured as described above, before the element substrate 10 and the counter substrate 20 are bonded to each other and the liquid crystal is sealed in the manufacturing process, the electrical characteristics of the plurality of pixel units 2a. Can be evaluated or inspected. As a defect to be inspected for electrical characteristics, for example, a defect that the pixel unit 2a is fixed to LOW due to leakage of the additional capacitor Cs that is a data holding capacitor of each pixel unit 2a (hereinafter referred to as “LOW”). There is a defect in which the pixel portion 2a is fixed to HIGH due to leakage between the source and drain of the pixel switching transistor (hereinafter referred to as “HIGH fixing defect”).

  Next, the inspection and operation of the liquid crystal device according to the present embodiment will be described with reference to the drawings.

  Before describing the inspection of the pixel portion of the liquid crystal device in the manufacturing process, first, an operation when the liquid crystal device according to the present embodiment performs normal image display will be described with reference to FIG.

  In FIG. 3, first, in two video signal lines 7, odd-numbered and even-numbered image signals are respectively input to input terminals ine and ino of the video signal line 7. Each image signal is supplied to each data line S via a plurality of sampling switches 77 s constituting the sampling circuit 77 in accordance with a column selection signal (ie, output timing signal) from the X driver circuit 101. .

  The image signal supplied to each data line S is the pixel portion 2a (more specifically, the liquid crystal capacitance Clc and the additional capacitance Cs) in the row selected when the scanning line G from the Y driver circuit 104 becomes HIGH. Is written to. That is, in the selected scanning line G, the image signal supplied to the data line S is supplied and held as a display image signal in the corresponding pixel portion 2a. By performing this operation in, for example, row order, a desired image is displayed in the image display area 10a of the liquid crystal device.

  The precharge and reference circuit 13 applies a precharge voltage Vpre to each data line S before the scanning line G becomes HIGH. The precharge voltage Vpre is supplied to the voltage application terminal 3 a of the precharge and reference circuit 13. The timing for supplying the precharge voltage Vpre is determined by precharge control signals PCG1 and PCG2 applied to the control terminals 3b1 and 3b2.

  When an image is displayed as a liquid crystal device as a product or a prototype, the display data reading circuit 4 does not operate and is not used.

  Next, the inspection procedure of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 9 is a block diagram of the inspection system. FIG. 10 is a flowchart showing an example of the entire flow of inspection. FIG. 11 is a timing chart for explaining the read operation in step ST2 of FIG. FIG. 12 is an explanatory diagram showing a writing state of each pixel portion at the time of inspection.

  As shown in FIG. 9, the liquid crystal device 1 at the time of inspection (that is, the element substrate 10 on which the plurality of pixel portions 2a and the above-described various circuits are formed before being bonded to the counter substrate 20), and pixel data A test device 15 capable of writing and reading is electrically connected via a connection cable 16. The connection cable 16 includes the terminals ino and ine of the video signal line 7 of the liquid crystal device 1, the terminals 4 b and 4 d of the signal line of the display data reading circuit 4, the terminals 3 a and 3 b of the precharge and reference circuit 13, etc. Electrical connection is made (see FIG. 3).

  By supplying a predetermined voltage from the test device 15 to each terminal in a predetermined order to be described later, the electrical characteristics of the plurality of pixel portions 2a can be inspected. Below, the procedure for inspecting whether or not there is a LOW fixed defect among the above-described defects will be described as the contents of the inspection.

  As shown in FIG. 10, first, by a writing process, a predetermined pixel signal (or pixel data) is input from the input terminals ino and ine of the video signal line 7 to each pixel unit 2a which is a cell (step ST1). . The inspection of the pixel portion 2a is performed by determining whether or not the pixel portion 2a in the column to be inspected is normal with respect to the pixel portion 2a in the reference column. Each timing signal shown in FIG. 11 is generated by the test apparatus 15 and supplied to each terminal.

  Particularly in the present embodiment, the reference is supplied from the outside, and it is not necessary to write the reference to the pixel unit 2a. Each pixel portion 2a is written for inspection. That is, for example, in the case of inspecting a LOW fixing defect, as shown in FIG. 12, all the scanning lines G are turned on and HIGH is written in all the pixel portions 2a. FIG. 12 shows that the pixel signal written to each pixel unit 2a of n rows × m columns is HIGH (indicated by “H” in FIG. 12).

  In addition, when LOW is written in each pixel portion 2a, it is possible to inspect a HIGH fixing defect. Hereinafter, an example will be described in which HIGH is written in all the pixel portions 2a and a plurality of pixel portions 2a are inspected, but only a part of the pixel portions may be inspected. After the image signal is written, the gate of the scanning line G is turned off.

  At this time, the drive signal SAp-ch is the power supply potential VDD, the drive signal SAn-ch is the ground potential, and each differential amplifier circuit 4a of the display data read circuit 4 is in a non-operating state.

  Next, as shown in FIG. 10, pixel signals are read out by a reading process (step ST2). By supplying a high connection control signal TE (see FIG. 11) to the connection control terminal 9b, each transistor 60s of the transmission gate 60 is turned on. Thereby, the transistor 60s is turned on, and the data lines S1, S2,..., Sm and each of the so wirings 4g are electrically connected. Thus, the written pixel signal is read for each row and supplied to the display data reading circuit 4.

  Immediately before reading out such pixel signals, precharge and equalization processing are performed. That is, after the above-described predetermined pixel signal is written to all the pixel portions 2a, first, the precharge control signals PCG1 and PCG2 supplied to the terminals 3be and 3bo of the precharge and reference circuit 13 become HIGH.

  As shown in FIG. 11, in order to secure the data holding time, the precharge control signals PCG1 and PCG2 supplied to the terminals 3be and 3bo of the precharge and reference circuit 13, respectively, are HIGH only for the data holding time t1. Become.

  As a result, the precharge voltage Vpre supplied from the voltage application terminal 3a via the reference potential signal line R is applied to the se wiring 4f and each source wiring S via the transistor 3ce, and the so wiring 4g via the transistor 3co. To be applied. In the so wiring 4g, when the differential amplifier circuit 4a operates, the precharge voltage Vpre functions as a reference voltage. For example, an intermediate potential is selected as the precharge voltage Vpre.

  The precharge voltage Vpre of each data line S is set to an intermediate potential between HIGH and LOW, and the common fixed potential CsCOM (see FIG. 4) is set to the LOW potential. The common fixed potential CsCOM is set to the LOW potential because when the additional capacitor Cs, which is a data holding capacitor, has a leakage failure, the common fixed potential CsCOM at the leak destination becomes the LOW potential. This is to make it lower. Then, a slightly long time is set for the first precharge period so that a voltage change due to a leak failure appears.

  Further, as shown in FIG. 11, when the precharge voltage Vpre and the reference are applied, the HIGH equalize control signal EQ is also supplied to the control terminal 8b, the transistor 8a of the equalize circuit 8 is also turned on, and the so wiring The 4g and se wiring 4f have the same potential. Thereby, at this time, the nodes so and se of each data line S and the differential amplifier circuit 4a are in an intermediate potential state.

  Next, immediately before reading out the pixel signal, the precharge control signal PCG1 and the equalize control signal EQ are set to LOW to stop the precharge and reference processing. At this time, the gates of the transistors 3ce and 8a change from HIGH to LOW to cause pushdown. Note that the precharge control signal PCG2 remains HIGH, and the transistor 3co remains on.

  As shown in FIG. 3, in the present embodiment, the reference potential signal line R has a portion wired along the direction in which the data line S extends. More specifically, as viewed in plan on the element substrate 10, it has a portion that is aligned with the data line S and wired from the node so to the opposite side of the image display area 10 a from the node so. ing. That is, the reference potential signal line R is wired alternately with the data line S in the image display area 10a. In other words, the reference potential signal line R is wired in parallel with the data line S in practically the same pattern as the data line S, that is, along the data line S when viewed in plan on the element substrate 10. Therefore, the difference in wiring capacitance between the data line S and the reference potential signal line R is almost or completely eliminated in practice. Thereby, the push-down amount of the node so (that is, the potential drop amount) and the push-down amount of the node se are almost or completely the same in practice. Note that the amount of potential drop at the nodes so and se due to pushdown is sufficiently small, and is not shown in FIG.

  Next, as shown in FIG. 11, after the data holding time t <b> 1 has elapsed, the scanning line G <b> 1 is set to HIGH and pixel signal readout is started. At this time, the drive signal SAp-ch is the power supply potential VDD, the drive signal SAn-ch is the ground potential, and each differential amplifier circuit 4a is not yet operated.

  When the scanning line G1 is set to HIGH, pixel signals are simultaneously output from the pixel units 2a connected to the scanning line G1. That is, the charges written and held in the pixel portion 2a (specifically, the additional capacitor Cs) move all at once to the corresponding data line S. When HIGH is written in each pixel portion 2a and the pixel portion 2a is normal, the potential of each data line S and se wiring 4f slightly increases as shown by the solid lines in FIG. If there is a leak in the additional capacitor Cs and the pixel signal of the pixel unit 2a changes to LOW, the potential of each data line S slightly drops as shown by the broken line in FIG. . On the other hand, as shown in FIG. 11, since the potential of the node so supplied with the reference is added with the wiring capacitance of the reference potential signal line R, the push-down amount is sufficiently small and remains almost the intermediate potential. .

  As shown in FIG. 11, after setting the scanning line G1 to HIGH, the connection control signal TE to the connection control terminal 9b is set to LOW, and the transistor 60s of the transmission gate 60 is turned off for a predetermined time t2. That is, at the predetermined time t2, the connection control signal TE, the precharge control signals PCG1, PCG2, and the equalize control signal EQ are all LOW, and the transistors 9a, 3ce, 3co, and 8a are all turned off. And se wiring 4f will be in a floating state. Therefore, the intermediate potential of the se wiring 4f and the slightly increased potential of the so wiring 4g are maintained in the se wiring 4f and the so wiring 4g, respectively, and are not affected by other wiring such as the data line S.

  As shown in FIG. 11, the drive signal SAn-ch is changed from LOW to HIGH at the same time as or before or after the connection control signal TE is changed to LOW, and the drive signal SAp-ch is changed from HIGH to LOW.

  When the pixel unit 2a is normal, the drive signal SAn-ch becomes HIGH, so that the ground potential is applied to the power supply node sn of the differential amplifier circuit 4a, and becomes a lower potential among the nodes se and so. The node so is lowered to the ground potential (see the solid line of the node so in FIG. 11). Further, when the drive signal SAp-ch becomes LOW, the power supply voltage VDD is applied to the power supply node sp of the differential amplifier circuit 4a, and the node se having a higher potential among the nodes se and so has the power supply voltage VDDD. (See the solid line of node se in FIG. 11).

  When a LOW fixing defect occurs in the pixel portion 2a, the drive signal SAn-ch becomes HIGH so that the ground potential is applied to the power supply node sn of the differential amplifier circuit 4a. The node se having a low potential is lowered to the ground potential (see the broken line of the node se in FIG. 11). Further, when the drive signal SAp-ch becomes LOW, the power supply voltage VDD is applied to the power supply node sp of the differential amplifier circuit 4a, and the node so that has a higher potential among the nodes se and so becomes the power supply voltage VDD. (See the broken line of node so in FIG. 11). That is, the level relationship between the potentials of the nodes so and se is opposite to the level relationship when the pixel portion 2a is normal.

  Next, as shown in FIG. 10 again, the determined potentials of the nodes se and so are compared (step ST3). That is, when the potentials of the nodes so and se are determined to be LOW or HIGH, the connection control signal TE is set to HIGH to turn on the transistor 60s of the transmission gate 60 in order to output the potential of the node so.

  The determined potential of the node se of the differential amplifier circuit 4a is supplied from the se wiring 4f to the corresponding data line S. The gates TG1 to TGm of each sampling switch 77s of the sampling circuit 77 are opened in order (that is, an output timing signal is supplied from the X driver circuit 101), and the pixel signal of each pixel unit 2a in the first row is supplied from the video signal line 7. Read in order and output to output nodes outo and oute.

  When the pixel signals of all the pixel portions electrically connected to the scanning line G1 are read, the scanning line G1 is changed from HIGH to LOW, the drive signal SAn-ch is changed from HIGH to LOW, and the drive signal SAp-ch is changed to LOW. To HIGH to stop the operation of the differential amplifier circuit 4a.

  Next, as shown in FIG. 11, the precharge control signal PCG1 and the equalize control signal EQ are set to HIGH to precharge all the data lines S. Note that the second and subsequent precharge times may not be as long as the first time. After this precharge operation (that is, after the precharge time has elapsed, after the precharge control signal PCG1 and the equalize control signal EQ are changed from HIGH to LOW), the potential of the second scanning line G2 is changed to HIGH. The transistor 30 of each pixel unit 2a in the second row is turned on. Thereafter, the readout operation described above is repeated for each scanning line G up to the pixel portion 2a electrically connected to the n-th scanning line Gn, and finally pixel signals are read from all the pixel portions 2a.

  The determined potentials of the nodes so and se are output to the test apparatus 15 from the output terminals outo and oute. The test device 15 compares the pixel signal read in the reading process with the pixel signal written in the writing process. As shown in FIG. 11, when the pixel portion 2a is normal, HIGH is output to the output terminals outo and oute (see the solid lines of the output terminals outo and oute in FIG. 11). On the other hand, when a LOW fixing defect has occurred in the pixel portion 2a, LOW is output (see the broken lines of the output terminals outo and oute in FIG. 11). Therefore, the test apparatus 15 can determine whether or not a LOW fixing defect has occurred in the pixel portion 2a to be inspected.

  Next, as shown in FIG. 10, the test apparatus 15 identifies a pixel unit 2 a (or also referred to as “cell”) whose pixel signal read from the pixel unit 2 a to be inspected is not HIGH, and detects an abnormal pixel unit (or abnormal pixel unit). For example, a predetermined pixel unit number (or cell number) corresponding to each pixel unit is output so as to be displayed on a monitor screen (not shown) (step ST4).

  In this way, each differential amplifier circuit 4a can determine the quality of each pixel unit 2a by comparing the reference potential (ie, intermediate potential) applied from the outside with the potential of each data line S. To do.

  It is obvious that the HIGH fixed defect can be inspected by setting the reference to an intermediate potential and writing LOW in the pixel portion 2a to be inspected.

  As described above, in the manufacturing process of the liquid crystal device, it is possible to determine or detect the quality of the plurality of pixel portions 2a before the element substrate 10 in which the plurality of pixel portions 2a and the like are formed is bonded to the counter substrate 20. Therefore, the yield can be reduced and the manufacturing period can be shortened, the number of defective products can be reduced, and the cost can be reduced. In particular, in the case of a prototype, it can be expected to shorten the development period and the development cost. In addition, since the quality of the pixel portion 2a can be detected before the element substrate 10 is bonded to the counter substrate 20, so-called repair is facilitated.

  Furthermore, as described above with reference to FIG. 3, in the present embodiment, the reference potential signal line R is electrically connected to the node so, and the reference potential is supplied from the power supply terminal 3a. That is, the reference potential is supplied to the node so from the external test apparatus 15 (see FIG. 9) via the reference potential signal line R. Therefore, since the reference potential can be stably supplied from the outside, the quality of the pixel portion 2a can be reliably determined. That is, a defect in the pixel portion can be detected as a defect for each pixel portion. Furthermore, it is possible to electrically detect what kind of trouble occurs in which part of the transistor 30 or the additional capacitor Cs included in each pixel portion 2a.

  Further, as shown in FIG. 3, in the present embodiment, the reference potential signal line R is wired along the direction in which the data line S extends. Specifically, when viewed in plan on the element substrate 10, the data lines S are arranged side by side and wired from the node so to the node so so as to be opposite to the image display region 10a. That is, the reference potential signal line R is wired alternately with the data line S in the image display region 10a (that is, the reference potential signal line R1, the data line S1, the reference potential signal line from the left side in FIG. 3). R2, the data line S2,..., The reference potential signal line Rm, and the data line Sm are arranged in this order and are arranged almost in parallel). The reference potential signal line R may partially or completely overlap the data line S when viewed in plan on the element substrate 10, or may be wired side by side. For example, the length and width of the reference potential signal line R and the data line S are preferably equal. Therefore, the difference in wiring capacitance between the data line S and the reference potential signal line R can be eliminated almost or preferably completely. Furthermore, when some electrical noise is generated in the image display area 10a, both the data line S and the reference potential signal line R are affected by almost the same noise, so that the differential amplifying circuit 4a causes the node so. It is possible to prevent the level relationship between the supplied reference potential and the potential of the potential signal supplied to the node se from being reversed due to the influence of noise. Accordingly, it is possible to prevent the differential amplifier circuit 4a from malfunctioning and to obtain an accurate comparison result.

  As described above, according to the liquid crystal device according to the present embodiment, it is possible to detect a defect of the pixel unit 2a as a defect for each pixel unit. Furthermore, it is possible to electrically detect what kind of trouble occurs in which part of the transistor 30 or the additional capacitor Cs included in each pixel portion 2a. In addition, the quality of the pixel portion 2a can be determined with little or no influence from the difference in wiring capacitance between the data line S and the reference potential signal line R or the noise in the image display area 10a.

  Next, a specific configuration of the pixel portion will be described with reference to FIGS. FIG. 13 and FIG. 14 are plan views showing a partial configuration related to the pixel portion on the element substrate, which respectively correspond to a lower layer portion (FIG. 13) and an upper layer portion (FIG. 14) in a laminated structure described later. . FIG. 15 is a cross-sectional view taken along line AA ′ when FIGS. 13 and 14 are overlapped. In FIG. 15, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.

  13 to 15, each circuit element of the pixel portion 2 a described above with reference to FIGS. 3 and 4 is structured on the element substrate 10 as a patterned conductive film. The element substrate 10 is made of, for example, a single crystal silicon substrate, and is disposed so as to face the counter substrate 20 made of at least a glass substrate or a quartz substrate, for example. Each circuit element includes, in order from the bottom, the first layer including the transistor 30 and the additional capacitor Cs, the second layer including the data line S, the relay layer 600, the capacitor wiring 400, the relay layer 610, the light shielding film 710, and the like. The third layer includes at least a fourth layer including the light shielding film 720 and the like, and a fifth layer including the pixel electrode 9a and the like. Further, a first interlayer insulating film 41 between the first layer and the second layer, a second interlayer insulating film 42 between the second layer and the third layer, a third interlayer insulating film 43 between the third layer and the fourth layer, A fourth interlayer insulating film 44 is provided between the fourth layer and the fifth layer to prevent a short circuit between the above-described elements. Of these, the first to second layers are shown in FIG. 13 as lower layer portions, and the third to fifth layers are shown in FIG. 14 as upper layer portions.

(Structure of the first layer-transistor 30 and additional capacitor Cs etc.)
The first layer includes the transistor 30 and the additional capacitor Cs.

  The transistor 30 includes an insulating film 2 including a gate electrode 30a, a semiconductor layer 1a, and a gate insulating film that insulates the gate electrode 30a from the semiconductor layer 1a. As shown in FIG. 13, the gate electrode 30a is formed to extend from the scanning line G extending along the X direction, and is made of, for example, conductive polysilicon. The gate electrode 30a (that is, the scanning line G) is made of refractory metal such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), and molybdenum (Mo) in addition to conductive polysilicon. It can be formed of a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate thereof including at least one of the above. The semiconductor layer 1a is formed by implanting impurity ions such as boron (B) and phosphorus (P) into an element substrate 10 made of at least silicon (Si) and diffusing it at a high temperature (see FIG. 13). The semiconductor layer 1a includes at least a channel region 1a ′, a source region 1d, and a drain region 1e. That is, a source region and a drain region are formed in a self-aligned manner by implanting impurities at a high concentration using the gate electrode 30a as a mask. Yes. The transistor 30 may have an LDD (Lightly Doped Drain) structure.

  The additional capacitor Cs includes a lower electrode 71, a dielectric film 75, and a capacitor electrode 300. Similar to the semiconductor layer 1a, the lower electrode 71 is formed by implanting impurity ions on the element substrate 10 and diffusing it at a high temperature. That is, the lower electrode 71 and the semiconductor layer 1a are formed so as to be separated by implanting impurity ions into regions where the additional capacitor Cs and the transistor 30 on the element substrate 10 are to be formed on the same occasion. (See FIG. 13). The dielectric film 75 is the same film as the insulating film 2 including the gate insulating film described above. Since the liquid crystal device according to the present embodiment is a reflective liquid crystal device, the dielectric film 75 (that is, the insulating film 2) does not need to consider the transmittance, and has a high dielectric constant such as a silicon nitride film. Alternatively, a single layer film or a multilayer film such as hafnium oxide (HfO 2), alumina (Al 2 O 3), or tantalum oxide (Ta 2 O 5) may be used. The capacitor electrode 300 is formed of the same film as the gate electrode 30a described above, that is, for example, conductive polysilicon.

(Configuration of the second layer—data line S, relay layer 600, capacitor wiring 400, etc.)
The second layer is composed of the data line S, the relay layer 600, and the capacitor wiring 400.

  The data line S is formed from a metal film such as aluminum. The data line S may be formed as a three-layer film of aluminum, titanium nitride, and silicon nitride, for example, in order from the bottom. The data line S is formed so as to have a portion overlapping the source region 1d of the transistor 30 along the Y direction in FIG. 13 when viewed in plan on the element substrate 10, and includes the first interlayer insulating film 41 and It is electrically connected to the source region 1 d of the transistor 30 through a contact hole 81 that penetrates the insulating film 2.

  The relay layer 600 and the capacitor wiring 400 are formed as the same film as the data line S. The relay layer 600, the capacitor wiring 400, and the data line S are formed so as to be separated from each other as shown in FIG. The relay layer 600 is electrically connected to the drain region 1 e of the transistor 30 through a contact hole 82 that penetrates the first interlayer insulating film 41 and the insulating film 2. Further, the relay layer 600 is electrically connected to the capacitor electrode 300 through a contact hole 83 opened in the first interlayer insulating film 41. On the other hand, the capacitor wiring 400 is electrically connected to the extending portion of the lower electrode 71 through a contact hole 84 that penetrates the first interlayer insulating film 41 and the dielectric film 75 (that is, the insulating film 2).

  The first interlayer insulating film 41 is made of, for example, NSG (non-silicate glass). In addition, for the first interlayer insulating film 41, silicate glass such as PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride, silicon oxide, or the like can be used. The surface of the first interlayer insulating film 41 is subjected to a planarization process such as a chemical polishing process (CMP), a polishing process, a spin coat process, or a recess embedding process.

(Structure of the third layer-relay layer 610, light shielding film 710, etc.)
The third layer includes a relay layer 610 and a light shielding film 710.

  The relay layer 610 is formed from a metal film such as aluminum. The relay layer 610 is electrically connected to the relay layer 600 through a contact hole 85 opened in the second interlayer insulating film 42.

  The light shielding film 710 is formed of the same film as the relay layer 610. As shown in FIG. 14, the light shielding film 710 is formed in the entire region of the pixel portion 2 a excluding the region including the relay layer 610 when viewed in plan on the element substrate 10. That is, the light shielding film 710 and the relay layer 610 are formed in almost the entire region of the pixel portion so that the light shielding film 710 and the light shielding film 710 surround the relay layer 610. The light shielding film 710 is provided to prevent the occurrence of light leakage current in the transistor 30.

  The second interlayer insulating film 42 is made of, for example, NSG. In addition, for the second interlayer insulating film 42, silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like can be used. Similar to the first interlayer insulating film 41, the surface of the second interlayer insulating film 42 is subjected to a planarization process such as CMP.

(Structure of the fourth layer—light shielding film 720, etc.)
The fourth layer is composed of a light shielding film 720. The light shielding film 720 is made of at least titanium or the like, for example. As shown in FIG. 14, the light shielding film 720 is formed in the entire region of the pixel portion 2a except for a region where a contact hole 86 to be described later is formed as viewed in plan on the element substrate 10. In other words, the light shielding film 720 is formed in almost the entire region of the pixel portion so as to surround the contact hole 86 when viewed in plan on the element substrate 10. Note that the light shielding film 720 is provided in order to prevent the occurrence of light leakage current in the transistor 30, similarly to the light shielding film 710.

  The third interlayer insulating film 43 is made of, for example, NSG. In addition, the third interlayer insulating film 43 can be made of silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like. Similar to the first interlayer insulating film 41, the surface of the third interlayer insulating film 43 is subjected to a planarization process such as CMP.

(Fifth layer configuration-pixel electrode 9a, etc.)
The fifth layer is composed of pixel electrodes 9a. The pixel electrode 9a is made of, for example, aluminum or the like, and reflects incident light from above in FIG. As shown in FIG. 14, the pixel electrode 9 a is formed in almost the entire region of the pixel portion 2 a when viewed in plan on the element substrate 10. Note that the pixel electrode 9a is not formed near the edge of the pixel portion 2a so that the pixel electrodes 9a in the adjacent pixel portions 2a are not electrically short-circuited with each other. The pixel electrode 9 a is electrically connected to the relay layer 610 through a contact hole 86 that penetrates the third interlayer insulating film 43 and the fourth interlayer insulating film 44.

  The fourth interlayer insulating film 44 is made of NSG, for example. In addition, for the fourth interlayer insulating film 44, silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like can be used. Similar to the first interlayer insulating film 41, the surface of the fourth interlayer insulating film 44 is subjected to a planarization process such as CMP.

  As described above, the pixel electrode 9a, the relay layer 610, the relay layer 610 and the relay layer 600, and the relay layer 600 and the drain region 1e of the transistor 30 are connected via the contact holes 86, 85, and 82, respectively. Electrically connected. That is, the pixel electrode 9a and the drain region 1e of the transistor 30 are relay-connected through the relay layer 610 and the relay layer 600.

  An alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a.

  The above is the configuration of the pixel portion on the element substrate 10 side.

  On the other hand, the counter substrate 20 is provided with a counter electrode 21 on the entire surface of the counter substrate 20, and an alignment film 22 is further provided thereon (under the counter electrode 21 in FIG. 15). The counter electrode 21 is made of at least a transparent conductive film such as an ITO film.

  A liquid crystal layer 50 is provided between the element substrate 10 and the counter substrate 20 thus configured. The liquid crystal layer 50 is formed by sealing liquid crystal in a space formed by sealing the peripheral portions of the element substrate 10 and the counter substrate 20 with a sealing material. The liquid crystal layer 50 takes a predetermined alignment state by the alignment film 16 and the alignment film 22 that have been subjected to an alignment process such as a rubbing process in a state where an electric field is not applied between the pixel electrode 9 a and the counter electrode 21. It is like that.

  The configuration of the pixel unit 2a described above is common to each pixel unit. Such pixel portions 2a are periodically formed in the image display region 10a (see FIG. 1).

  Next, a specific configuration of the reference potential signal wiring will be described with reference to FIGS.

  As shown in FIG. 15, the reference potential signal wiring R described above with reference to FIG. 3 is formed of the same film as the data line S, the relay layer 600, and the capacitor wiring 400. Further, as shown in FIG. 13, the reference potential signal line R is wired almost in parallel with the data line S (that is, along the Y direction). Further, the width and thickness of the reference potential signal line R are formed almost equal to the width and thickness of the data line S, respectively. As described above, the length of the reference potential signal wiring R is also almost equal to the length of the data line S. That is, it is formed so that there is almost no difference in wiring capacitance between the data line S and the reference potential signal line R. Therefore, as described above, it is possible to prevent the differential amplifier circuit 4a from malfunctioning and to obtain an accurate comparison result.

Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 16 is a block diagram having the same concept as in FIG. 3 in the second embodiment. In FIG. 16, the same components as those in the first embodiment shown in FIGS. 1 to 15 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  In FIG. 16, in this embodiment, in particular, a logic circuit 700 that outputs a logical sum of a potential signal supplied to the pixel portion 2a and a potential signal supplied to the reference potential signal line R to the data line S is provided. Other configurations are almost the same as those of the liquid crystal device according to the first embodiment. That is, the input terminal of the logic circuit 700 is electrically connected to the drain of the sampling switch 77 s and the reference potential signal line R, and the output terminal of the logic circuit 700 is electrically connected to the data line S. . When the potential signal is supplied to either the drain of the sampling switch 77s or the reference potential signal line R, the potential signal is supplied to the data line S. Therefore, at the time of inspection, for example, after a potential signal is written in advance in the pixel portion 2a, the reference potential signal line R and the data line S can be precharged via the reference potential signal line R. Further, at the time of normal display, the data line S can be precharged by a potential signal from the voltage application terminal 3a in the blanking period. That is, the reference potential signal line R serves as a precharge supply line for supplying a reference potential to the differential amplifier circuit 4a at the time of inspection and precharging the reference potential signal line R or the data line S at the time of inspection and normal display. Can function.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.
First, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 17 is a perspective view showing the configuration of this personal computer. In FIG. 17, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a front light to the front surface of the reflective liquid crystal device 1005.

  Next, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 18 is a perspective view showing the configuration of this mobile phone. In FIG. 18, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 17 and 18, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention includes a plasma display (PDP), a field emission display (FED, SED), an organic EL display, a digital micromirror device (DMD), an electrophoresis device, and the like. It is also applicable to.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change, In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

1 is a plan view showing an overall configuration of a liquid crystal device according to a first embodiment. Sectional drawing of HH 'of FIG. 1 is a block diagram showing a main circuit configuration of a liquid crystal device according to a first embodiment. FIG. 3 is a circuit diagram illustrating an electrical configuration of a pixel portion. The circuit diagram which shows the electric constitution of a differential amplifier circuit. The circuit diagram which shows the electrical constitution of a pull-up circuit. The circuit diagram which shows the electrical constitution of a pull-down circuit. 6 is a timing chart for explaining a malfunction of the differential amplifier circuit. The block diagram of an inspection system. The flowchart which shows the example of the whole flow of a test | inspection. FIG. 11 is a timing chart for explaining a read operation in step ST2 of FIG. Explanatory drawing which shows the writing state of each pixel part at the time of a test | inspection. It is a top view showing the partial structure concerning the pixel part on an element substrate, and is a figure equivalent to a lower layer part among laminated structures. It is a top view showing the partial structure concerning the pixel part on an element substrate, and is a figure equivalent to an upper layer part among laminated structures. FIG. 15 is a cross-sectional view taken along line AA ′ when FIG. 13 and FIG. 14 are overlapped. The block diagram of the same meaning as FIG. 3 in 2nd Embodiment. The perspective view which shows the structure of the personal computer which is an example of the electronic device to which the electro-optical apparatus is applied. The perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  2a ... Pixel unit, 4a ... Differential amplifier circuit, 7 ... Image signal line, 8 ... Equalize circuit, 9a ... Pixel electrode, 77 ... Sampling circuit, 10 ... Element substrate, 10a ... Image display area, 13 ... Precharge and reference Circuit: 20 ... Counter substrate, 60 ... Transmission gate, 71 ... Lower electrode, 75 ... Dielectric film, 101 ... X driver circuit, 104 ... Y driver circuit, 300 ... Capacitance electrode, Cs ... Additional capacitance, G ... Scanning line, S ... data line, R ... reference potential signal line, so, se ... node.

Claims (4)

On the board
A plurality of scan lines and a plurality of data lines intersecting each other;
A plurality of pixel portions arranged in a matrix corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
The first and second nodes are provided, and the potential signal supplied to the first node is compared with the potential signal supplied to the second node, and the potential signal is supplied to the first node. When the potential signal is low, the potential of the first node is lowered, and when the potential signal supplied to the first node is high, the potential of the first node is raised and output. An amplifier;
A reference potential signal line for supplying a reference potential to the first node, the portion being electrically connected to the first node and having a portion wired along a direction in which the data line extends; ,
An electro-optical device comprising: supply means for reading out and supplying a potential signal input to the pixel portion to the second node. Each of the plurality of pixel portions includes a reflective or transflective pixel electrode,
The reference potential signal line is wired to be lower than the pixel electrode via an interlayer insulating film and to overlap the pixel electrode when viewed in plan on the substrate. The electro-optical device according to claim 1. A logic circuit that is electrically connected to the reference potential signal line and the data line and outputs a logical sum of a potential signal supplied to the pixel portion and a potential signal supplied to the reference potential signal line to the data line. With
3. The electro-optical device according to claim 1, wherein a precharge signal for precharging the reference potential signal line and the data line is supplied to the reference potential signal line.   An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 3.

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