JP2006228312A - Shift register and liquid crystal drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shift register in which output of a needless drive pulse can be prevented by suppressing variation of gate voltage of an output transistor using reducing output impedance by bootstrap operation and a liquid crystal driver using this shift register. <P>SOLUTION: The shift register has a plurality of stages connected in cascade and in which input data is shifted and shift operation of the input data is performed, each stage has a first diode connected to a gate of the output transistor and inputting the input data, a capacitor connected between the gate and a source of the output transistor, and a clamping transistor connected between the gate and the source of the output transistor in parallel to the capacitor, wherein a source of the clamping transistor is connected to the source of the output transistor, a drain of the clamping transistor is connected to the gate of the output transistor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a shift register that is provided in a liquid crystal display device such as a liquid crystal display and supplies a scanning drive signal, and a liquid crystal drive circuit using the shift register.

For example, in an active matrix liquid crystal display device used for a computer display device and a television, video signal lines (column wirings) and scanning drive signal lines (row wirings) are provided in a matrix. A switching element such as a thin film transistor for driving the liquid crystal of each pixel is provided at the intersection of the wirings.
Then, a scanning drive signal that sequentially scans these signal lines and temporarily turns on all the switching elements on one scanning drive signal line is given to the plurality of scanning drive signal lines, and the video signal A video signal is supplied to the line in synchronization with the scanning drive signal line.
Here, a shift register performs an operation of sequentially supplying a plurality of scanning drive signal lines.

As shown in FIG. 7, in the display portion, a plurality of row wirings and column wirings are provided on the matrix, and switching elements (transistors) that control voltage application to the liquid crystal at intersections of the row wirings and column wirings. And an active matrix circuit in which a liquid crystal element composed of a liquid crystal unit to be controlled is arranged.
The gate driver (shift register) applies a predetermined voltage to the row wiring (scanning line) in time series to turn it on, and the column wiring driver applies a predetermined voltage to the source in synchronization with this timing (via the signal line). Application), the liquid crystal display device is driven by changing the optical state of the liquid crystal.

In order to drive the liquid crystal element, in FIG. 7, a gate driver is manufactured using a thin film transistor (see, for example, Patent Document 1).
At this time, it is necessary to operate a gate driver that applies a voltage to the row wiring at high speed and to supply a sufficient amount of current to the row wiring.
Here, as shown in FIG. 8, the gate driver is composed of a shift register having a plurality of SR (shift register) stages.

Each SR stage has the configuration shown in FIG. 9, and the SR stages are cascade-connected as shown in FIG. 8, and each SR stage sequentially applies a voltage as a drive pulse to the column wiring, and the liquid crystal element It functions as a gate driver that applies a predetermined voltage to the gate of the thin film transistor.
In each SR stage, the driving pulse of the subsequent stage is applied to the gate of the clamping transistor 25, whereby the gate voltage (node P) of the output transistor 16 is lowered to the ground level, and the output transistor 16 is turned off. That is, it is reset to a standby state where no drive pulse is output.

Here, in the waveform diagram showing the drive waveform in FIG. 10, the output transistor 16 is sufficiently turned on (state in which the on-resistance is sufficiently low) before and after the drive pulse (phase shift clock) is output to the node P1 in FIG. The shift register is designed so that a gate voltage Vgs (gate-source voltage) is applied.
In FIG. 10, the horizontal axis indicates the time, and the vertical axis indicates the waveform level.
Japanese Patent Laid-Open No. 08-87897

In the transition process to the standby state of each stage described above, the clamping transistor 25 is turned on by the drive pulse output from the subsequent stage. Therefore, the clamping transistor 25 is turned on only when a pulse is applied to the gate. In contrast, stress is applied, and application of surplus stress is reduced.
However, each SR stage is in a floating state in which the subsequent stage is in a standby state and the clamping transistor 25 is off and the node P is not clamped to a predetermined voltage, and the voltage at the node P fluctuates due to noise. An unstable state occurs.

That is, in the output transistor 16, the clock C1 is input to the drain electrode wiring 14 at a predetermined timing. When the clamping transistor 25 is in the OFF state, the voltage at the node P varies when the clock C1 is input. It will be.
Then, the output transistor 16 outputs a noisy drive pulse to drive the display device at a timing when the output transistor 16 itself is limited in output of the drive pulse due to the voltage fluctuation of the node P, as shown in FIG. End up.
As can be seen from FIG. 11 (simulation result), the pull-down transistor 17 can remove the DC component of the noisy driving pulse at the node 13 (output wiring) to some extent. The potential fluctuation cannot be completely removed.
In FIG. 11, the upper part shows the input waveform of the clock C1, the lower part shows the waveform of the drive pulse OUTn at the output terminal, the horizontal axis is time, and the vertical axis is the potential of the output waveform.

Therefore, even if the operation as a shift register is normal, an unnecessary display element of the display device is driven and the contrast of the display image is lowered. Therefore, it is used as a gate driver applied to the scanning circuit of the display device. Is not preferred.
Further, when the pull-down transistor 17 is deteriorated with the passage of time, the pull-down resistance is increased, and the DC component of noise at the node 13 cannot be suppressed.
As a result, the shift register does not have a function as a scanning circuit of the display device, and the display process in the display device cannot be normally performed.

In the configuration of the shift register described above, it is desirable that the node P is always pulled down to the ground level in order to prevent the output transistor 16 from malfunctioning due to voltage fluctuations at the node P and outputting unnecessary drive pulses.
However, in the configuration in which the node P is always grounded, an intermediate circuit that pulls down the node P is used, and it is necessary to provide a complicated compensation circuit so that excessive stress is not applied to the transistors that form the intermediate circuit. There is a problem that the circuit scale increases due to the wiring.

  The present invention has been made in view of such circumstances, and suppresses fluctuations in the gate voltage of the output transistor used by lowering the output impedance by bootstrap operation, thereby preventing the output of unnecessary drive pulses. It is an object of the present invention to provide a shift register that can be used and a liquid crystal driver using the shift register.

The shift register of the present invention has a plurality of cascaded stages, shifts input data by a plurality of clocks having different phases, and when the input data is input, a clock input to the drain of the output transistor, A shift register that outputs from a source as a phase shift clock and performs a shift operation of an output signal, and is connected to the gate of the output transistor in each stage, and a first diode that inputs the input data, and the output A capacitor connected between the gate and source of the transistor, and a clamping transistor connected in parallel with the capacitor between the gate and source of the output transistor, the source of the clamping transistor being the output transistor Connected to the source and the clamping traffic Drain of registers is connected to the gate of the output transistor.
As a result, in the shift register of the present invention, the clamping transistor clamps the gate of the output transistor to a predetermined potential, thereby suppressing potential fluctuation due to noise at the gate of the output transistor, and no output transistor is required. Malfunction that outputs a large driving pulse can be prevented.
In addition, since the shift register of the present invention suppresses potential fluctuation at the gate of the output transistor and does not require a control signal from another circuit including the output pulse of the subsequent stage, the circuit and wiring have a complicated configuration. In other words, the circuit scale is not increased.

In the shift register of the present invention, the clamping transistor is controlled to be in an off state during the stage drive period and to be in an on state during a period when the stage is not driven.
In the shift register of the present invention, an output voltage is applied to the gate of the clamping transistor during a stage drive period, and a voltage higher than the threshold voltage of the clamping transistor is applied during a stage drive period. It has a control circuit.
In the shift register of the present invention, the control circuit includes a second diode having an anode connected to the source of the clamping transistor, and a second capacitor interposed between the cathode of the second diode and a ground point. The cathode of the second diode is connected to the gate of the clamping transistor.
As a result, the shift register of the present invention applies a pulse-like stress only at the time of switching between driving and non-driving, and an unnecessary surplus with respect to the gates of the clamping transistor and additional transistors. There is no need to apply stress, and the overall reliability is improved.

The shift register of the present invention has a pull-down resistor interposed between the source of the output transistor and a ground point.
As a result, the shift register of the present invention can pull down the potential of the gate of the output transistor to the ground during a period when it is not driven by the pull-down transistor, so that potential fluctuation due to noise at the gate of the output transistor can be suppressed. Thus, it is possible to prevent a malfunction that the output transistor outputs an unnecessary drive pulse.

In the liquid crystal driving circuit of the present invention, the shift register having any one of the above structures is used to generate a scanning driving signal of an active matrix circuit in which scanning lines and signal lines intersect.
As a result, the liquid crystal driving circuit of the present invention can suppress the output of unnecessary driving pulses due to noise, so that the fluctuation level of the noisy driving pulses output to the display device can be reduced. It can be set to a range that does not affect the display quality on the liquid crystal display screen to the extent that the user does not feel.

  As described above, according to the present invention, the clamping transistor clamps the gate of the output transistor to a predetermined potential, so that the circuit and wiring are not complicated and the output is not increased. It is possible to suppress potential fluctuation due to noise at the gate of the transistor, and to prevent a malfunction in which the output transistor outputs an unnecessary drive pulse.

The present invention outputs a phase shift clock Gout (drive pulse), which is a scanning drive signal for driving a liquid crystal element, in a register cell, which is each stage of a shift register, formed of a-Si or the like on a substrate of a liquid crystal display device. The present invention relates to a technique for preventing malfunction due to noise of an output transistor.
That is, each stage of the shift register of the present invention is provided so that the clamping transistor suppresses the voltage fluctuation of the gate of the output transistor, and the clamping transistor sets the voltage of the gate of the output transistor during the period when the drive pulse is not output. The output transistor is held at a value lower than the threshold voltage.
Thus, each stage of the shift register of the present invention is controlled so that a voltage fluctuated due to noise is not applied to the gate of the output transistor, so that malfunction due to noise does not occur during a period in which no drive pulse is output. Do not output unnecessary drive pulses.

<First Embodiment>
Hereinafter, a shift register used as the gate driver (liquid crystal drive circuit) of FIG. 7 according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of the shift register according to the first embodiment.
In this figure, the shift register 100 has a structure in which a plurality of stages (register cells) 1, 2, 3, 4,... Are connected in cascade, and a plurality of phases input from an external clock generator, for example, 2 The input data is shifted by the phase clocks (CK1, CK2) and synchronized with the phase clock input to this stage at the stage to which the input data is input, and the phase shift clock is sequentially input from each stage to the terminal Mout1. , Mout2, Mout3, Mout4,.

Here, in each stage, when any one of the two-phase clocks is input in order of phase, and the input data to be sequentially shifted reaches itself, the output data (phase is synchronized with the input clock). Shift clock).
Stage 1 outputs the phase shift clock Gout1, Stage 2 outputs the phase shift clock Gout2, Stage 3 outputs the phase shift clock Gout3, and Stage 4 outputs the phase shift clock Gout4.

That is, in the shift register 100, the input data input by the start signal ST is sequentially shifted by the two-layer clock, and the stage to which the input data is input is connected in synchronization with the clock input to this stage. The phase shift clock is output as a drive signal to the liquid crystal element via the terminal Moutn.
Clock CK1 is input to stage 1, clock CK2 is input to stage 2, clock CK1 is input to stage 3, clock CK2 is input to stage 4,..., Clock m is input to stage n Is done. (M is the remainder of dividing n by “2” and is 2 when divisible.)

Next, the configuration of the stage n in the shift register of FIG. 1 will be described with reference to FIG. FIG. 2 is a conceptual diagram showing the circuit configuration of stage n (although the other stages also have different input signals, the configuration is the same as that of stage n).
The output transistor M1 has a gate connected to the drain of the transistor M2, a drain connected to the clock CKm, and a source connected to the terminal Moutm.

The diode D1 is an input circuit, and has an anode connected to the terminal In and a cathode connected to the gate of the output transistor M1 (connected at the connection point A).
The diode D1 may be a diode element or may be constituted by a transistor as shown in FIG. 2. In this case, a terminal connecting a gate and a drain is used as an anode, and a source is used as a cathode.
One end of the capacitor C1 is connected to the gate of the output transistor M1, and the other end is connected to the source of the output transistor M1.

The diode D2 has an anode connected to the source of the output transistor M1 and a cathode connected to one end (connection point B) of the capacitor C2.
As the diode D1, the diode D2 may be a diode element, or may be constituted by a transistor as shown in FIG. 2, and in this case, a terminal having a gate and a drain connected as an anode, Use the source as
The capacitor C2 has one end connected to the connection point B and the other end grounded, and is interposed between the output transistor M1 and the ground point (Vss) in series with the diode D2.

The transistor M2 is provided as a clamping transistor of the output transistor M1, the drain is connected to the gate of the output transistor M1, the source is connected to the source of the output transistor M1, and the gate is connected to the connection point B.
The transistor M3 has a drain connected to the gate of the transistor M2, a gate connected to the anode of the diode D1, and a source grounded.
The output transistors M1, M2 and M3 (and the transistors constituting the diodes D1, D2 and D3) are all n-channel FETs (field effect transistors).

Next, the operation of the shift register according to the first embodiment of the present invention will be described with reference to stage n with reference to FIG. FIG. 3 is a waveform diagram showing the operation of stage n in the shift register according to the first embodiment.
In stage n, the anode of diode D1 is connected to terminal Toutn-1 of stage n-1 of all stages. Here, for explanation, it is assumed that the clock CKm input to the drain of the output transistor M1 is CK2. Therefore, the clock CK1 is input to the drain of the output transistor M1 in the preceding stage n-1 and the succeeding stage n + 1.

At time t1, since the drive pulse Goutn-1 output from the stage n-1 is at "L" level, that is, the terminal In is at "L" level, the potential at the connection point A is at "L" level.
At this time, the output transistor M1 is off because the gate is at "L" level, and the clock CK2 having a predetermined pulse width is input to the drain, but the drive pulse Goutn is at "L" level.
As will be described in detail later, the connection point B is set to a predetermined control voltage by the control circuit including the diode D2 and the capacitor C2, and the transistor M2 is turned on.
For this reason, the connection point A becomes the potential of the source of the output transistor M1, that is, “L” by the transistor M2, and the output transistor M1 is in the OFF state.

Next, at time t2, since the drive pulse Goutn-1 output from the stage n-1 is at "H" level, that is, the terminal In is at "H" level, the potential at the connection point A transitions to "H" level. To do.
As a result, the transistor M3 is stored in the capacitor C2 because the "H" level is applied to the gate while the drive pulse Goutn-1 is at "H" level, that is, during the pulse width of the drive pulse Goutn-1. The discharged charge is discharged, and the connection point B is set to the “L” level.

On the other hand, when the shifted input data is “L” level, that is, the drive pulse Goutn−1 is “L” level, the capacitor C1 is not charged at the timing of the shift, and the output transistor M1 is in the OFF state. Therefore, the connection point B remains at the control voltage, and the transistor M2 is turned on.
Thus, even when the clock CKm is input, there is no voltage fluctuation at the output terminal Moutn, and no noise is output.

As a result, the transistor M2 is turned off, and the capacitor C1 is charged to a predetermined voltage. That is, the potential at the connection point B is controlled to be turned off at the timing when the capacitor C1 is charged to a predetermined voltage, thereby enabling the bootstrap of the gate voltage of the output transistor M1 by the capacitor C1.
The output transistor M1 is turned on because the “H” level is applied to the gate, but since the clock CK2 is not input to the drain, the output pulse Moutn can be output at the “H” level. Absent. Therefore, the output terminal Moutn is at the “L” level.

Next, at time t3, the output of the stage n-1 is turned off, but the capacitor C1 is charged with a predetermined voltage by the diode D1, that is, charged to a predetermined voltage.
Since the output transistor M1 is in the on state, the clock CK2 input to the drain is at the “H” level, so that a current flows and raises the source potential.
As a result, electric charge is supplied to one terminal of the capacitor C1 (terminal connected to the source of the output transistor M1) and the potential rises, and the other terminal of the capacitor C1 (terminal connected to the gate of the output transistor M1) In order to maintain the potential difference of the capacitor C1, the voltage rises by the same potential as one terminal of the capacitor C1 (bootstrap operation).

  That is, when the output transistor M1 is in the ON state and the clock CK2 is input at the “H” level, the voltage applied to the gate is boosted by the voltage level of the clock CK2 by the capacitor C1, and the output transistor M1 is turned on. As a result, the drive pulse Goutn (input data) having a voltage level and pulse width substantially the same as those of the clock CK2 is output to the next stage n + 1.

At this time, since the drive pulse Goutn-1 is at the “L” level, the transistor M3 is in an OFF state, current flows from the output transistor M1 to the capacitor C2 via the diode D2, and electric charge is accumulated in the capacitor C2. Thus, the capacitor C2 is charged to a predetermined voltage.
As a result, the transistor M2 is in a state where a voltage exceeding the threshold value is applied to the gate, but the gate and the source have substantially the same potential, and thus the transistor M2 is in an off state in which no current flows.

Next, when the clock CK2 becomes “L” level, the voltage of the source of the output transistor M1, that is, the potential of the output terminal Moutn, is caused to flow to the drain side by the output transistor M1 in the on state. Level.
The transistor M2 is turned on because the source voltage is at the "L" level while the gate voltage is at the "H" level, and the charge accumulated in the capacitor C1 is discharged through the output transistor M1. Thus, the potential at the connection point A is set to the “L” level.
At this time, although the potential of the capacitor C2 is lowered by the gate-source capacitance C3 of the transistor M2, the capacitance C2 and the capacitance C2 are set so that the voltage charged by the capacitor C2 becomes a control voltage higher than the threshold voltage of the transistor M2. The capacitance ratio of the capacitor C3 is set beforehand.
As a result, since the control voltage stored in the capacitor C2 is applied to the gate, the transistor M2 remains on.

Next, at time t4, the output transistor M1 is off because the node A is at "L" level, and the clock CK2 is also at "L" level, so that the drive pulse Goutn is at "H" level. There is no output.
At this time, the transistor M2 remains on because the control voltage stored in the capacitor C2 is applied to the gate.
For this reason, even if the noise tries to change the potential at the connection point A, the transistor M2 suppresses the increase in the potential at the connection point A due to the noise, so that the fluctuation of the gate voltage of the output transistor M1 is suppressed, and the output transistor M1 malfunctions. Can be prevented.

Next, at time t5, the output transistor M1 is in the OFF state because the gate voltage is at the “L” level.
At this time, the clock CK2 is set to the “H” level, but since the transformer M2 is in the on state, the drive pulse Goutn is output at the “H” level in noise in order to suppress the potential fluctuation at the connection point A. As a result, the output transistor M1 does not malfunction.

In addition, in order to discharge the electric charge accumulated in the capacitor C1, it is necessary to provide a grounded transistor for discharging and to turn on this transistor by a drive pulse (used as a reset signal) output from the subsequent stage. Therefore, wiring between stages can be reduced, a circuit mounting area can be reduced, and a circuit scale can be reduced.
Similarly, in order to clamp the gate voltage of the output transistor, there is no need to provide a grounded discharge transistor (pull-down transistor or clamping transistor) and control the gate voltage of this transistor. There is no need to provide a circuit for controlling the voltage, and the circuit configuration and wiring can be simplified.

A pull-down resistor may be inserted between the output terminal Moutn and the ground point. Thereby, in the circuit of the stage n in FIG. 2, since the output terminal Moutn is not pulled down, when the charge supplied by noise accumulates in the output wiring connected to the output terminal Moutn, the output terminal Moutn The potential increases gradually.
However, since electric charges are accumulated, the electric potential is a direct current component, and the increase of the electric potential can be easily suppressed by inserting a pull-down resistor between the output terminal Moutn and the ground point.

Furthermore, as described above, since only the DC component accumulated at the output terminal Moutn is removed, a pull-down resistor having a higher resistance than that of the conventional circuit may be used, and the parasitic resistance of the circuit may be sufficient. .
Corresponding to the simulation result of the conventional example (see FIG. 11), the other constants of the transistor and the capacitor other than the transistor M2 as the clamping transistor and the diode D2 and the capacitor C2 as the control circuit were similarly performed. The simulation result in the embodiment is shown in FIG.
In FIG. 4, the upper part shows the input waveform of the clock CKm, the lower part shows the waveform of the drive pulse Goutn at the output terminal Moutn, the horizontal axis is time, and the vertical axis is the potential of the output waveform. .

Compared to FIG. 11, it can be seen that there is no voltage fluctuation at the output terminal Goutn when the clock CKm is input.
Also, in the simulation, if the resistance of the first embodiment is higher than that of the pull-down resistor (transistor 17) set in the conventional example, for example, the conventional example is 1 M (mega) Ω, Operation was confirmed using a 100 MΩ resistor, but it was found that the potential fluctuation of the output wiring connected to the output terminal Moutn was suppressed to an extremely small level as shown in FIG.

Therefore, when the drive pulse Goutn is output at the “H” level, the voltage drop due to the connection of the pull-down resistor can be suppressed by increasing the resistance value of the pull-down resistor, and the driving capability of the output transistor M1 can be reduced. It is possible to reduce power consumption.
In addition, the above-described operation of the transistor M2 can be easily performed immediately after the power is turned on by applying a control voltage for turning on the transistor M2 to the connection point B to the capacitor C2 using the diode D3. It can be carried out.
The diode D3 is not necessarily provided, and is provided in a timely manner in response to the above-described case.

Furthermore, when the shift register according to the first embodiment is used for the gate driver of the liquid crystal display device shown in FIG. 5, a staggered configuration in which the shift registers are laid out on both sides in the column direction of the display unit may be desirable.
In this case, in the shift register, it is not necessary to wire the driving pulse of the next stage and subsequent stages as a reset signal.

<Second Embodiment>
Next, a second embodiment is shown in FIG. The second embodiment of the present invention can be used as the gate driver (liquid crystal driving circuit) in FIG. 7 as in the first embodiment. The gate driver configuration of FIG. 5 is the same as that of the first embodiment shown in FIG. 2 except that the anode of the diode D3 is not connected to the output terminal Moutn but is connected to the drain of the output transistor M1. It is the composition which is.
In this case, the capacitor C2 is repeatedly charged every time the clock CKm becomes “H” level, and holds a voltage value almost the same as the “H” level potential of the clock CKm.

For this reason, the voltage at the connection point B, that is, the gate voltage of the transistor M2, is almost the same as the “H” level potential of the clock CKm, as shown in FIG.
FIG. 6 shows the results of a simulation performed under the same conditions as in FIG. 4, with the horizontal axis representing time and the vertical axis representing the potential level of each waveform.
Therefore, as can be seen from the simulation results, in the second embodiment, similarly to the first embodiment, when the clock CKm is input to the drain of the output transistor M1 other than when the drive pulse Goutn is output, The output terminal Moutn does not generate noise as in the conventional example shown in FIG.

  The circuit configuration of the shift register according to the first and second embodiments described above is not limited to an a-Si (amorphous silicon) TFT (thin film transistor), but a gate driver for a polycrystalline silicon TFT or a driver IC for a single crystal silicon ( The present invention can also be applied to an integrated circuit.

It is a block diagram which shows the structural example of the shift register by the 1st and 2nd embodiment of this invention. It is a conceptual diagram which shows the structural example of the circuit of the stage n by 1st Embodiment in FIG. It is a wave form diagram which shows operation | movement of the shift register of FIG. FIG. 3 is a diagram illustrating a simulation result waveform in the shift register of FIG. 1 using the configuration of the stage n of FIG. 2. It is a conceptual diagram which shows the structural example of the circuit of the stage n by 2nd Embodiment in FIG. It is a figure which shows the waveform of the simulation result in the shift register using the structure of the stage n of FIG. It is a conceptual diagram which shows the structural example of a liquid crystal display device. It is a block diagram which shows the structure of the shift register by a prior art example. It is a conceptual diagram which shows the circuit structure of the stage which is each stage of FIG. FIG. 9 is a waveform diagram illustrating an operation example of the shift register of FIG. 8. It is a figure which shows the waveform of the simulation result in the shift register of FIG.

Explanation of symbols

1, 2, 3, 4, n ... stages A, B ... connection points C1, C2 ... capacitors D1, D2, D3 ... diodes M1 ... output transistors M2, M3 ... transistors Mout1, Mout2, Mout3, Mout4, Moutn ... terminals

Claims (6)

It has a plurality of cascaded stages, and input data is shifted by a plurality of clocks with different phases, and when the input data is input, the clock input to the drain of the output transistor is output from the source as a phase shift clock And a shift register that performs a shift operation of the output signal,
In each stage,
A first diode for inputting the input data, connected to a gate of the output transistor;
A capacitor connected between the gate and source of the output transistor;
A clamping transistor connected in parallel with the capacitor between the gate and source of the output transistor;
A shift register, wherein a source of the clamping transistor is connected to a source of the output transistor, and a drain of the clamping transistor is connected to a gate of the output transistor.   2. The shift register according to claim 1, wherein the clamping transistor is controlled to be in an off state during a period in which the stage is driven and to be in an on state during a period in which the stage is not driven.   And a control circuit that applies an output voltage to the gate of the clamping transistor during a period in which the stage is driven and applies a voltage higher than a threshold voltage of the clamping transistor in a period in which the stage is not driven. The shift register according to claim 2. The control circuit is
A second diode having an anode connected to a source of the clamping transistor;
A second capacitor interposed between the cathode of the second diode and the ground point,
4. The shift register according to claim 3, wherein the cathode of the second diode is connected to the gate of a clamping transistor.   5. The shift register according to claim 1, further comprising a pull-down resistor interposed between a source of the output transistor and a ground point. 6. A liquid crystal drive, wherein the shift register according to claim 1 is used to generate a scan drive signal of an active matrix circuit in which a scan line and a signal line cross each other. circuit.

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