KR100932799B1 - register - Google Patents

Abstract

The present invention is to improve the configuration of the input portion of the register in a register consisting of a plurality of cascade connected to the shift register, so that the signal input from the preceding register can be input without loss occurs, the voltage drop is It can be input without generation to stabilize the operating characteristics of the circuit, improve the operating characteristics of the shifter resistor, and extend its service life.

Description

Register {Register}

1 is a block diagram showing the configuration of a general shifter register;

FIG. 2 is a circuit diagram showing the configuration of a register forming each stage shown in FIG. 1;

3 is a circuit diagram showing the configuration of another example of an input unit in a conventional register;

4 is a circuit diagram showing the configuration of an embodiment of a register according to the present invention;

5 is a graph for explaining the improvement effect by the register of the present invention;

6 is a graph for explaining a voltage drop generated in a conventional resistor;

7 is a circuit diagram showing the configuration of another embodiment of the input unit in the register of the present invention, and

8 is a circuit diagram showing the configuration of another embodiment of the input unit in the register of the present invention.

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The present invention relates to a register in which a plurality are cascaded to constitute a shift register. More particularly, the present invention relates to a register in which a plurality of cascade-dependent registers constitute a shift register. The register may be improved so that a signal input from a previous register may be input without loss.

In general, display devices using a flat panel display panel such as an LCD (Liquid Crystal Display) panel and an organic light emitting display (OLED) panel use a shift register to sequentially drive a plurality of scan electrodes provided in the flat panel display panel. Doing. The shift register is a plurality of registers are cascade-connected to output a predetermined driving signal while the plurality of registers are sequentially shifted to sequentially drive the plurality of scan electrodes of the flat panel display panel.
When such a shift register is used for a long time, a characteristic change often occurs in a transistor provided in each of a plurality of cascaded resistors, and such a characteristic change causes a deterioration in the operation of the shifter resistor.

1 and 2 show the configuration of the shift register proposed in the prior patent application No. 10-2002-0033455. That is, FIG. 1 is a block diagram of a general shifter register, and FIG. 2 is a circuit diagram showing the configuration of each register constituting a shift register by cascading a plurality of shown in FIG.
In the general shift register, as shown in FIG. 1, a plurality of registers SR1, SR2,... Are cascaded, and output signals Gout of each of the registers SR1, SR2,... , SR3, ... are connected to be input to the input terminal IN. Each of the registers SR1, SR2, ... has an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal CKV, CKVB, an input terminal CK, and a first power supply voltage Voff. It has a terminal and a second power supply voltage (Von) input terminal. The start signal STV is input to the input terminal IN of the first register SR1, and the output signals Gout (1), Gout (2), Gout (3), Gout 4... Are sequentially outputted to utilize them and these output signals Gout (1), Gout (2), Gout (3), Gout (4),... Are input to the input terminals IN of the registers SR2, SR3, ... provided in the next stage, respectively. The first clock signal CKV is input to the clock terminal CK of the odd-numbered registers SR1, SR3, SR5, ..., and the second clock is supplied to the clock terminal CK of the even-numbered registers SC2, SC4, .... The signal CVKB is input. Here, the first clock signal CKV and the second clock signal CKVB have the same frequency and have phases opposite to each other.

Each of the resistors SR1, SR2, ... includes a pull-up driving transistor 502, 504, 506, a pull-down driving transistor 508, and a gate output driver 510, 512, as shown in FIG.

In the transistor NT1, a drain is connected to an input terminal of a second power supply voltage Von, a gate is connected to an input terminal IN, and a signal Gout (N-1) output from a resistor in front of the transistor is applied, and a source is a node N1. Is connected to. Operation starts as the output signal of the front end resistor is supplied to node N1 through transistor NT1. That is, when the signal Gout (N-1) outputted from the preceding register is input to the input terminal IN, the transistor NT1 is in a conductive state, and the node through the transistor NT1 is not lost while the second power supply voltage Von is lost. It is supplied to N1.
Thus, another connection method of the transistor NT1 to which the output signal of the preceding resistor is input is shown in FIG. The connection method of FIG. 3 is generally widely used and one example is shown in the prior patent application No. 10-2004-0004764. In FIG. 3, instead of the drain being connected to the second power supply voltage Von, the output signal Gout (N-1), which is connected to the gate and output from the resistor in the front end, is applied. The transistor shown in FIG. 3 operates as a diode, and the voltage output from the front end resistor is output to the source through this drain electrode. Even in this case, the output voltage of the front end is not lost and must be output to the source of the transistor to ensure good operating characteristics.

However, the operation of the transistor starts when the gate voltage exceeds a predetermined threshold voltage (VT), the operation is initiated, the voltage flowing into the resistor is less than the input voltage because of this threshold voltage. Therefore, compared with the case where all the input voltage flows into the node N1 without loss, the characteristics of the operation are lowered and the life of the circuit is reduced.

SUMMARY OF THE INVENTION In order to solve the problems of the prior art, the present invention provides a register which improves the operating performance and enables the normal operation without affecting the operation even if the characteristics of the transistor are degraded.

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In particular, the present invention provides a resistor that can improve the operation performance and increase the operating life of the circuit by improving the circuit for inputting the output voltage of the preceding resistor and the circuit associated therewith.

In order to achieve the above object, the present invention inputs an input signal by adding one transistor and one capacitor one by one, and adds a transistor for a reset function separately to implement stable circuit operation to improve operation performance. , Increase the operating life.

The transistor used in the resistor of the present invention is composed of ordinary gates, sources, and drains, and is indicated by G, S, and D in the drawings, respectively.

The configuration of the register according to the present invention will be described with reference to FIG. In the present invention, an input terminal includes a first transistor T1, a second transistor T2, and a capacitor C3. That is, the gate and the drain of the first transistor T1 and the drain of the second transistor T2 are commonly connected to the input terminal IN. The source of the first transistor T1 is connected to the gate of the second transistor T2, and the capacitor C3 is connected between the gate and the source of the second transistor T2.

The output unit includes the capacitors C1 and C2 and the fourth transistor T4. That is, the node N1, which is the connection point of the source of the second transistor T2 and the capacitor C3, is connected to the gate of the fourth transistor T4, and the first clock signal CKV is connected to the capacitor C1. It is configured to be applied to the gate of the fourth transistor (T4) through. The second clock signal CKVB is applied to the drain of the fourth transistor T4, and a capacitor C2 is connected between the gate and the source of the fourth transistor T4 so that the fourth transistor ( The connection point between the source of T4 and the capacitor C2 is connected to the output terminal OUT to output the output signal Gout (N).
The output terminal OUT is connected to the gate of the sixth transistor T6, and the drain of the sixth transistor T6 is the source of the first transistor T1 and the gate of the second transistor T2. And an input reset unit connected to a connection point of the capacitor C3, and a source of the sixth transistor T6 connected to a first power supply voltage Voff input terminal to discharge the charging voltage of the capacitor C3. do.
The control terminal CT, to which the output signal Gout (N-1) of the next stage register is input, is connected to the gates of the third transistor T3 and the fifth transistor T5. The drain of the third transistor T3 is connected to the node V1, and the source of the third transistor T3 is connected to the first power supply voltage Voff input terminal. A drain of the fifth transistor T5 is connected to the output terminal OUT, and a source of the fifth transistor T5 is connected to the first power supply voltage Voff input terminal to form an output reset unit.

In the register of the present invention configured as described above, the output signal Gout (N-1) output from the preceding register is input to the input terminal IN while the first power supply voltage Voff is applied.
Then, the signal input to the input terminal (IN) is applied to the gate of the second transistor (T2) while being charged to the capacitor (C3) through the first transistor (T1) acting as a diode so that the second transistor (T2) ) Becomes a conductive state, and the input signal of the input terminal IN is output to the node N1 through the second transistor T2 and charged to the capacitor C2. At this time, the input signal inputted to the input terminal IN, that is, the output signal Gout (N-1) outputted from the register in front of the node N1 through the second transistor T2 without a loss occurring. Is output.

That is, according to the present invention, the output signal Gout (N-1) output from the resistor in the front end is applied to the gate of the second transistor T2 while being charged to the capacitor C3 through the first transistor T1, and thus the second signal is output to the second transistor T2. When the transistor T2 is brought into a conductive state, the output signal Gout (N-1) is outputted to the node N1 through the second transistor T2 and charged in the capacitor C2, and the capacitor ( The voltage applied to the gate of the second transistor T2 is increased by the voltage charged in C2 so that the output signal Gout (N-1) is all supplied to the node N1 without being damaged. The output signal Gout (N-1) supplied to the node N1 is applied to the gate of the transistor T4 while being charged in the capacitor C2.

The voltage of the node N1 is shown in FIG. 5. Referring to FIG. 5, the voltage of the node N1 increases while the output signal Gout (N-1) of the front end resistor is inputted to be equal to the level of the output signal Gout (N-1). It can be seen that.
6 illustrates the voltage of the node N1 when the input unit of the prior art is used to compare the present invention with the conventional technique. As shown in FIG. 6, it can be seen that the voltage of the node N1 is significantly lower than the voltage of the output signal Gout (N-1) input from the resistor in the previous stage when the input unit of the prior art is used.
In this state, the fourth transistor T4 is brought into a conductive state by the voltage charged in the capacitor C2, and is applied to the gate of the fourth transistor T4 when the first clock signal CKV is input. The voltage rises as shown in FIG.
When the first clock signal CKVB is input, the input first clock signal CKVB is output to the output terminal OUT through the fourth transistor T4 and output to the output terminal OUT. The output signal Gout (N) is input to the input terminal of the register of the next stage.
Since the signal output to the output terminal OUT is applied to the gate of the sixth transistor T6, the transistor T6 is brought into a conductive state, and the contact voltage charged in the capacitor C3 is discharged through the transistor T6. As a result, the input unit is reset to the initial state.
The output signal Gout (N) output to the output terminal OUT is input to the register of the next stage, and the register of the next stage outputs the output signal Gout (N + 1) as in the present invention. The output signal Gout (N + 1) is input to the control terminal CT and is applied to the gates of the third transistor T3 and the fifth transistor T5.
As a result, the third transistor T3 and the fifth transistor T5 are in a conductive state, and the charging voltages of the capacitors C1 and C2 are discharged through the third transistor T3 and the fifth transistor T5. The output section is reset to the initial state.

Such a circuit of the present invention can be applied not only to the shift register as in the embodiment of the present invention but also to various circuits for processing various types of shift registers or input voltages.

7 is a circuit diagram showing the configuration of another embodiment of the input unit in the register of the present invention. Referring to FIG. 7, according to another embodiment of the present invention, an input terminal IN is connected to a gate of the eleventh transistor 11, and a second power supply voltage Von input terminal is connected to a drain of the eleventh transistor T11. Connected to the drain of the twelfth transistor T12, a source of the eleventh transistor T11 is connected to a gate of the twelfth transistor T12, and a capacitor C13 between the gate and the source of the twelfth transistor T12. Is connected to constitute an input unit.
According to another embodiment of the present invention configured as described above, when the output signal Gout (N-1) of the preceding register is input to the input terminal IN, the eleventh transistor T11 is brought into a conductive state. When the eleventh transistor T11 is in a conductive state, the output signal Gout (N-1) of the previous register input to the input terminal IN is charged to the capacitor C13 through the eleventh transistor T11. The twelfth transistor T12 is in a conductive state by being applied to the gate of the twelfth transistor T12. When the twelfth transistor T12 is in a conductive state, the output signal Gout (N-1) is outputted to the node N1 through the twelfth transistor T12 and charged to the capacitor C2, thereby providing the twelfth transistor T12. The gate voltage of the transistor T12 is increased to allow the node N1 to charge the output and the capacitor C2 without causing a loss in the output signal Gout (N-1).

8 is a circuit diagram showing the configuration of another embodiment of the register of the present invention. Referring to FIG. 8, according to another embodiment of the present invention, the input terminal IN is connected to the gate of the twenty-first transistor T21, and the drain of the twenty-first transistor T21 and the drain of the twenty-second transistor T21 are provided. The second power supply voltage Von input terminal is connected. The source of the twenty-first transistor T21 is connected to the gate of the twenty-second transistor T21, and the capacitor C23 is connected between the gate and the source of the twenty-second transistor T22 to form an input unit.
According to another embodiment of the present invention configured as described above, when the output signal Gout (N-1) output from the previous register is input to the input terminal IN while the second power supply voltage Von is applied. The twenty-first transistor T21 is brought into a conductive state When the twenty-first transistor T21 is brought into a conductive state, a second power supply voltage Von is charged to the capacitor C23 through the twenty-first transistor T21, and the twenty-second transistor is in a conductive state. It is applied to the gate of T21 and output to the node N1.
The voltage output to the node N1 is charged in the capacitor C2, and the gate voltage of the twelfth transistor T12 is increased according to the charging voltage of the capacitor C2 to be input to the input terminal IN. It is possible to charge the output and the capacitor C2 to the node N1 without causing a loss in the output signal Gout (N-1) of the preceding resistor.

As described in detail above, the present invention improves the reliability of an operation by improving the structure of an input unit of a register, in which a plurality of cascades are connected, so that a loss can be input when an input signal is input. Even if the transistor deteriorates or the performance of the transistor deteriorates due to an abnormal process, reliable operating characteristics can be secured to extend the operating life.

Claims (4)

A register for shifting a predetermined drive signal sequentially by forming a shift register with a plurality of cascaded connections, comprising: an input unit for inputting an output signal output from a preceding register to an input terminal and supplying the signal to a node; A register comprising an output section for outputting to a register of a next stage in accordance with a clock signal, and an output reset section for resetting the output section in accordance with an output signal outputted by a register of a next stage. The input unit; A gate and a drain of the first transistor and a drain of the second transistor are commonly connected to the input terminal so that the source of the first transistor is connected to the gate of the second transistor and between the gate and the source of the second transistor. And a capacitor connected to the node of the second transistor and a connection point of the capacitor to the node. A register for shifting a predetermined drive signal sequentially by forming a shift register with a plurality of cascaded connections, comprising: an input unit for inputting an output signal output from a preceding register to an input terminal and supplying the signal to a node; A register comprising an output section for outputting to a register of a next stage in accordance with a clock signal, and an output reset section for resetting the output section in accordance with an output signal outputted by a register of a next stage. The input unit; The input terminal is connected to the gate of the eleventh transistor, the second power supply voltage input terminal is connected to the drain of the eleventh transistor and the drain of the twelfth transistor, and the source of the eleventh transistor is connected to the gate of the twelfth transistor. And a capacitor is connected between a gate and a source of the twelfth transistor, and a connection point of the source of the twelfth transistor and the capacitor is connected to the node. A register for shifting a predetermined drive signal sequentially by forming a shift register with a plurality of cascaded connections, comprising: an input unit for inputting an output signal output from a preceding register to an input terminal and supplying the signal to a node; A register comprising an output section for outputting to a register of a next stage in accordance with a clock signal, and an output reset section for resetting the output section in accordance with an output signal outputted by a register of a next stage. The input unit; The input terminal is connected to the gate of the twenty-first transistor, the second power supply voltage input terminal is connected to the drain of the twenty-first transistor and the drain of the twenty-second transistor, and the source of the twenty-first transistor is connected to the gate of the twenty-second transistor. And a capacitor is connected between the gate and the source of the twenty-second transistor so that a connection point of the source and the capacitor of the twenty-second transistor is connected to the node. The method according to any one of claims 1 to 3, And a sixth transistor configured to discharge the charging voltage of the capacitor to reset the input unit according to a signal output from the output unit.

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