CN1822088A

CN1822088A - Shift register and liquid crystal driver circuit

Info

Publication number: CN1822088A
Application number: CNA2006100047037A
Authority: CN
Inventors: 岩崎千里
Original assignee: Alps Electric Co Ltd
Current assignee: Alps Alpine Co Ltd
Priority date: 2005-02-16
Filing date: 2006-02-15
Publication date: 2006-08-23
Also published as: JP2006228312A; KR20060092104A; TW200634713A

Abstract

The invention provided a shift register in which output of a needless drive pulse can be prevented by suppressing variation of gate voltage of an output transistor using reducing output impedance by bootstrap operation and a liquid crystal driver using this shift register. The shift register has a plurality of stages connected in cascade and in which input data is shifted and shift operation of the input data is performed, each stage has a first diode connected to a gate of the output transistor and inputting the input data, a capacitor connected between the gate and a source of the output transistor, and a clamping transistor connected between the gate and the source of the output transistor in parallel to the capacitor, wherein a source of the clamping transistor is connected to the source of the output transistor, a drain of the clamping transistor is connected to the gate of the output transistor.

Description

Shift register and liquid crystal display drive circuit

Technical field

The present invention relates to for example be arranged on the liquid crystal indicator of LCD etc., the shift register of scanning drive signal is provided and uses its liquid crystal display drive circuit.

Background technology

For example, in the liquid crystal indicator of the active array type of display device that is used in computing machine and televisor, rectangular video signal cable (row distribution) and the scanning drive signal line (row distribution) of being provided with is provided with the on-off elements such as thin film transistor (TFT) of the liquid crystal that drives each pixel at the intersection point of these distributions.

And, scan these signal wires successively, the scanning drive signal that provides the whole on-off elements that make on the scanning drive signal line temporarily to become conducting state (ON state) to a plurality of scanning drive signal lines is to video signal cable and scanning drive signal line locking ground supplying video signal.

At this, the work that a plurality of scanning drive signal lines are supplied with successively be exactly shift register.

As shown in Figure 7, in display part, on matrix, be provided with a plurality of capable distributions and row distribution, become the active circuit that disposes liquid crystal cell in this row distribution and row wiring crossing portion, on-off element (transistor) that described liquid crystal cell is applied to the voltage of liquid crystal by control and controlled liquid crystal portion constitute.

Gate drivers (shift register) applies assigned voltage by the time sequence, make capable distribution (sweep trace) become conducting state, the driver of row distribution and this timing synchronously apply predetermined voltage (utilizing signal wire to apply) to source electrode, change the optical states of liquid crystal thus, drive liquid crystal indicator.

Then, drive liquid crystal cell, so in Fig. 7, utilize film crystal pipe manufacturer gate drivers (for example, with reference to patent documentation 1).

At this moment, need make the gate drivers high speed operation that the row distribution is applied voltage, and supply with the sufficient magnitude of current to the row distribution.

At this, as shown in Figure 8, gate drivers is made of the shift register of the hop count with a plurality of SR (shift register) level.

Then, each SR level becomes structure shown in Figure 9, and as shown in Figure 8, this SR level cascade connects, and each SR level applies voltage as driving pulse to the row distribution successively, plays the function that the grid of the thin film transistor (TFT) of liquid crystal cell is applied the gate drivers of predetermined voltage.

In addition, each SR level applies the driving pulse of back segment by the grid to clamping transistor 25, and the grid voltage of output transistor 16 (node P) just drops to earth level, and output transistor 16 is reset to off state, does not promptly export the holding state of driving pulse.

At this, shift register is designed to: in the oscillogram of the expression drive waveforms of Figure 10, before and after driving pulse (phase shifted clock) output, the node P1 among Fig. 9 is applied the grid voltage Vgs (grid one source pole voltage) that makes output transistor 16 fully become conducting state (state that conducting resistance is fully low).

In Figure 10, transverse axis represents that the longitudinal axis is represented the level of waveform constantly.

Patent documentation 1: Japanese kokai publication hei 08-87897 communique

Above-mentioned at different levels in the transfer processing of holding state, the driving pulse owing to according to back segment output makes clamping transistor 25 become conducting state, therefore, only when grid has been applied pulse, could give stress, reduce applying of residual stress reed bit transistor 25.

But, become holding state at the back segment of each SR level, clamping transistor 25 become conducting state during, node P becomes not by the quick condition of reed position to predetermined voltage, produces the non-steady state of the variation in voltage of node P owing to noise.

That is, the predetermined timing of output transistor 16 bases, to drain electrode distribution 14 input clock C1, when reed bit transistor 25 is off state, an input clock C1, the voltage of node P is change just.

Then, just according to the variation in voltage of this node P, as shown in figure 11, in the timing of the output that self is limiting driving pulse, the driving pulse of output noise drives display device to output transistor 16.

From Figure 11 (analog result), utilize pull-down transistor 17, the flip-flop of the driving pulse of above-mentioned noise might be in node 13 (output distribution), removed to a certain extent, but the potential change of pulse type can not be removed fully.

In Figure 11, the input waveform of clock C1 is represented on top, and the waveform of the driving pulse OUTn in the lead-out terminal is represented in the lower part, and in addition, transverse axis is that the longitudinal axis is the current potential of output waveform constantly.

Thereby, even working properly as shift register also drives the unnecessary display element of display device, the contrast of display image is descended, therefore, the gate drivers that is not suitable as in the sweep circuit that is applied to display device uses.

In addition and since pull-down transistor 17 because of through the time change deterioration, therefore, pull down resistor raises, and can not suppress the flip-flop of the noise in the node 13.

Its result, shift register does not just have the function as the sweep circuit of display device, can not normally carry out the display process in the display device.

In the structure of above-mentioned shift register, because of the variation in voltage output transistor 16 of node P delays work, do not export unnecessary driving pulse, so expectation node P pulls down to earth level all the time.

But the node P structure of ground connection all the time uses the intermediate circuit of pull-down node P, and complicated compensating circuit need be set, so that the transistor that constitutes this intermediate circuit is not applied residual stress, the problem that increases circuit scale because of circuit structure and distribution thereof is arranged.

Summary of the invention

The present invention makes in view of such thing, its purpose is, a kind of shift register is provided or uses the liquid crystal driver of this shift register, this shift register can utilize bootstrapping work to reduce output impedance, the change of the grid voltage of the output transistor that suppresses to use prevents the output of unnecessary driving pulse.

Shift register of the present invention has a plurality of levels that cascade connects, utilize the different a plurality of clocks of phase place will import data shift, when these input data of input, the clock that is input to the drain electrode of output transistor is exported from source electrode as phase shifted clock, carry out the displacement work of output signal, have at different levels above-mentioned: the 1st diode, be connected with the grid of above-mentioned output transistor, import above-mentioned input data; Capacitor is connected between the grid and source electrode of above-mentioned output transistor; And the reed bit transistor, between the grid of above-mentioned output transistor and source electrode, be connected in parallel with above-mentioned capacitor; The source electrode of above-mentioned clamping transistor is connected with the source electrode of above-mentioned output transistor, and the drain electrode of above-mentioned clamping transistor is connected with the grid of above-mentioned output transistor.

Thus, shift register of the present invention, the grid clamping that makes output transistor by clamping transistor is predetermined current potential, just can suppress the potential change because of the noise generation in the grid of output transistor, can prevent that output transistor from exporting delaying work of unwanted driving pulse.

In addition, the potential change in the grid of shift register inhibition output transistor of the present invention, thus comprise the output pulse of back segment, need be from the control signal of other circuit, therefore, circuit and distribution do not become complicated structure, do not increase circuit scale.

Shift register of the present invention, above-mentioned clamping transistor is controlled as off state during the driving of level, be not controlled as conducting state during driven.

Shift register of the present invention has control circuit, and this control circuit applies output voltage for the grid of above-mentioned clamping transistor during level is driven, applies the voltage higher than the threshold voltage of this clamping transistor during level is not driven.

Shift register of the present invention, above-mentioned control circuit comprises: the 2nd diode that anode is connected with the source electrode of above-mentioned clamping transistor, and between the negative electrode of the 2nd diode and the 2nd capacitor between the earth point; The negative electrode of above-mentioned the 2nd diode is connected with the grid of clamping transistor.

Thus, shift register of the present invention just only applies pulse feature stress when the conversion of driving and non-driving, does not need clamping transistor and other additional transistorized grids are applied unwanted residual stress, improves whole reliability.

Shift register of the present invention has between the source electrode of above-mentioned output transistor and the pull down resistor between the earth point.

Thus, shift register of the present invention just can utilize pull-down transistor, during not driven, the grid potential of output transistor is pulled down to ground connection, therefore, can suppress the potential change that causes by noise in the grid of output transistor, can prevent that output transistor from exporting delaying work of unwanted driving pulse.

The shift register of above-mentioned any structure uses liquid crystal display drive circuit of the present invention for the scanning drive signal of the active matrix circuit that generates sweep trace and signal wire and intersect to constitute.

Thus, liquid crystal display drive circuit of the present invention can suppress the output of the unnecessary driving pulse that caused by noise, therefore, can make change degree to the driving pulse of the noise of display device output become the degree of the reduction etc. of the imperceptible contrast of user, promptly not influence the scope of the display quality in the liquid crystal display picture.

The invention effect

As described above such, according to the present invention, the reed bit transistor pulls down to the grid of output transistor the current potential of regulation, circuit and distribution do not form complicated structure thus, do not increase circuit scale, can suppress the potential change that causes by noise in the grid of output transistor, prevent that output transistor from exporting delaying work of unwanted driving pulse.

Description of drawings

Fig. 1 is the block diagram of the structure example of the shift register that relates to of expression the of the present invention the 1st and the 2nd embodiment;

Fig. 2 is the concept map of structure example of the circuit of the level n that relates to of the 1st embodiment in the presentation graphs 1;

Fig. 3 is the oscillogram of work of the shift register of presentation graphs 1;

Fig. 4 is the figure of the waveform of the analog result in the shift register of Fig. 1 of structure of the expression level n that used Fig. 2;

Fig. 5 is the concept map of structure example of the circuit of the level n that relates to of the 2nd embodiment in the presentation graphs 1;

Fig. 6 is the figure of the waveform of the analog result in the shift register of structure of the expression level n that uses Fig. 5;

Fig. 7 is the concept map of the structure example of expression liquid crystal indicator;

Fig. 8 is the block diagram of the structure of the shift register that relates to of expression conventional example;

Fig. 9 is the concept map of circuit structure of levels at different levels of presentation graphs 8;

Figure 10 is the oscillogram of work example of the shift register of presentation graphs 8;

Figure 11 is the figure of the waveform of the analog result in the shift register of presentation graphs 8.

Embodiment

The present invention relates on the substrate that is formed on liquid crystal indicator by a-Si etc., the at different levels of shift register are in the register cell, prevent the technology of delaying work of output transistor because of noise, the scanning drive signal that this output transistor output drives liquid crystal cell is phase shifted clock Gout (driving pulse).

Promptly, the clamping transistors that are provided with at different levels of shift register of the present invention, be used to suppress the variation in voltage of the grid of output transistor, do not export driving pulse during, above-mentioned clamping transistor remains below the voltage of the grid of output transistor the value of the threshold voltage of output transistor.

Thus, the at different levels just grid of output transistor being controlled to be of shift register of the present invention do not apply the voltage that changes because of noise, therefore, do not export driving pulse during, do not delay work because of noise causes, do not export unnecessary driving pulse.

The 1st embodiment

Below, the shift register that relates to reference to description of drawings the 1st embodiment of the present invention, use as the gate drivers (liquid crystal display drive circuit) of Fig. 7.Fig. 1 is the block diagram of the structure example of the shift register that relates to of above-mentioned the 1st embodiment of expression.

In the figure, shift register 100 become cascade connected a plurality of level (register cells) 1,2,3,4 ... structure, utilization is from a plurality of phases of the clock generator of outside input, the clock of 2 phases (CK1, CK2) for example, make the input data shift, by the level of having imported data, with the clock synchronization mutually that is input to this grade, successively from different levels to terminal Mout1, Mout2, Mout3, Mout4 ... output phase shift clock respectively.

At this, any clock in the clocks of importing 2 phases according to phase sequence at different levels is when the input data of displacement have successively arrived self, with the clock synchronization ground output output data (phase shifted clock) of input.

Level 1 output phase shift clock Gout1, level 2 output phase shift clock Gout2, level 3 output phase shift clock Gout3, level 4 output phase shift clock Gout4.

Promptly, in shift register 100, utilize above-mentioned dual clock to make successively from the input data shift of commencing signal ST input, imported the level and the clock synchronization that is input to this grade of data, by the terminal Moutn that connects, to liquid crystal cell output phase shift clock as drive signal.

To level 1 input clock CK1, to level 2 input clock CK2, to level 3 input clock CK1, to level 4 input clock CK2 ..., to level n input clock m.(m is with " 2 " numerical value divided by the remainder of n, is 2 under situation about eliminating.)

Below, with reference to the structure of the level n in the shift register of Fig. 2 key diagram 1.Fig. 2 is the concept map (the input signal difference of other grades, but structure is identical with this grade n) of the circuit structure of expression level n.

Among the output transistor M1, connect the drain electrode of transistor M2 on grid, to drain electrode input clock CKm, source electrode is connected with terminal Moutm.

Diode D1 is an input circuit, and anode is connected with terminal In, and negative electrode is connected (utilizing tie point A to connect) with the grid of output transistor M1.

This diode D1 also can use diode component, also can constitute with transistor as shown in Figure 2, under this situation, uses the terminal that has connected grid and drain electrode as anode, uses source electrode as negative electrode.

The end of capacitor C1 is connected with the grid of output transistor M1, and the other end is connected with the source electrode of output transistor M1.

The anode of diode D2 is connected with the source electrode of output transistor M1, and negative electrode is connected with the end (tie point B) of capacitor C2.

This diode D2 and diode D1 similarly also can use diode element, also can be made of transistor as illustrated in fig. 2, use the terminal that has connected grid and drain electrode as anode under this situation, use source electrode as negative electrode.

The end of capacitor C2 is connected with tie point B, other end ground connection, and diode D2 is in series between output transistor M1 and earth point (Vss).

Be provided with the clamping transistor of transistor M2 as output transistor M1, the drain electrode of transistor M2 is connected with the grid of output transistor M1, and source electrode is connected with the source electrode of output transistor M1, and grid is connected with tie point B.

The drain electrode of transistor M3 is connected with the grid of transistor M2, and grid is connected source ground with the anode of diode D1.

Output transistor M1, transistor M2, M3 (constituting in addition, the transistor of diode D1, D2, D3) all are n channel fet (field effect transistors).

Below, utilizing Fig. 3, the work of the shift register that relates to about the 1st embodiment of the present invention is that benchmark illustrates with level n.Fig. 3 is the oscillogram of the work of the level n in the shift register that relates to of expression the 1st embodiment.

In level n, the anode of diode D1 is connected with the terminal Tout n-1 of the level n-1 of full section.At this, for convenience of description, the clock CKm that establishes the drain electrode that is input to output transistor M1 is CK2.Therefore, clock CK1 has been imported in the drain electrode of the output transistor M1 in the level n+1 of level n-1 and the back segment of leading portion.

In moment t1, because the driving pulse Goutn-1 of level n-1 output is " L " level, that is, terminal In is " L " level, and therefore, the current potential of tie point A just becomes " L " level.

At this moment, output transistor M1 because of grid for " L " so level is an off state, imported the clock CK2 of predetermined pulsewidth to drain electrode, but driving pulse Goutn becomes " L " level.

In addition, the back explains, but the control circuit that tie point B reason diode D2 and capacitor C2 constitute and become expectant control voltage, transistor M2 has become conducting state.

Therefore, tie point A becomes the current potential of the source electrode of output transistor M1, i.e. " L " by transistor M2, and output transistor M1 is an off state.

Then, at moment t2, the driving pulse Goutn-1 of level n-1 output becomes " H " level, and promptly, terminal In becomes " H " level, therefore, the current potential of tie point A is " H " level with regard to transition.

Thus, during driving pulse Goutn-1 is " H " level, promptly, during the pulsewidth of driving pulse Goutn-1, the grid of transistor M3 is applied " H " level, therefore,, make tie point B become " L " level charges accumulated discharge among the capacitor C2.

On the other hand, input data after displacement are " L " level, promptly, driving pulse Goutn-1 is under the situation of " L " level, in the timing of displacement, capacitor C1 is not recharged, and output transistor M1 still is an off state, therefore, tie point B is still control voltage, makes transistor M2 become conducting state.

Thus, even input clock CKm, the voltage of lead-out terminal Moutn does not change yet, not output noise.

Thus, transistor M2 becomes off state, and capacitor C1 is charged to predetermined voltage.That is, the current potential of tie point B is controlled to be in the timing that is charged as predetermined voltage by capacitor C1 becomes off state, just can carry out the bootstrapping of the grid voltage of output transistor M1 by capacitor C1.

And, be applied in " H " level on the grid of output transistor M1, thus conducting state become, but, therefore, just do not export driving pulse Goutn with " H " level also not to drain electrode input clock CK2.Therefore, lead-out terminal Moutn is " L " level.

Then, in moment t3, the output of level n-1 becomes off state, but becomes the state of having accumulated electric charge in capacitor C1 by diode D1, promptly is charged as predetermined voltage.

Then,, become " H " level to the clock CK2 of drain electrode input because output transistor M1 is a conducting state, therefore, the current potential rising that electric current flows and makes source electrode.

Thus, terminal (terminal that is connected with the source electrode of output transistor M1) to capacitor C1 is supplied with electric charge and the current potential rising, another terminal of capacitor C1 (terminal that is connected with the grid of output transistor M1) is in order to keep the potential difference (PD) of capacitor C 1, and the current potential part (bootstrapping work) same with the terminal of capacitor C1 rises.

Promptly, output transistor M1 is under the conducting state at output transistor M1, with " H " level input clock CK2, thus, the voltage that applies to grid is by the voltage level part of capacitor C1 boosting timeclock CK2, by reducing conducting resistance, to the voltage level that level n+1 exports and clock CK2 is roughly same of next section and the driving pulse Goutn (input data) of pulsewidth.

At this moment, because driving pulse Goutn-1 is " L " level, so transistor M3 becomes off state, to capacitor C2 inflow current, electric charge is accumulated in capacitor C2 from output transistor M1 process diode D2, and capacitor C2 is charged as predetermined voltage.

Thus, transistor M2 just becomes grid has been applied the state that surpasses the voltage of threshold value, but because grid and source electrode are roughly the same current potentials, so the immobilising off state of electric current.

Then, when clock CK2 becomes " L " level, the voltage of the source electrode of output transistor M1, be the current potential of lead-out terminal Moutn, electric current flows to drain side by the output transistor M1 that is in conducting state, becomes " L " level.

Then, transistor M2 is under the state of " H " level at grid voltage, because the current potential of source electrode becomes " L " level, so be conducting state, the electric charge that will be accumulated among the capacitor C1 by output transistor M1 discharges, the current potential of tie point A is become " L " level.

At this moment,, but preestablish the capacity ratio of capacitor C 2 and capacitor C3, so that the voltage of capacitor C2 charging becomes the control voltage higher than the threshold voltage of transistor M2 because of the current potential of the 3 capacitor C2 of the capacitor C between the gate-to-source of transistor M2 descends.

Thus, because grid has been applied the control voltage that is accumulated among the capacitor C2, therefore, transistor M2 is still conducting state.

Then, in moment t4, because tie point A becomes " L " level, so output transistor M1 becomes off state, because clock CK2 also is " L " level, so not with " H " level output driving pulse Goutn.

At this moment, because grid has been applied the control voltage of accumulating among the capacitor C2, so transistor M2 still is a conducting state.

Therefore, even noise will make the potential change of tie point A, the current potential that transistor M2 also suppresses the tie point A that caused by noise rises, so, can suppress the change of the grid voltage of output transistor M1, prevent that output transistor M1 from delaying work.

Then, at moment t5, because of grid voltage becomes " L " level, so output transistor M1 is an off state.

At this moment, clock CK2 becomes " H " level, but because transistor M2 becomes conducting state, therefore, suppresses the potential change of tie point A, so do not make output transistor M1 with such the delaying work of " H " level noise ground output driving pulse Goutn.

In addition, in order to make charges accumulated discharge among the capacitor C1, do not need to be provided with the transistor of the discharge usefulness of ground connection, driving pulse (utilizing as reset signal) by the later level output of back segment makes this transistor turns, therefore, can cut down the distribution of inter-stage, cut down the erection space of circuit, dwindle circuit scale.

Similarly, do not control this transistorized grid voltage because do not need to be provided with the transistor (pull-down transistor and clamping transistor) of the discharge usefulness of ground connection, the grid voltage that is used for reed position output transistor, so, do not need to be provided for controlling the circuit of this grid voltage, can simplify circuit structure and distribution.

In addition, also can between lead-out terminal Moutn and earth point, insert pull down resistor.Thus, in the circuit of the level n of Fig. 2 because lead-out terminal Moutn is by drop-down, so, with output distribution that lead-out terminal Moutn is connected in accumulating under the situation by the electric charge of noise supply, the current potential of lead-out terminal Moutn rises gradually.

But owing to just accumulating electric charge, so current potential is flip-flop, by insert pull down resistor between lead-out terminal Moutn and earth point, just can easily suppress this current potential rising.

In addition, as described above,, therefore, consider to compare with available circuit owing to only removed the flip-flop of accumulating among the lead-out terminal Moutn, good with high-resistance pull down resistor, the also sufficient situation of the dead resistance that circuit had.

Corresponding with the analog result (with reference to Figure 11) of conventional example, except the transistor M2 and diode D2, capacitor C2 as control circuit of clamping transistor, the transistor that makes other is identical with the fixed number of capacitor and analog result in the 1st embodiment that carries out is shown in Fig. 4.

In Fig. 4, the input waveform of clock CKm is represented on top, and the waveform of the driving pulse Goutn among the lead-out terminal Moutn is represented in the lower part, and in addition, transverse axis is that the longitudinal axis is the current potential of output waveform constantly.

With Figure 11 more as can be known, the lead-out terminal Moutn during input clock CKm does not have variation in voltage.

In addition, in simulation, compare with the pull down resistor of setting in the conventional example (transistor 17), using more in the 1st embodiment, high resistance has carried out the work affirmation, for example, if conventional example is 1M (million) Ω, then use the resistance of 100M Ω in the 1st embodiment, as shown in Figure 4 as can be known, the potential change of the output distribution that is connected with lead-out terminal Moutn suppresses to be minimum level.

Thereby, with " H " level output driving pulse Goutn the time,, just can suppress can reduce the driving force of output transistor M1 by connecting the voltage drop that pull down resistor causes by promoting the resistance value of pull down resistor, also can reduce consumed power.

In addition, use diode D3 that tie point B is applied the control voltage that transistor M2 becomes conducting state, just can easily carry out the work of above-mentioned transistor M2 after the energized and then for capacitor C2.

Not necessarily need to be provided with this diode D3, can suitably be provided with accordingly with above-mentioned situation.

In addition, be used under the situation of gate drivers of the liquid crystal indicator of representing among Fig. 5, be desirably in the broached-tooth design of both sides configuration shift register of the column direction of display part sometimes at the shift register that the 1st embodiment is related to.

Under this situation, do not need the driving pulse of the level that next section is later to connect up as reset signal in shift register, therefore, wiring has generated feature of the present invention easily.

The 2nd embodiment

Below, Fig. 5 represents the 2nd embodiment.The 2nd embodiment of the present invention and the 1st embodiment similarly, the gate drivers (liquid crystal display drive circuit) that can be used as Fig. 7 uses.The gate drivers structure of Fig. 5 and the 1st embodiment shown in Figure 2 are same, and difference is that the anode of diode D3 is not connected with lead-out terminal Moutn, the structure that is connected with the drain electrode of output transistor M1.

Under this situation, each clock CKm becomes " H " level, and capacitor C2 is charging repeatedly just, the roughly same magnitude of voltage of current potential of " H " level of maintenance and clock CKm.

Therefore, tie point B be transistor M2 grid voltage as shown in Figure 6, apply the roughly same magnitude of voltage of current potential with " H " level of clock CKm.

Fig. 6 represented with Fig. 4 similarity condition under the analog result of carrying out, transverse axis is that the longitudinal axis has been represented the potential level of each waveform constantly.

Thereby, from analog result as can be known, the 2nd embodiment and the 1st embodiment similarly, during except output driving pulse Goutn, even to the drain electrode input clock CKm of output transistor M1, in lead-out terminal Moutn, do not produce the such noise of conventional example as shown in figure 11 yet.

In addition, the circuit structure of the shift register that the 1st and the 2nd above-mentioned embodiment relates to is not only applicable to a-Si (amorphous silicon) TFT (thin film transistor (TFT)), goes for the gate drivers of multi-crystal TFT and the driver IC of monocrystalline silicon (integrated circuit) yet.

Claims

1, a kind of shift register, have a plurality of levels that cascade connects, utilize the different a plurality of clocks of phase place will import data shift, when these input data of input, the clock that is input to the drain electrode of output transistor is exported from source electrode as phase shifted clock, carried out the displacement work of output signal, it is characterized in that, above-mentioned at different levels in, have:

The 1st diode is connected with the grid of above-mentioned output transistor, imports above-mentioned input data;

Capacitor is connected between the grid and source electrode of above-mentioned output transistor;

And clamping transistor, between the grid and source electrode of above-mentioned output transistor, be connected in parallel with above-mentioned capacitor;

The source electrode of above-mentioned clamping transistor is connected with the source electrode of above-mentioned output transistor, and the drain electrode of above-mentioned clamping transistor is connected with the grid of above-mentioned output transistor.

2, shift register as claimed in claim 1 is characterized in that, above-mentioned clamping transistor is controlled as off state during the driving of level, is not controlled as conducting state during driven.

3, shift register as claimed in claim 2, it is characterized in that having control circuit, this control circuit is to the grid of above-mentioned clamping transistor, during level is driven, apply output voltage, during level is not driven, apply the voltage higher than the threshold voltage of this clamping transistor.

4, shift register as claimed in claim 3 is characterized in that, above-mentioned control circuit comprises:

The 2nd diode that anode is connected with the source electrode of above-mentioned clamping transistor and

Between the negative electrode of the 2nd diode and the 2nd capacitor between the earth point;

The negative electrode of above-mentioned the 2nd diode is connected with the grid of clamping transistor.

5, shift register as claimed in claim 4 is characterized in that, has between the source electrode of above-mentioned output transistor and the pull down resistor between the earth point.

6, a kind of liquid crystal display drive circuit is characterized in that, uses the described shift register of claim 1, is used to generate sweep trace and signal wire and intersects the scanning drive signal of the active matrix circuit that constitutes.