JP2002289663A - Method for manufacturing electronic device and program for analyzing defect data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quantify fatal defects accurately to control manufacturing process by analyzing foreign substances and pattern defects found in an electronic device forming a circuit pattern. SOLUTION: After a defect map data read step 11 and a failure rate distribution data read step 12 are executed, non-fatal defects are removed in a defect map data filtering step 13 by using these data. Then, a good/bad map data read step 14 is executed, and in a fatal defect rate calculation step 15, the defect map data and the good/bad map data are checked to calculate a fatal defect rate in the defect map data. Furthermore, in a fatal defect rate output step 16, the calculation result is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program for detecting foreign matter or pattern defects generated in the process of manufacturing an electronic device, and using the detection result to effectively analyze a factor of deterioration in the yield of the electronic device. Provided is a method for manufacturing an electronic device used.

[0002]

2. Description of the Related Art In general, an electronic device represented by a semiconductor integrated circuit is manufactured by a method in which a plurality of layers such as circuit patterns are formed on a silicon wafer and a plurality of chips (elements) are separated from each other. It can be broadly divided into post-processes for completing products. Most of the defects that occur during manufacturing occur in a pre-process in which fine processing is performed, and improving the yield in the pre-process is an important issue for reducing manufacturing costs. Here, the yield in the previous process refers to the non-defective rate determined by the result of the electrical test (probe test), which is the final test in the previous process, that is, the ratio of non-defective chips to the total number of chips in a wafer.

[0003] Defects that cause yield deterioration in the previous process can be roughly classified into functional defects and parametric defects.
A functional failure is a failure in which a circuit does not operate normally due to a disconnection or a short circuit of a circuit pattern, mainly due to a foreign substance or a pattern defect (collectively referred to as a defect hereinafter). On the other hand, a parametric defect is a defect in which the operation timing of a transistor, the capacitance of a capacitor, and the like are not completed according to design specifications due to minute variations in a process such as a circuit size and an oxide film thickness.

For the purpose of finding the cause of the malfunction at an early stage and taking countermeasures, each time a layer such as a circuit pattern is formed, a defect inspection is appropriately performed using a defect inspection apparatus such as a foreign substance inspection apparatus or a visual inspection apparatus. The defect inspection apparatus outputs information such as the position and size of the defect.

A defect detected by a defect inspection of a certain layer is not always a defect of the layer. For example, if a defect occurs in a certain layer, the film may be raised in a convex shape due to the defect even after the formation of the next layer. Therefore, the defect is also detected in the next layer defect inspection. Therefore, the same wafer is subjected to defect inspection for each layer, and from the results of the defect inspection for each layer, defects detected at the same position between layers may be determined to be the same defect. Here, the same position is a place having an allowable range in consideration of the reproducibility of the XY stage of the defect inspection apparatus, the alignment error of the wafer, and the like. Among the defects at the same position, the first defect detected in a layer is called a net defect, and the defect detected in a subsequent layer is called a carry-in defect. Excluding minute defects that cannot be detected by the defect inspection apparatus, net defects in each layer are defects generated in each layer.

Further, individual defects detected by a defect inspection device are observed with an electron microscope or an optical microscope called a review device, and the modes are classified into foreign matters, remaining resist, and non-opening defects. Alternatively, classification into random defects and non-random defects is performed based on the two-dimensional distribution of defects detected by the defect inspection device in the wafer surface.

As described above, there is a technique for quantitatively evaluating the fatality of a defect included in the information from information on a defect detected by the defect inspection apparatus, information on a net defect, and information on a defect classified in a mode. This technology is called "Semicon Kansai 97 UL
"Yield Monitoring and Analysis" by Hall et al., Author of SI Technology Seminar Proceedings, pp.4 / 42-4 / 47 (1997)
The method is described in “In Semiconductor Manufacturing” and the like, and is referred to as a fatal rate calculating method.FIG. 7 is a diagram showing a fatal rate calculating method.This method uses defect position information and an electrical inspection result. 7 shows the position information of the defect in the wafer surface, that is, the defect map.
Wafer forming electronic device, black circle 31, 34, 3
5 represents a defect, and a white square represents a chip. FIG.
The figure on the right shows the information of non-defective chips and defective chips as a result of the electrical inspection, that is, a non-defective / defective product map.
Is a wafer, "G" is a good chip (Good),
“B” indicates a defective chip (Bad). The information of the defect map and the information of the nondefective / defective product map are compared for each chip, and the lower table 63 in FIG. The number GD of defective and non-defective chips, the number GND of non-defective non-defective products, the number of defective chips and defective chips BD, and the number of defective and non-defective chips BND are determined. The fatality rate KR is obtained from Table 63 in FIG. 7 using (Equation 1).

[0008]

(Equation 1) In the example of FIG. 7, GD is 1 chip, GND is 9 chips, B
D is 2 chips, BND is 1 chip, and the fatality rate KR is 0.63.

[0009]

A defect inspection apparatus such as a foreign substance inspection apparatus or a visual inspection apparatus has a primary object of detecting a defect from a semiconductor integrated circuit in a manufacturing process. Semiconductor integrated circuits have been increasingly miniaturized, and the size of defects to be detected has been reduced. In order to detect minute defects, the defect inspection apparatus has been improved in sensitivity, and the number of defects detected in the defect inspection has increased dramatically. In addition, since a large number of minute defects are included in the detected defects, non-fatal defects that do not become electrical defects are increasing.

[0010] When the number of non-fatal defects increases,
The calculation accuracy of the mortality rate KR according to (Equation 1) was measured by computer simulation. FIG. 13 shows the result. Figure 1
In 3, the horizontal axis represents the number of non-fatal defects, and the vertical axis represents the variation in the criticality calculation result. This result indicates that as the number of non-fatal defects increases, the variability of the fatality rate calculation result increases, that is, the calculation accuracy decreases. Therefore, in order to calculate the fatality rate KR with high accuracy, (Equation 1)
It is important to reduce non-lethal defects before calculating.

[0011]

In order to solve the above-mentioned problems, the present invention effectively reduces non-fatal defects and calculates (Equation 1). Further, using the calculation results, the manufacturing process of the electronic device is managed to maintain a high yield.

First, one solution is a manufacturing process of forming a circuit pattern on a substrate, and a defect inspection process of detecting the position and size of a foreign substance or a pattern defect of the substrate on which the circuit is formed in the manufacturing process. An electrical inspection step of determining whether each device in the substrate is good or defective in the manufacturing process, wherein a defect inspection result obtained in the defect inspection step and an electrical inspection result obtained in the electrical inspection step are compared. A method of manufacturing an electronic device, the method comprising controlling the manufacturing process by using a defect inspection result obtained in the defect inspection process and a defect with respect to the position and size of a foreign substance or a pattern defect set in a device formed on the substrate. The defect occurrence rate of each foreign matter or pattern defect is calculated from the occurrence rate distribution data, and the position of the foreign matter or pattern defect whose defect occurrence rate is larger than a predetermined value is calculated. From the electrical test results were obtained in about 査工, by calculating the kill ratio of the foreign matter or pattern defect possessed by substrate, it is to perform management of the manufacturing process.

Another solution is a manufacturing step of forming a circuit pattern on a substrate, a defect inspection step of detecting a position of a foreign substance or a pattern defect of the substrate on which a circuit is formed in the manufacturing step, and a manufacturing method of the manufacturing method. An electrical inspection step of determining whether each device in the substrate is non-defective or defective in the process, and using the defect inspection results obtained in the defect inspection process and the electrical inspection results obtained in the electrical inspection process to perform the inspection. A method of manufacturing an electronic device for managing a manufacturing process, wherein a foreign substance existing in a critical area is determined based on a defect inspection result obtained in the defect inspection step and fatal / non-fatal map data set in a device formed on the substrate. Alternatively, the position of the pattern defect is calculated, and the position of the foreign matter or the pattern defect existing in the critical area is calculated.
By calculating the fatality rate of foreign substances or pattern defects of the substrate from the electrical inspection results obtained in the electrical inspection process,
The management of the manufacturing process is performed.

The program for executing the above-described analysis method includes defect map data having information on the position and size of a foreign substance or a pattern defect of the inspection object, and setting in a device formed on the inspection object. Input means for inputting defect occurrence rate distribution data with respect to the position and size of the detected foreign matter or pattern defect, and non-defective / defective product map data determined as non-defective / defective for each device in the inspection object; The position and size of the data are compared with the defect occurrence rate distribution data, the defect occurrence rate for each foreign matter or pattern defect in the defect map data is calculated, and the defect occurrence rate of the foreign matter or pattern defect is larger than a predetermined value. Calculating means for comparing a position with the non-defective / defective map data and calculating a fatality rate of the defect map data; A.

Further, another program includes defect map data having information on the position of a foreign substance or a pattern defect of the inspection object, and fatal / non-fatal map data set in a device formed on the inspection object. Input means for inputting non-defective / defective map data for each device in the object to be inspected, and comparing the position of the defect map data with the fatal / non-fatal map data, Calculating means for extracting a foreign matter or pattern defect existing in a fatal area from the map data, collating the extracted foreign matter or pattern defect position with the non-defective / defective map data, and calculating a fatality rate of the defect map data; It is to have.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

First, an in-line defect inspection of a semiconductor wafer will be described with reference to FIG.

Semiconductor wafers are generally manufactured through hundreds of manufacturing steps. In FIG. 2, white squares such as 100 represent each manufacturing process. In the manufacturing process, dozens of defect inspections are performed. Squares shown by oblique lines 101 to 103 are defect inspections. In the defect inspection, the position and size of the defect are output. Then, an electrical inspection 104 is performed at the end of the wafer manufacturing process, and a good product and a defective product are determined for each chip formed on the wafer.

FIG. 1 is a diagram showing an embodiment of a procedure for analyzing defect data of a semiconductor wafer according to the present invention. In FIG. 1, in step 11, defect map data is read. The defect map data is data including information on the position of a defect. Fig. 3 shows an example of defect map data
Shown in Figure 3 shows a defect inspection during the wafer manufacturing process.
This is an example in which five defects are detected. Reference numeral 20 denotes defect map data. The defect map data 20 has five defects, each of which has a serial number and a defect number. For example, the defect with the defect number 1 is located in the chip having the column number 3 and the row number 1, and is located at the coordinates of X 7 and Y 5 in the coordinate system within the chip and has a size of 1.3 micrometers. It means that it is. Numeral 21 shows the defect map data 20 in the form of a wafer map. Here, it is called a defect map. The round frame is the wafer, the white square is the chip,
Black circles 31 to 35 represent defects. Defect map data 20
Defect number 1 is defect 31, defect number 2 is defect 32, defect number 3 is defect 33, defect number 4 is defect 34, defect number 5
Corresponds to the defect 35. Here, the size of the defect can be defined by using, for example, the length of the foreign substance in the longitudinal direction, but is not limited to that case. As another method, it may be defined as √ (ΔAΔB) using the length ΔA of the foreign material in the longitudinal direction and the length ΔB in the direction perpendicular to the longitudinal direction.

FIG. 4 shows the defect map data 20 of FIG.
This is an example in which dots are hit at coordinates in an SI chip. A bold square 50 represents a chip. Black circles 51 to 55 represent the positions of the defects in the chip. Defect map data 20 of FIG.
Defect number 1 is defect 51, defect number 2 is defect 52, defect number 3 is defect 53, defect number 4 is defect 54, defect number 5
Corresponds to the defect 55.

Next, in FIG. 1, in step 12,
Read the failure occurrence rate distribution data. Semiconductor integrated circuits
It is composed of a variety of fine circuits, and when viewed two-dimensionally, there are portions where the circuits are dense and portions where the circuits are sparse.
Therefore, when a defect occurs, in areas where the circuit is dense,
An electrical failure is likely to occur, while an electrical failure is less likely in a sparse circuit. Therefore, the defect occurrence rate distribution data expresses at which position in the semiconductor integrated circuit a defect is likely to be caused by the occurrence of a defect by quantitative information.

FIG. 5 is an example of the failure occurrence rate distribution data. In the example of FIG. 5, the size of the defect is divided into three sections, each having two-dimensional distribution data 41 to 43. The distribution data 41 has a defect size of 0.0 μm or more and less than 1.0 μm, the distribution data 42 has a defect size of 1.0 μm or more and less than 2.0 μm, and the distribution data 43 has , The size of the defect is information of 2.0 micrometers or more. Distribution data 41 to 43
Is an example in which an LSI chip is divided into 16 equal parts in the horizontal direction and four equal parts in the vertical direction.
It has information on the defect occurrence rate.

Next, in FIG. 1, in step 13,
Filter the defect map data. The filtering of the defect map data is a process of excluding non-fatal defect information from individual defect information included in the defect map data and extracting fatal defect information. First, FIG.
The defect map data 20 of FIG. 6 is compared with the defect map data 20 of FIG. For example, the defect map data 2 shown in FIG.
Since the defect number 1 of 0 has a size of 1.3 micrometers, the distribution data 42 is referred to. Further, since this defect is located at the position of the defect 51 in FIG.
13 can be calculated. The result of calculating the defect occurrence rate for each defect is the defect map data 22. In step 13, when the reference threshold rate of fatal or non-fatal, which is a preset threshold value, is set to, for example, 0.10 in the defect map data 22, a defect occurrence rate of 0.10 or more indicates a fatal defect or defect occurrence. A fatal defect is extracted with a rate less than 0.10 as a non-fatal defect. Fatal defects having a defect occurrence rate of 0.10 or more are defect numbers 1, 4, and 5 in the defect map data 22.

Next, in FIG.
Read the non-defective / defective map data. The non-defective / defective map data is a result of judging whether each LSI chip on the wafer is a non-defective product or a non-defective product in an electrical inspection as a final test in a wafer manufacturing process. Reference numeral 62 in FIG. 7 is an example of the non-defective / defective map data. In 62,
“G” indicates a good chip (Good), and “B” indicates a defective chip (Bad).

Next, in FIG. 1, in step 15,
The fatality rate is calculated based on (Equation 1). FIG. 7 is an example showing a method of calculating the fatality rate. The defect map of the defect number 1, the defect number 4, and the defect number 5 determined to be fatal in step 13 from the defect map data 20 is 61. Also,
The non-defective / defective map is 62. The corresponding chips 61 and 62 are compared, and a binary table shown in Table 63 below is created. Table 63 shows that there is one non-defective chip having a defect, eight non-defective chips having no defect, two defective chips having a defect, and one defective chip having no defects. It is shown that. Using (Equation 1) from Table 63,
The fatality rate KR can be calculated as 0.63.

Finally, in FIG. 1, in step 16, the calculation result 0.63 is output.

If all the defects in the defect map data 20 are used for the calculation of the fatality rate, as shown in the lower table 64 of FIG. 8, there are three non-defective chips having defects and non-defective chips having defects. 6 chips are not used. As a result, the fatality rate KR becomes a small value of 0.31, and there is a possibility that an erroneous decision is made as to whether the target defect is a defect that does not need to be dealt with for the production line. The present invention can reduce such erroneous decisions.

Next, an embodiment of a system for executing the present invention will be described. FIG. 9 is a block diagram of a system that executes the present invention. In FIG. 9, 70 is a local area network, 71 is a defect inspection device, 72 is a review device, 73 is an electrical inspection device, 74 is a layout server, 7
5 is an analysis unit. 71 to 75 are connected via a local area network 70, and can exchange data with each other. The analysis unit 75 includes an input unit 76,
It has a storage unit 77, a calculation unit 78, and an output unit 79. The defect inspection device 71, the review device 72, the electrical inspection device 73, and the layout server 74 provide a local area network 70.
Via the input unit 76 via the. The defect inspection device 71 is a device for measuring the position and size of a defect in a wafer surface, and the review device 72 is
A device for observing individual defects using the defect map data detected by the defect inspection device 71;
Is a device for determining non-defective or defective chips, and the layout server 74 is a device for managing CAD data of a mask layout and calculating the defect occurrence rate distribution data shown in FIG. For example, from the defect inspection device 71,
From the detected defect map data and the review device 72,
The defect map data after mode classification, the non-defective / defective map data from the electrical inspection device 73, the layout server 7
From 4, the data on the distribution of the incidence of defects is acquired. The acquired data is stored in the storage unit 77. In the procedure shown in FIG.
2. Step 14 is to store data from the storage unit 77 into the arithmetic unit 7
8 and the calculation of the steps 13 and 15 is performed by the calculation unit 78.

Next, an example of a method of creating the defect rate distribution data shown in FIG. 5 will be described with reference to FIG. The defect occurrence rate distribution data may be created by the layout server 74 shown in FIG. 9 or may be created by the analysis unit 75.

FIG. 10 shows an example 80 in which a part of the CAD data of the mask layout of the semiconductor integrated circuit is enlarged. The hatched portion represents a circuit pattern. Particles are simulated in the layout data on a computer by Monte Carlo simulation. Circles 81 to 89 are generated particles. Particles 81-89 are the same size. The positional relationship between the particles 81 to 89 and the circuit pattern of the layout data is subjected to graphic processing, and it is determined whether or not a short circuit or disconnection occurs in the circuit pattern due to the particles. Since the particles 81 and 82 indicated by oblique lines are connected to a plurality of circuit patterns, it is determined that a short circuit occurs. As a result, of the particles of this size, two out of nine particles have an electrical failure, and the probability of failure is two-ninths. The one that is plotted on the graph is the 91 diamond. Curve 92
Is the result of performing this Monte Carlo simulation with particles of various sizes, with the horizontal axis representing the particle size and the vertical axis representing the defect occurrence rate. 16 in the semiconductor integrated circuit chip
The defect distribution shown in FIG. 5 is obtained by dividing the size of the particle on the horizontal axis into three, and drawing the curve by simulation for each region.

Next, a second embodiment will be described. The above-described embodiment has the position and size information as the defect map data. However, size information may not be available. In this case, even if the defect rate distribution data shown in FIG. 5 is prepared for each defect size, it cannot be used effectively. Therefore, the defect occurrence rate distribution data independent of the size of the defect is created by the following method. Generally, the smaller the defect, the smaller the number of defects, and the smaller the defect, the more the defects. Proceedings "IBMJourn
al of Research and Development ", 1984, 28
“Modeling of defects in i”
According to “ntegrated circuit photolithographic” or the like, it is said that the number D of defects for each size can be represented by (Equation 2).

[0032]

(Equation 2) Here, the coefficient k is a value that satisfies (Equation 3).
n is a value close to 3.

[0033]

(Equation 3) Here, x0 determines the size of a minute defect such as 0.1 micrometer.

Next, the result of integrating the curve 92 and (Equation 3) from x0 to infinity with respect to the magnitude is shown by 44 in FIG.
Is the value of each of the 16 divided areas.

Numeral 45 in FIG. 12 is defect occurrence rate distribution data obtained by binarizing the defect occurrence rate distribution data 44 in FIG.
When only the position information is used without using the size information of the defect map data, the defect occurrence rate distribution data 45 of FIG. 12 is used.

In FIG. 1, at step 11, defect map data is read, and at step 12, the defect occurrence rate distribution data 45 of FIG. 12 is read. Next, step 13
Then, each defect position of the defect map data is compared with the defect occurrence rate distribution data 45, and the defect occurrence rate distribution data 45 is compared.
A defect existing at a value of 1 is determined as a fatal defect, and a defect existing at a value of 0 is determined as a non-fatal defect. At step 14, the non-defective / defective product map data is read, and at step 15, the defect position determined as a fatal defect among the defect map data is compared with the non-defective / defective product map data to calculate the fatality rate. Finally, the fatality rate calculated in step 16 is output.

The two embodiments for calculating the defect fatality rate using the defect map data and the defect occurrence rate distribution data have been described above. The defect inspection is not performed only in one process as shown in FIG. 2, but is performed in a plurality of processes, for example, one process.
It is performed as 01 to 103. Quantitative comparison of the fatality rates of the defects detected in the respective defect inspections is also performed. When the present invention is used for comparison between processes, it is also effective to use different defect occurrence rate distribution data between processes, and conversely, to apply defect occurrence distribution data of a certain process commonly to defect map data of each process. is there.

In the above-described embodiment, the failure occurrence rate distribution data is created by Monte Carlo simulation. However, when there is no layout server 74 for performing the simulation, the analyst looks at the circuit pattern,
A visually dense circuit area has a value of 1 and a sparse circuit area has a value of 0.
As an alternative, the failure occurrence rate distribution data 45 in FIG. 12 may be created and used.

Next, a description will be given of an embodiment of the present invention for calculating a critical rate and managing a manufacturing process of a semiconductor integrated circuit.

FIG. 14 shows an example of a method for comparing defect map data output from a review device and making a decision on a production line. As shown in FIG. 9, the review device 72 classifies the defects detected by the defect inspection device 71 into defect modes such as “defect A” and “defect B”. The defect map data 111 and 112 in FIG. 14 are defect map data for each defect mode assigned by the review device. From the defect map data 111 and 112, the fatality rate is calculated according to the present invention using the defect occurrence rate distribution data 113 and the non-defective / defective product map data 114, respectively.
The result of the calculation of the fatality rate is represented by 115.
In the graph 115, the horizontal axis represents the defect mode assigned by the review device, and the vertical axis represents the result of the fatal rate calculation. In this example, the fatality rate of the defect map data of “defect A” is 0.3, the fatality rate of the defect map data of “defect B” is 0.2,
It can be seen that “defect A” is more likely to cause a defect than “defect B”. Therefore, the production line decided that “Defect A” should be prioritized over “Defect B”.
Focus on technician resources. Here, an example is shown in which a decision is made based on the magnitude of the fatality rate. However, the loss amount YL of the yield is further calculated from (Equation 4) from the fatality rate, and a defect mode in which the loss amount YL of the yield is large is determined. It is also effective to take measures.

[0041]

(Equation 4) Here, KR, GD, BD, GND, and BND have the same definition as (Equation 1).

In the above-described example, the method of calculating the fatality rate for each defect mode, which is the output of the review device, and making a decision is shown. In addition, one of the decision making means is to calculate the fatality rate from the output of the defect inspection device or the review device between the defect inspection processes and to compare the processes.

[0043]

As described above, according to the present invention,
Even when defect inspection is performed using a high-sensitivity defect inspection device that can detect even minute defects, the criticality of defects can be quantified accurately, and decisions are made as to whether the target defect is a defect to be addressed. Can be performed correctly.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a defect data analysis procedure according to the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of a semiconductor wafer.

FIG. 3 is a diagram illustrating an example of defect map data.

FIG. 4 is a diagram showing an example of a defect map in a chip.

FIG. 5 is a diagram illustrating an example of failure occurrence rate distribution data.

FIG. 6 is a diagram showing an example of defect map data with a defect occurrence rate.

FIG. 7 is a diagram illustrating an example of a fatal rate calculation.

FIG. 8 is a diagram illustrating a second example of the fatal rate calculation.

FIG. 9 is a block diagram illustrating one embodiment of a system for performing the present invention.

FIG. 10 is a diagram illustrating a simulation method for calculating a defect occurrence rate.

FIG. 11 is a diagram showing a second example of the failure occurrence rate distribution data.

FIG. 12 is a diagram illustrating an example of binary defect occurrence rate distribution data.

FIG. 13 is a diagram showing a variation in a fatal rate calculation result with respect to the number of non-fatal defects.

FIG. 14 is a diagram illustrating an example of a decision making procedure based on a comparison of the fatality rates.

[Explanation of symbols]

11: Defect map data reading step, 12: Defect occurrence distribution data reading step, 13: Defect map data filtering step, 14: Good / defective map data reading step, 15: Fatal rate calculation step, 1
6: Critical rate output step, 20: Defect map data, 2
1. Defect map at wafer level of defect map data,
22... Defect map data with defect occurrence rate, 31 to 35
... Defect position distribution data, 41 to 43... Defect occurrence distribution data for each defect size, 44... Defect occurrence distribution data independent of defect size, 45.
0: In-chip defect map of defect map data, 51 to 5
5: position of defect in chip, 61: defect map after filtering, 62: non-defective / defective product map, 63 to 64: 2
Base table, 71: Defect inspection device, 72: Review device, 73
... Electrical inspection device, 74 ... Layout server, 75 ... Analysis unit, 76 ... Input unit, 77 ... Storage unit, 78 ... Operation unit, 79 ... Output unit, 80 ... Partial enlarged view of layout data, 81-86 ... Particles, 91: dots of calculation result of defect occurrence rate, 92: defect occurrence rate curve, 100: manufacturing process, 10
1 to 103: defect inspection, 104: electric inspection, 111:
Defect map data of “Defect A”, 112... Defect map data of “Defect B”, 113...
14: good / defective map data, 115: lethality comparison graph.

Continued on the front page F-term (reference) 2G051 AA51 AB02 DA07 EA12 EA14 EA21 EC01 EC02 4M106 AA01 CA38 CA50 DA15 DJ18 DJ20 DJ21 DJ27

Claims (5)

[Claims] 1. A manufacturing process for forming a circuit pattern on a substrate, a defect inspection process for detecting the position and size of a foreign substance or a pattern defect of the substrate on which a circuit is formed in the manufacturing process, An electrical inspection process for determining whether each device in the device is good or defective, and using the defect inspection result obtained in the defect inspection process and the electrical inspection result obtained in the electrical inspection process to perform the manufacturing process. A method of manufacturing an electronic device to be managed, comprising: a defect inspection result obtained in the defect inspection process; and a defect occurrence rate distribution data for a position and a size of a foreign substance or a pattern defect set in a device formed on the substrate. The defect occurrence rate of each foreign matter or pattern defect is calculated, and the position of the foreign matter or pattern defect whose defect occurrence rate is larger than a predetermined value is compared with the electric inspection result obtained in the electric inspection process. From, by calculating the kill ratio of the foreign matter or pattern defects having a substrate, a method for fabricating an electronic device and performs management of the production process. 2. A manufacturing process for forming a circuit pattern on a substrate, a defect inspection process for detecting a position of a foreign substance or a pattern defect of the substrate on which a circuit is formed in the manufacturing process, and An electronic inspection step of determining whether the device is good or defective, and using the defect inspection result obtained in the defect inspection step and the electric inspection result obtained in the electric inspection step to manage the manufacturing process. A method for manufacturing a device, comprising: determining a position of a foreign substance or a pattern defect existing in a critical region from a defect inspection result obtained in the defect inspection process and fatal / non-fatal map data set in a device formed on the substrate. Calculate and calculate the fatality rate of the foreign matter or pattern defect on the substrate from the position of the foreign matter or pattern defect existing in the critical area and the electrical inspection result obtained in the electrical inspection process. In Rukoto, a method for fabricating an electronic device and performs management of the production process. 3. A defect map data having information on the position and size of a foreign substance or a pattern defect of an inspection object, and a defect map data having information on the position and size of a foreign substance or a pattern defect set in a device formed on the inspection object. An input step of receiving the defect occurrence rate distribution data and the non-defective / defective product map data for each device in the inspection object, and the position and size of the defect map data and the defect occurrence rate The distribution data is collated, the defect occurrence rate for each foreign matter or pattern defect in the defect map data is calculated, and the position of the foreign matter or pattern defect where the defect occurrence rate is larger than a predetermined value is compared with the non-defective / defective map data. And calculating a fatality rate of the defect map data by a calculation means. Analysis program. 4. A defect map data having information on a position of a foreign substance or a pattern defect of the inspection object, a critical / non-critical map data set in a device formed on the inspection object, and a defect map data set in the inspection object. An input step of receiving non-defective / defective product data for each device, comparing the position of the defect map data with the critical / non-fatal map data, and determining a critical area from the defect map data. Extracting the foreign matter or pattern defect existing in the defect map data, comparing the position of the extracted foreign matter or pattern defect with the non-defective / defective product map data, and calculating the fatality rate of the defect map data by the calculating means. A defect data analysis program to be executed. 5. The defect occurrence rate distribution data according to claim 3 or the fatal / non-fatal map data according to claim 4 is used to calculate the defect occurrence rate with respect to the size of the defect with respect to the circuit pattern layout data. 5. The non-transitory computer-readable storage medium according to claim 3, wherein the defect data is analyzed.