JPH10214870A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively inspect a semiconductor device being manufactured and to improve a manufacturing yield by inspecting the semiconductor device that is manufactured by a second manufacturing line by an inspection device being set, based on manufacturing line control information. SOLUTION: First, a semiconductor device is manufactured by each kind of manufacturing device 16 in prototype 1. A quality inspection device 3 obtains quality information from a wafer being manufactured and sends it to a check item generation station 9. The number of defects and foreign matters on the wafer is acquired by a foreign matter/appearance inspection device 4. On the other hand, a probe inspection device 5 acquires the electrical characteristics of each chip from the wafer and sends them to the check item generation station 9. A station 11 judges which chip has the defect. Then, a probability PF where a chip with a defect becomes a non-conforming article is calculated, a correlation diagram between the probability PF and a yield Y on the wafer is created, and a guidance station 12 determines an inspection process and its inspection conditions, based on the correlation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique for improving a semiconductor device manufacturing yield, and more particularly to a manufacturing technique for efficiently managing a semiconductor device manufacturing line to improve the manufacturing yield.

[0002]

2. Description of the Related Art A semiconductor device forms a pattern by repeating a film forming process, an exposure process, an etching process, and the like.
It is manufactured by stacking them in layers. The processing dimensions of patterns formed on semiconductor devices are fine, and products already having dimensions of 1 μm or less are widely sold.

[0003] In a semiconductor device having such characteristics, a defective product is likely to occur if a foreign substance is mixed in during the manufacturing process, or if the pattern is chipped or deformed due to a malfunction of the manufacturing device or the like. Therefore, in the field of manufacturing semiconductor devices, it is very important to improve the production efficiency by controlling the manufacturing status to reduce the ratio of defective products and improve the production efficiency.

In general, when a defective product occurs during the manufacture of a semiconductor device, a problem is identified by examining the defective portion and the history of processing the defective portion to improve the yield.
Here, the history refers to a processing machine, a processing date and time, processing conditions (set values and actual values), quality of preceding and subsequent lots, a monitoring result of a processed apparatus, and the like.

As a method of examining a defective portion of a defective product, there is a so-called fail bit analysis method as disclosed in JP-A-61-243378. This analyzes the location of a defect in a chip by looking at the position of a bit that does not work, and from the arrangement of defective cells, the location of the defect in the layers stacked in multiple layers Can be calculated.

However, fail bit analysis can be performed only after the wafer processing step of the semiconductor device is completed and the electrical characteristics can be measured. Therefore, in the fail bit analysis, even if a product defect occurs during manufacturing, there is a disadvantage that the occurrence of the defect cannot be detected until the wafer processing step is completed.

[0007] Therefore, it is effective to carry out an inspection during manufacturing to detect foreign matter and a defect in the appearance of a pattern, analyze the state of occurrence, and take an appropriate countermeasure at an early stage. This method is described in detail in JP-A-3-44054. This is to improve the yield by grasping from the result of the foreign matter appearance inspection the process in which many foreign matter and appearance defects occur and the characteristics of the occurrence pattern.

[0008]

However, according to the above-mentioned prior art, in which step the foreign matter appearance inspection or the like is performed, which area on the wafer is inspected, and how much accuracy (sensitivity)
It is necessary to determine whether or not to perform inspections and what criteria (management criteria) to manage. After setting the predetermined inspection conditions and starting mass production of the semiconductor device, the optimum inspection conditions are determined while appropriately changing the inspection conditions, etc., so that the efficiency required until the data necessary for the analysis is collected. Good inspection is not possible.

Recently, it has been required to manufacture a new semiconductor device at an early stage and at a low cost, and it is necessary to establish an inspection standard earlier than ever. If the establishment of the inspection standard is delayed, the production yield will be affected accordingly and the cost will be increased. In general, the period for manufacturing a semiconductor device usually takes several tens of days. Therefore, according to the above-described conventional technology, it takes a considerable number of days from the start of production to the establishment of an inspection standard.

An object of the present invention is to improve the production yield by effectively inspecting a semiconductor device being manufactured.

[0011]

In order to achieve the above object, the present invention obtains necessary inspection information during a trial production period before starting mass production of semiconductor devices, and mass-produces semiconductor devices using the inspection information. I do. In other words, it analyzes the area where defects occurred in the prototype and the degree of impact on the yield by each generation step, and for example, the size, generation area, observation image, and inspection means of fatal defects for each defect generation step as pre-check items. In summary, in mass production, inspection is performed based on the pre-check items, so that in the manufacture of semiconductor devices, a management standard for inspection results, an inspection process, an inspection area, and the like are determined without delay, and the yield is quickly improved.

More specifically, a step of manufacturing a semiconductor device on a first manufacturing line, a step of inspecting the semiconductor device by an inspection device provided on the first manufacturing line, and an inspection result of the semiconductor device Generating production line management information from the step, setting an inspection device in a second production line based on the generated production line management information, and manufacturing a semiconductor device in the second production line, The above object is achieved by including a step of inspecting a semiconductor device manufactured on the second manufacturing line by an inspection device set based on the manufacturing line management information.

[0013] Thereby, based on the inspection information acquired during the trial production period, the inspection standard at the time of mass production, for example, the location to be inspected especially on the wafer can be effectively set without delay.
Stable production at a mass production site can be realized at an early stage, and the yield can be improved. The present invention will be described in more detail. A step of manufacturing a semiconductor device on a first manufacturing line and a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line. Detecting the electrical characteristics of the chips of the wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line;
Discriminating a chip having a defect from the detection result of the foreign substance inspection device, and from the detection result of the probe inspection device,
Calculating a percentage of the chip determined to have the defect to have a poor electrical characteristic; and inspecting the wafer on the second manufacturing line, in which the process of the step in which the percentage exceeds a predetermined value is completed. The above object is achieved by including the step of setting the frequency to be equal to or higher than the inspection frequency of a wafer for which processing of a process in which the ratio is less than a predetermined value is completed and manufacturing a semiconductor device.

[0014] This makes it possible to judge a process which is likely to cause a defective product due to a defect before mass production is started, and to inspect a relatively large number of wafers processed in the relevant process, so that a defect caused by the occurrence of a defect can be determined. The yield can be improved by suppressing the generation of non-defective products.

Similarly, a step of manufacturing a semiconductor device on a first manufacturing line, and a step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line. Detecting the electrical characteristics of chips on a wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line; detecting results of the appearance / foreign matter inspection device and the probe inspection device; Calculating a correlation between the number of defects and the yield from the detection result; setting a management criterion of an inspection device provided in the second manufacturing line to the number of foreign substances whose yield is within a predetermined value; Manufacturing a semiconductor device on a second manufacturing line, and managing a semiconductor device manufactured on the second manufacturing line by an inspection device that has set the management standard. Sonaere words, it is possible to improve the yield can be set effective amount of foreign matter to be managed by the inspection apparatus before starting mass production.

In this case, the appearance / foreign matter inspection apparatus determines the size of a defect on a wafer, calculates the correlation between the number of defects and the yield for each predetermined defect size, and provides an inspection apparatus capable of detecting the defect size. Set up a second production line,
It is preferable to set the number of defects for each defect size for which the yield is within a predetermined value as a management standard of the set inspection device. Calculating the correlation between the number of defects and the yield for each type of defect, setting an inspection device capable of detecting the type of the defect in the second production line, and setting the yield as a management standard for the set inspection device. It is preferable to set the number of defects for each defect type within the value.

Similarly, a step of manufacturing a semiconductor device on the first manufacturing line, and a defect on a wafer forming the semiconductor device is detected by an appearance / foreign matter inspection device provided on the first manufacturing line. Calculating the defect occurrence density on the wafer from the detection result of the appearance / foreign matter inspection device, and inspecting the region provided with the second production line so that the defect occurrence density is equal to or more than a predetermined value. Setting, a step of manufacturing a semiconductor device on the second manufacturing line, and a step of inspecting an area of the set semiconductor device by an inspection apparatus provided in the second production line, Since the area on the wafer to be inspected by the inspection apparatus can be set before the start, the area where defects are likely to occur can be effectively managed, and the yield can be reduced without reducing the throughput. It is possible to improve.

In this case, the appearance / foreign matter inspection apparatus determines the size of the defect on the wafer, calculates the defect occurrence density on the wafer for each predetermined size, and determines whether the defect occurrence density of one of the defect sizes is a predetermined value. In the above case, it is preferable to set an inspection apparatus capable of detecting a defect size having the predetermined value or more in the second production line.

The appearance / foreign matter inspection apparatus determines the type of the defect on the wafer, calculates the defect occurrence density on the wafer for each predetermined defect type, and calculates the defect occurrence density of any of the defect types. When the value is equal to or more than the predetermined value, it is preferable to set an inspection apparatus capable of detecting the type of the defect having the value equal to or more than the predetermined value in the second manufacturing line.

According to another aspect of the present invention, a step of attaching a defect of a predetermined size to the shape of each step in the process of manufacturing a semiconductor device and simulating the subsequent manufacturing process; A step of storing a connection relation of each part forming the simulated shape by attaching the connection relation; a connection relation of each of the stored parts; and a connection relation of each part forming the simulated shape without generating a defect. A step of judging an object having an inconsistency in connection relationship as an abnormality, and setting an inspection apparatus capable of detecting a defect of a predetermined size in a step judged as abnormal by the simulation. The above object can be achieved.

Thus, since any phenomenon can be simulated before mass production starts, the yield at a mass production site can be improved by predicting and managing a phenomenon that becomes defective due to the attachment of a defect.

In this case, it is preferable to simulate the defect attachment positions differently and set an inspection area of the inspection apparatus so as to inspect the attachment position determined to be abnormal.

In addition, it is preferable to set an inspection apparatus which can simulate each of the defects with different sizes, and detect the size of the defects in a process determined as abnormal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a system diagram showing the concept of the present invention.

FIG. 1 is composed of a stage of trial production 1 for establishing the optimum manufacturing conditions of a designed device and a stage of mass production 2 on the assumption that the device is actually sold as a product. The prototype 1 and the mass production 2 may be performed on the same line, or may be performed on different lines. However, there may be some overlap in time, but prototype 1 is mass-produced 2
Of course is done before.

The prototype 1 includes various manufacturing apparatuses 15 for performing processes such as film formation, exposure, etching and the like on a loaded wafer, and a quality inspection apparatus 3 (for example, a wafer) for inspecting the quality of wafers processed by the manufacturing apparatus. Foreign matter / appearance inspection apparatus 4) for inspecting the above defects or foreign matter, probe inspection apparatus 5 for inspecting the electrical characteristics of the wafer after all wafer processing steps have been completed, and quality inspection apparatus 3 result (foreign matter / appearance inspection) 4) and a manufacturing result (a result of the probe inspection 5) to generate necessary inspection information, and a database 10 for storing the inspection information generated by the check generation item station 9. Is done.

The mass production site 2 forms a film on the input wafer,
Various manufacturing apparatuses 15 for performing processes such as exposure and etching;
A quality inspection apparatus 3 for inspecting the quality of the wafer processed by the manufacturing apparatus (for example, a foreign substance / visual inspection apparatus 4 for inspecting a defect or a foreign substance on the wafer); A probe inspection device 5 for inspecting characteristics, a database 11 for storing inspection information generated in the prototype 1, and a management standard, a process to be inspected, a location on a wafer to be inspected, and the like based on the inspection information stored in the database. And a guide station 12 for outputting.

The database 10 of the prototype 1 and the database 12 of the mass production site 2 are connected via a communication line 14. The databases included in the prototype 1 and the mass production base 2 are not necessarily required, and the guidance station 12 of the mass production base outputs necessary information based on the inspection information generated by the check item generation station 9 of the prototype 1. If there is no problem. For example, prototype 1 and mass production base 2
Or the information of the prototype 1 may be transferred to the mass production base 2 via a storage medium.

Next, an example of managing the mass production base 2 based on the inspection information (process to be inspected) acquired in the prototype 1 will be described.

FIG. 2 is a flowchart showing a process from obtaining the inspection information (process to be inspected) in the prototype 1 to applying the inspection information to the mass production 2.

First, in prototype 1, a semiconductor device is manufactured using various manufacturing apparatuses 15 (step 101).

The quality inspection device 3 acquires quality information from the wafer being manufactured and transmits it to the check item generation station 9 (step 102). In the present embodiment, the defect on the wafer and / or the number of foreign particles are obtained by using the foreign particle / visual inspection device 4.

The inspection result of the foreign matter / visual inspection apparatus 4 is shown in FIG.
As shown in FIG. 7, the information includes items such as a product type name, a process name, a lot number, a wafer number, a defect coordinate (x, y), a defect type, a defect size, an observed image, and a defect occurrence site. FIG. 3 shows information on the wafer number 1 stored in the lot number L001 of the semiconductor device HM001. After the process of the process P1, the defect coordinates (1000, 2000) indicate the defect type A and the defect size 1
0 indicates that a defect was detected. However, the type and size of the defect are not necessarily required, and it is sufficient that the presence or absence of the defect can be determined. Here, the defect coordinates refer to a flat portion of the wafer 20 (referred to as an orientation flat 21) as shown in FIG.
Are set parallel (X-axis 22) and perpendicular (Y-axis 23). However, this is merely an example, and other coordinate systems may be used, and even if the wafer itself does not have an orientation flat, it is sufficient that the coordinate system is described in a coordinate system that is well-aligned.

On the other hand, the probe inspection device 5 acquires the electrical characteristics of each chip from the wafer and transmits the acquired electrical characteristics to the check item generation station 9 (step 103).

As shown in FIG. 5, the inspection result of the probe inspection device 5 includes a product name, a lot number, a wafer number, chip coordinates (m, n), and information on the quality of the corresponding chip. Here, the chip coordinates mean chip positions on the wafer. In FIG. 5, the lot number L of the semiconductor device HM001 is shown.
It shows information on the wafer number 1 stored in 001, and the pass / fail status of each chip after the process of the process P1 is indicated by “1” and “0”. For example, “1” is displayed for the chip at the chip position (1, 3), indicating that the chip is defective.

Next, check item generation station 11
Determines which chip has a defect on the basis of the inspection result of the foreign matter / visual inspection apparatus 4, information on the chip layout of the wafer stored in advance, and equations (1) and (2) (step 104). . The information relating to the chip layout of the wafer may include information on the chip horizontal width XW, the chip vertical width YL, the number of horizontal chips, and the number of vertical chips as shown in the type information table 30 shown in FIG. It should be noted that the present invention is not limited to the equations (1) and (2), and it is only necessary to be able to determine which chip has a defect detected by the foreign matter / appearance detection device 4. The calculated chip coordinates (m ′, n ′) must correspond to the coordinates of the probe inspection device 5.

M ′ = [x / XW] +1 Expression (1) n ′ = [y / YL] +1 Expression (2) (m ′, n ′): chip coordinates (x, y): defect coordinates [ x] indicates the largest integer not exceeding x.

Next, the chip coordinates (m ', n') having the defect determined in step 104, the result of the pass / fail judgment for each chip (m, n), which is the detection result of the probe inspection device 5,
Then, the probability PF of a defective chip becoming a defective product is calculated using Expression (3) (Step 105). The calculation of the probability PF that a chip having a defect becomes a defective product is performed for wafers of the same type and inspected in the same process.

PF = (number of defective chips in defect-producing chips) / (number of defect-producing chips) Expression (3) Accordingly, a chip defect rate graph 40 for each process as shown in FIG. 7 can be created. Here, the horizontal axis 41 indicates the process, and the vertical axis 42 indicates the probability PF of a defective chip becoming defective. In this case, the value of PF in step P4 is close to 1.0.
This indicates that if a defect occurs, the probability of becoming a defective chip is high. It should be noted that the step-by-step chip failure rate graph 40 shown in FIG.
It may be recorded as a product name, a process name, and a probability PF that a chip having a defect in each process becomes a defective product.

Next, the yield Y is defined by equation (4).
As shown in FIG. 9, a correlation diagram 70 between the established PF and the yield Y on the same wafer is created, and
Next regression equation 73 is obtained (step 106).

Y = (number of non-defective chips) / (number of target chips) Expression (4) In the check item generation station 9, information on the established PF and the yield Y is analyzed as shown in FIG.
Record as 0. In the analysis result table 90, the type name,
The process name includes the lot number, wafer number, PF, and Y.

As described above, the inspection information (PF value of each process shown in FIG.
Correlation information between the established PF and the yield Y shown in FIG. 10) is generated.

Next, at the mass production site 2, the already acquired
The guidance station 12 determines an inspection process and its inspection conditions based on the correlation between the PF, the established PF, and the yield Y (Step 107). That is, in the guidance station 12 of the mass production base 2, the desired yield is set using FIG. 10, the corresponding established PF is calculated from the linear regression equation 73, and the manufacturing apparatus in the process more than the established PF is focused. To manage. Specifically, the inspection frequency or / and the inspection area of the inspection device are increased for the process having the established PF equal to or more than the predetermined value.

As described above, the process that has a large influence on a defective chip due to a defect (a process with a large established PF) is inspected and intensively inspected by increasing the inspection frequency or / and the inspection area of the inspection apparatus so that the defect is not generated. Therefore, the number of defective chips due to defects can be reduced and the yield can be improved.

Next, another example of extracting a process to be inspected from the inspection information collected in the prototype 1 is shown in FIG.

First, in prototype 1, a semiconductor device is manufactured using various manufacturing apparatuses 15 (step 201).

Next, when a problem occurs during the manufacturing, the process in which the problem occurred and the type of the problem are registered in the check item generation station 9 and the number of occurrences of each is recorded (step 202). Here, the types of problems are problems caused by the device structure, problems caused by the manufacturing apparatus, and the like. FIG. 12 shows an example of data to be stored. (1) The chip width XW and the chip length YW are calculated by the following equations (1) and (2).
In drawing a diagram showing a wafer as shown in FIG. 4, the number of vertical chips and the number of horizontal chips are required. In many cases, as shown in FIG. 4, the arrangement of chips differs in the number of chips processed for each row. Therefore, it is better to specify a region that is not actually processed in a region where the number of vertical chips and the number of horizontal chips are hardly set. The problem due to the device structure includes, for example, a large step on the base, a focus being lost at the time of exposure depending on a place, and a desired pattern cannot be processed. In such a case, measures are taken by observing in detail how the shape is deviated from the desired shape. Therefore, observation using an SEM is preferable. The problem caused by the manufacturing apparatus is, for example, that foreign matter is generated from the apparatus and the foreign matter adheres to the wafer and cannot be processed into a desired shape. Unlike the problem caused by the device structure, it is not known when the failure of the device occurs. Therefore, it is necessary to increase the inspection frequency and quickly detect the occurrence of the device abnormality.

Next, in the guidance station 12 of the mass production base 2, based on the stored data, the setting is made so that the inspection in which the number of occurrences of the problem is equal to or more than the predetermined number is mainly performed (step 203).

For example, when there are many problems caused by the device structure, the inspection is managed by a SEM visual inspection apparatus having high inspection sensitivity, and when there are many problems caused by the manufacturing apparatus, the inspection frequency is managed (step 204). ).

As described above, if a process that is likely to cause a problem from the start of mass production is managed by using an optimum inspection device according to the type of the problem, the same problem that occurred in the prototype 1 can be found at an early stage, and the yield is improved. Can be done.

By associating the information with an area on the wafer to be inspected (an area where a problem has occurred) and an inspection sensitivity required for the inspection apparatus, the inspection can be effectively performed in a partial area on the wafer. Therefore, the yield can be improved without lowering the throughput.

Next, an example in which inspection information (conditions to be inspected) is acquired in prototype 1 and the inspection information is applied to mass production 2 will be described with reference to FIG.

In FIG. 13, steps 301 to 303 are the same as those in FIG. FIG.
In step 304, in step 304, the check item generation station 9 uses the inspection result of the foreign matter / visual inspection apparatus 4 and the inspection result of the probe inspection apparatus 5, as shown in FIG. And a linear regression equation 73 is obtained from these plots. Note that the yield Y is calculated using the aforementioned equation (4).

As described above, in the prototype 1, the mass production base 2
, The necessary information (correlation information between the number N of foreign particles and the yield Y shown in FIG. 14) is generated.

Next, the guidance station 12 of the mass production base 2 determines the inspection conditions based on the correlation between the number N of foreign particles and the yield Y that have already been obtained (step 305).

That is, at the mass production site 2, the desired yield is set using FIG.
It is calculated from the following regression equation 63, and the manufacturing apparatus is managed so that no foreign matter exceeding the number N of foreign matters is generated in the corresponding process. In this case, it is desirable to add the sensitivity of the inspection apparatus used in the prototype 1 as information and perform the inspection with the same sensitivity as the prototype 1.
If the conditions (management criteria) to be managed in each process are known before the start of mass production, stable mass production can be performed early and the yield can be improved.

For example, if the foreign matter / appearance inspection device 4 generates foreign matter having a size of about a pattern processing size at the time of film formation,
The management of the film forming apparatus is strict. In addition, since the gate processing accuracy is poor and the desired shape is not obtained, if the desired transistor characteristics cannot be obtained, it is necessary to manage the shape after the gate processing. In this case, even a deviation of about 1/10 of the processing dimension may greatly affect characteristics.

Next, an example will be described in which inspection information (area to be inspected) is acquired in the prototype 1 and the inspection information is applied to the mass production 2.

FIG. 15 is a flowchart showing a process from acquiring the inspection information (inspection area) in the prototype 1 to applying the inspection information to the mass production base 2. Steps 401 to 402 are the same as those in FIG. 2 and will not be described.

In FIG. 15, as shown in FIG. 16, the defect position 101 is spotted on the area indicating the wafer from the inspection result during the manufacture of the prototype 1 (the detection result of the foreign matter / visual inspection apparatus 4) (step 403). . At this time, J inspection results for a plurality of wafers performed in the same process may be superimposed. As shown in FIG. 16, an area in which the position of a defect is spotted on an area indicating a wafer is referred to as a defect map 100. A virtual mesh 102 is cut on the defect map, and a number (p, q) is assigned to each mesh. Which mesh each defect belongs to is determined in the same manner as Expressions (1) and (2) (Step 404). Here, L is a mesh pitch. p = [x / L] +1 Expression (5) q = [y / L] +1 Expression (6) From the results of Expressions (5) and (6), the number of defects N (p, q) in each mesh ) Is obtained (step 405). At this time, as shown in FIG.
4 should be shown together. The check item generation station 9 records this result in a format as shown in FIG.
In FIG. 17, a product type name, a process name, a defect type, and a defect-prone area are recorded as a defect map table 110.

As described above, the inspection information is obtained in the prototype 1.

Next, the guidance station 12 of the mass production base 2 sets an inspection area based on the above-described inspection information (step 406). That is, a constant threshold value D is set in Expression (7), and an area that satisfies the relationship of Expression (7) is inspected. Here, a defect map may be created for each defect type. L is arbitrary, but is preferably about 1/10 of the chip width XW. D is preferably two to three times the average defect density per sheet.

N (p, q) / (L × L × J)> D Equation (7) Since the area (p, q) satisfying the equation (7) has a high defect generation density, a defect in that area is obtained. , The occurrence of defects on the entire wafer can be suppressed, and the yield can be improved. In particular, when the prototype 1 and the mass production base 1 are on the same production line, defects caused by the production apparatus can be suppressed, and the yield can be greatly improved.

The area to be inspected described above is given to an inspection apparatus 140 as shown in FIG. The inspection device 140 includes a data interface 141, a control unit 14,
2. It comprises an inspection stage 143, a detection unit 144, a man-machine interface 145, and a display unit 146.
The control unit 142 calculates a stage control amount based on the area (p, q) to be inspected received by the data interface 141, and controls the inspection stage 143. As a result, the inspection apparatus 140 automatically checks the area (p,
Check q). Further, it is preferable that the inspection apparatus 140 inspects a predetermined number of points on the wafer in addition to the area (p, q) to be inspected. Thereby, the inspection on the wafer can be performed uniformly, and the inspection on a part of the area on the wafer can be focused.

As shown in FIG. 19, the display unit 146 displays an inspection area 151 and a defect detection position 152 on the guidance screen 150, and displays an image 153 of the defect detected in the prototype 1 in the inspection area and a mass production. Preferably, the image 154 of the defect detected in step 2 is also displayed. As a result, it is possible to compare the image of the defect detected during the trial production with the image of the defect detected during the mass production, and determine whether the defect occurring during the mass production has been experienced during the trial production.

As described above, the inspection device 140 is provided with
Since the area to be inspected is known in advance for each defect type, the inspection efficiency is high.

Next, FIG. 20 shows an example in which a process to be inspected at the mass production site 2 is determined based on the inspection result during the manufacture of the first prototype.

First, after the formation of the layers corresponding to the respective photomasks is completed in the prototype 1, a virtual defect is generated by a cross-sectional shape simulator, and it is determined whether or not the device shape obtained by the normal manufacturing process after the defect has been generated is normal. A judgment is made (step 501). The defects to be generated are various defect sizes,
Handle the defect attachment position. Some cross-sectional shape simulators for generating virtual defects (foreign matter) are already commercially available, and are easy to realize. For example, PRADISEWORLD of NTT Fanet Systems, Inc.
There is.

The method of assigning the parameter of the defect size is に 対 し て with respect to the minimum processing line width of each layer, the same as ／, and twice. The attachment position is randomly generated in the simulated area. The number of cases generated here is assumed to be SF.

Next, a method for determining whether the device shape is normal or abnormal will be described.

A simulated normal shape is prepared in advance without generating a defect, and the connection relation of each part is recorded (step 502). This can be recorded by assigning a serial number to each part, and the connection is represented by a set of numbers of the two parts.

On the other hand, after a defect is generated and simulated, the connection relation of each part is recorded (step 503). Here, the connection with the defect is omitted.

Next, if the connection between the defect and the normal shape is different from the connection between the defect and the normal shape, it is determined that an abnormality has occurred in the shape. (Step 504). FIG. 21 shows an example of the simulation. FIG. 21 shows an example in which a defect 122 is generated on a normal part 121, and the part 123 is divided into a part 123 and a part 124 under the influence of the defect 122, and a new connection between the part 121 and the part 124 is generated. FIG. 22 shows the connection relationship in this case. In FIG. 22, the normal connection relationship is (12
1,123), and the connection relationship at the time of defect attachment is (121,123).
123) and (121,124). The check item generation station 9 compares the connection relationships shown in FIG. 22 to determine that a shape abnormality has occurred.

In this way, the number AF in which the shape abnormality has occurred is determined, and the abnormality occurrence rate AP is calculated using equation (8). That is, the abnormality occurrence rate A for each layer and each defect size
Simulate P (step 505).

AP = AF / SF Expression (8) The check item generation station 9 compares the result with FIG.
Is recorded as a simulation result table 130 as shown in FIG. In FIG. 23, the vertical 131 indicates the layer and the horizontal 132 indicates the defect size, and the corresponding AP is recorded in each cell 133.

As described above, the inspection information is obtained in the prototype 1.

Next, at the guidance station 12 of the mass production base 2, inspection conditions are set based on the above-described inspection information (step 506). In other words, a desired yield Y0 is set, and when there are n layers listed on the vertical axis in FIG. 23, the process having 1-AP less than the nth root of Y0 is mainly inspected. Specifically, management is performed by an inspection device that can detect a defect size for a corresponding process. This is because when the AP of the n-th layer is written as AP (n), Y0 is Y0 = (1−AP (1)) (1−AP (2)) (1−AP (n)) Formula (1) 9) and comparing the nth root of Y0 with 1-AP (i) (where i is a number from 1 to n), the fact that 1-AP (i) is smaller is This indicates that the possibility of occurrence of a defect is high. Therefore, it is necessary to manage a foreign substance having a size that is considered to cause a problem in the performance of the product by a simulation or the like.

As a result, since it is possible to grasp how large a defect should be managed in each layer, stable mass production can be performed at an early stage, and the yield can be improved. Further, since various problems that may occur at the mass production base can be considered in advance by simulation, unexpected unexpected problems can be prevented.

Finally, a more specific example will be described below.

For example, in FIG. 21, a simulation is performed assuming a defect caused by the device, and a simulation result is obtained in which, for example, a foreign matter having a size of 1 μm causes a problem in product performance in a contact hole forming step. Pre-check item database 10
Register with. The contents to be registered are assumed defects (whether due to the device or the device structure), the process name, the size of the foreign matter in question, the shape obtained by simulation and the image ID indicating the shape, the phenomenon that occurred, and the inspection. Area to be used. However, in the case of simulation, knowledge about the region to be inspected on the wafer is often not obtained. This data is copied to the pre-check database 11 to generate a pre-check list. In the prior checklist, the type of inspection is defined according to the assumed failure. Here, since a defect due to the apparatus is assumed, a foreign substance inspection is performed. The phenomenon is a non-opening of the contact hole, and the management size is, for example, 1 μm. Further, the image ID is managed so that the simulation shape can be searched. Also, if no knowledge is obtained about the area to be inspected,
The entire wafer should be inspected. The guidance station 12 instructs the inspection type (foreign matter inspection), management criteria (foreign matter size 1 μm or more), inspection process (contact hole forming process), and inspection location (entire wafer surface) based on the preliminary check list 13.

Further, when based on an actually occurring case,
The detected means, phenomenon, size, image ID, location where the error occurred, and the like are registered in the pre-check item database 10. The preliminary check list 13 is generated based on the information. Here, since the short circuit between the wirings is found at the chip position (12, 13) (13, 14) by the SEM, the guidance station gives an instruction to inspect the corresponding process and the corresponding portion by the SEM.

FIG. 25 shows the flow of this processing. If this is registered as a pre-check item, whether it is a simulation or an actual case, the subsequent processing is the same.

In the example described so far, the check item generation station 9 performs the analysis based on the inspection result. However, the check item generation station 9 merely collects the inspection result, and the guidance station 12
However, there is no problem even if all analyzes are performed.

[0085]

As described above, according to the present invention, based on the inspection information acquired during the trial production period, the inspection standard at the time of mass production can be set effectively, so that stable production at the mass production base can be quickly performed. It can be realized, and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a system diagram of the present invention.

FIG. 2 is a flowchart showing an example of an operation mode of the present invention.

FIG. 3 is a diagram showing an example of information acquired from an appearance / foreign matter inspection device.

FIG. 4 is a diagram showing coordinates on a wafer.

FIG. 5 is a diagram showing an example of information acquired from a probe inspection device.

FIG. 6 is a diagram showing an example of information on a wafer.

FIG. 7 is a view showing an established PF for each process.

FIG. 8 is a view showing an established PF for each process.

FIG. 9 is a correlation diagram between yield Y and establishment Y.

FIG. 10 is a diagram showing a correlation between yield Y and probability Y.

FIG. 11 is a flowchart showing an example of an operation mode of the present invention.

FIG. 12 is a diagram showing a problem occurrence situation for each process.

FIG. 13 is a flowchart showing an example of an operation mode of the present invention.

FIG. 14 is a correlation diagram between yield Y and the number N of defects.

FIG. 15 is a flowchart illustrating an example of an operation mode of the present invention.

FIG. 16 is a view showing a defect occurrence area on a wafer.

FIG. 17 is a view showing information on a defect occurrence area on a wafer.

FIG. 18 is a view showing an appearance / foreign matter inspection apparatus of the present invention.

FIG. 19 is a diagram showing an example of a display screen of the present invention.

FIG. 20 is a flowchart showing an example of an operation mode of the present invention.

FIG. 21 is a diagram showing an example of a simulation result of the present invention.

FIG. 22 is a view showing information on a simulation result of the present invention.

FIG. 23 is a diagram showing information on a simulation result of the present invention.

FIG. 24 is a system diagram of the present invention.

FIG. 25 is a flowchart showing an example of an operation mode of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Prototype line 2, 6 ... Mass production line 3, 7 ... Quality inspection device 4, 8 ... Foreign material appearance inspection device 5 ... Probe inspection device 9 ... Check item generation station 10, 11 ... Preliminary check item database 12 ... Guidance station 20 ... Wafer 21 ... Orifice flat 22 ... X axis of coordinate system that describes defect position 23 ... Descriptive position of defect Y-axis of coordinate system 24: chips processed on wafer 30: type information table 40: chip failure rate graph by process 41: horizontal axis (process) 42 of chip failure rate graph by process 42 ··· Vertical axis (PF) of chip defect rate graph by process 50 ··· Defect occurrence rate table 60 ··· Correlation chart between number of defects and yield 61 ··· Horizontal axis of correlation chart between number of defects and yield Number) 62 ・ ・ ・ missing Vertical axis of the correlation diagram between the number and the yield (yield) 63... Linear regression line of the correlation between the number of defects and the yield 70... Correlation diagram between the chip failure rate and the yield by process 71. The horizontal axis of the correlation diagram between the yield and the yield (chip failure rate by process) 72: the vertical axis of the correlation diagram between the chip failure rate and the yield by process (yield) 90: analysis result table 100: defect map 101 Defect position 102: virtual mesh on defect map 103: process name on defect map 104: defect type on defect map 110: defect map table 121: device layer 1 122: virtual foreign matter on device layer 121 123: wiring pattern at one of device layers 124: part where device layer 123 is divided 130: simulation Table 131: Semiconductor device layers in the simulation result table 132: Defect size in the simulation result table 133: Incidence rate for each layer in the simulation result table 140: Inspection apparatus. 141 data interface 142 control part 143 inspection stage 144 detection part 145 man-machine interface 146 display part 150 guidance screen 151 inspection area 152 ... Defect detection position 153 ... Image of defect detected in prototype 1 154 ... Image of defect detected in mass production 2 160 ... Semiconductor manufacturing line

Claims (11)

[Claims] 1. A step of manufacturing a semiconductor device on a first manufacturing line, a step of inspecting the semiconductor device by an inspection device provided on the first manufacturing line, and a manufacturing line based on a result of the inspection of the semiconductor device. Generating management information; setting an inspection device on a second manufacturing line based on the generated manufacturing line management information; manufacturing a semiconductor device on the second manufacturing line; Inspecting a semiconductor device manufactured on the second manufacturing line by an inspection device set based on management information. 2. A step of manufacturing a semiconductor device on a first manufacturing line, and a step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line. Detecting electrical characteristics of chips on a wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line; and determining a chip having a defect from the detection result of the appearance / foreign matter inspection device. Calculating the percentage of the chip determined to have the defect to have poor electrical characteristics based on the detection result of the probe inspection apparatus; and The semiconductor device is set by setting the inspection frequency of the wafers having completed the processing of the process having the value equal to or greater than the inspection frequency of the wafer having completed the processing of the process having the ratio less than the predetermined value. The method of manufacturing a semiconductor device characterized by comprising a step of producing. 3. A step of manufacturing a semiconductor device on a first manufacturing line, and a step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line. Detecting electrical characteristics of chips on a wafer forming the semiconductor device by a probe inspection device provided on the first manufacturing line; detecting results of the appearance / foreign matter inspection device and detecting the probe inspection device Calculating a correlation between the number of defects and the yield from the result; setting a management criterion of an inspection device provided in the second manufacturing line to the number of foreign substances whose yield is within a predetermined value; Manufacturing a semiconductor device on the second manufacturing line, and managing the semiconductor device manufactured on the second manufacturing line by the inspection device that has set the management standard. The method of manufacturing a semiconductor device according to claim Rukoto. 4. An inspection apparatus capable of detecting the size of a defect on a wafer, calculating a correlation between the number of defects and a yield for each predetermined defect size, and detecting the defect size. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the number of defects is set for each of the second manufacturing lines, and the number of defects for each defect size whose yield is within a predetermined value is set as a management standard of the set inspection apparatus. . 5. An inspection apparatus capable of detecting a type of a defect on a wafer, calculating a correlation between the number of defects and a yield for each predetermined defect type, and detecting the type of the defect. 5. The semiconductor device according to claim 3, wherein the semiconductor device is set in a second manufacturing line, and the number of defects for each type of defect whose yield is within a predetermined value is set as a management standard of the set inspection apparatus. Manufacturing method. 6. A step of manufacturing a semiconductor device on a first manufacturing line, and a step of detecting a defect on a wafer forming the semiconductor device by an appearance / foreign matter inspection device provided on the first manufacturing line. Calculating the defect occurrence density on the wafer from the detection result of the appearance / foreign matter inspection device; and setting the inspection device provided in the second manufacturing line to inspect an area where the defect occurrence density is equal to or more than a predetermined value. A semiconductor device comprising: a step of manufacturing a semiconductor device on the second manufacturing line; and a step of inspecting an area of the set semiconductor device by an inspection device provided on the second manufacturing line. Device manufacturing method. 7. The appearance / foreign matter inspection apparatus determines a size of a defect on a wafer, calculates a defect occurrence density on the wafer for each predetermined size, and the defect occurrence density of any one of the defect sizes is equal to or more than a predetermined value. 7. The method according to claim 6, wherein an inspection device capable of detecting a defect size equal to or larger than the predetermined value is set in the second manufacturing line. 8. The appearance / foreign matter inspection apparatus determines a type of a defect on a wafer, calculates a defect occurrence density on the wafer for each predetermined defect type, and calculates a defect occurrence density of one of the defect types. 8. The method of manufacturing a semiconductor device according to claim 6, wherein an inspection device capable of detecting a type of a defect having the predetermined value or more is set in the second manufacturing line when the value is equal to or more than the predetermined value. 9. A step of attaching a defect of a predetermined size to the shape of each step in the process of manufacturing the semiconductor device and simulating the subsequent manufacturing process, and forming the simulated shape by attaching the defect. Storing the connection relation of each part; comparing the stored connection relation of each part with the connection relation of each part constituting the simulated shape without generating a defect; Determining that the semiconductor device is abnormal, and, for the process determined to be abnormal by the simulation, setting an inspection apparatus capable of detecting the defect having the predetermined size and manufacturing the semiconductor device. Manufacturing method of a semiconductor device. 10. The inspection area of the inspection apparatus according to claim 9, wherein the positions of the defects are differently simulated, and an inspection area of the inspection device is set so as to inspect the adhesion position determined to be abnormal. A method for manufacturing a semiconductor device. 11. An inspection apparatus capable of simulating each of the defects with different sizes, and setting an inspection apparatus capable of detecting the size of the defect for a process determined to be abnormal. The manufacturing method of the semiconductor device described in the above.