JP2001250949A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the threshold voltage of a reverse staggered TFT using stresses of thin films. SOLUTION: The product of a stress and the film thickness of a first insulation layer on electrodes formed on a substrate, the product of a stress and the film thickness of an active layer composed of a crystalline semiconductor film having a tensile stress on the first insulation layer, and the product of a stress and the film thickness of a second insulation layer provided on the active layer, are set for adequate values to control the threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an integrated circuit using a thin film transistor on a substrate. For example, the present invention relates to a configuration of an electro-optical device represented by a liquid crystal display device and an electronic apparatus equipped with the electro-optical device.

[0002]

2. Description of the Related Art A semiconductor device represented by an active matrix type liquid crystal display device has been developed in which a large number of TFTs (thin film transistors) are arranged on a substrate. The TFT is formed by stacking at least an active layer made of an island-shaped semiconductor film, a first insulating layer provided on the substrate side of the active layer, and a second insulating layer provided on the opposite side of the active layer. It has a structure.

A structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer via the first insulating layer is called an inverted stagger or bottom gate type.
The present description all relates to this inverted staggered structure.

By the way, among the several characteristic parameters representing the TFT characteristics, the field-effect mobility and the threshold voltage are used as a measure of good characteristics.

With the goal of realizing high field-effect mobility,
The TFT structure and its manufacturing process have been carefully studied from theoretical analysis and empirical aspects. It has been considered that a particularly important factor is to reduce the bulk defect density in the semiconductor layer and the interface state density at the interface between the semiconductor layer and the insulating layer as much as possible.

[0006] The type of device is distinguished by setting a threshold voltage, which is the most important parameter in device design. TFTs that require a gate voltage to be applied for conduction are enhancement-type (Enhance
ment) or normally-off TF
T, a TFT that requires a gate voltage to be applied in order to prevent conduction is called a depletion type (Depletion) or a normally-on type (Normally-On) TFT.

In general, the threshold voltage, enhancement type TFT, and depletion type TFT are defined as follows. As shown in FIG. 1a, in the gate voltage-drain current characteristic curve, the tangent line a of the square characteristic region of the characteristic curve
The intersection of the horizontal axis (gate voltage axis) is defined as the threshold voltage. Further, the enhancement type TFT is defined as an n-channel type TFT whose threshold voltage is zero or positive voltage, or a p-channel type TFT whose threshold voltage is negative voltage. Similarly, the depletion type TFT is replaced with an n-channel type TFT having a negative threshold voltage or a p-channel type TFT having a threshold voltage of zero or positive voltage.
Defined as T.

As a method of controlling the threshold voltage, a channel doping method of introducing an impurity into a semiconductor film on a gate insulating layer by ion implantation or a method of flowing an impurity gas at the time of forming a semiconductor film is generally used. ing.

In the case of the enhancement type TFT, an impurity of a conductivity type different from the conductivity type at the time of channel formation is added to the channel portion in the enhancement type TFT, and the same conductivity type impurity is introduced in the depletion type TFT.
For example, an n-channel TFT is replaced with an enhancement type TFT.
A p-type impurity such as boron may be introduced to obtain a depletion type, and an n-type impurity such as phosphorus or arsenic may be introduced to obtain a depletion type. The concentration of the impurity in the channel formation region exceeds the detection limit of 1 × 10 ¹⁵ atoms / cm ³ in SIMS (Secondary Ion Mass Spectroscopy) analysis, and is about 2 V at 5 × 10 ¹⁷ atoms / cm ^3. However, a concentration exceeding 5 × 10 ¹⁷ atoms / cm ³ causes a marked decrease in mobility due to deterioration in crystallinity, so that a concentration not exceeding this is preferable.

By the way, even in a TFT having a threshold voltage of 0 V, the drain current is not actually 0 when the gate voltage is 0 V. In order to reduce the drain current when the gate voltage is 0 V, the value is sufficiently close to 0 V using the gate voltage when the value of the drain current is equal to or lower than the reference value as an index rather than the threshold voltage. Better. In this specification, the gate when the drain current flows at 1 pA per 1 μm width of the channel formation region under the condition of the absolute value of the drain voltage of 1 V (specifically, the drain voltage is -1 V for the p-channel TFT and the drain voltage is +1 V for the n-channel TFT). Consider that the voltage is used as a reference value and this value is controlled.
(Fig. 1b)

Further, in this specification, the enhancement type TFT and the depletion type TFT are defined by the gate voltage value when the absolute value of the drain voltage is 1 V and the absolute value of the drain current is 1 pA per 1 μm width of the channel forming region. That is, the enhancement-type TFT is an n-channel TFT, a drain voltage of +1 V, and a gate voltage of zero or a positive voltage at a drain current of 1 pA per 1 μm of the width of the channel forming region, or a p-channel TFT. A TFT whose gate voltage is a negative voltage when the drain current is 1 pA per 1 μm in width of the channel formation region at a voltage of −1 V is defined as a TFT. Similarly,
The depletion type TFT is an n-channel type TFT having a drain voltage of +1 V and a gate voltage of a negative voltage at a drain current of 1 pA per 1 μm width of a channel forming region, or a p-channel type TFT having a drain voltage of +1 V and a channel. A TFT whose gate voltage is zero or positive when the drain current is 1 pA per 1 μm width of the formation region is defined as a TFT.

Further, when the gate voltage at a drain current of 1 pA per 1 μm width of the channel forming region and an absolute value of the drain voltage of 1 V is sufficiently close to 0 V, the threshold voltage is also controlled to a certain voltage value. Therefore, in this specification, making the gate voltage sufficiently close to 0 V when the drain current is 1 pA per 1 μm of the width of the channel forming region and the absolute value of the drain voltage is 1 V has the same meaning as controlling the threshold voltage. And

[0013]

When the channel doping method is used to control the threshold voltage, an impurity is introduced into the active layer, so that a bulk crystal defect due to the impurity and an insulation between the semiconductor layer and the semiconductor layer are inevitably caused. This causes an interface level of the layer. As a result, TFT characteristics, particularly field-effect mobility, are deteriorated.

The present inventor has found that it is important to control the threshold voltage without deteriorating the TFT characteristics from the viewpoint of device fabrication. Therefore, a method of controlling the threshold voltage without using the channel doping method has been proposed. I thought it was important to establish. It was also considered effective to control the stress of the thin film for that purpose.

[0015]

A case in which channel doping is not performed will be considered. In this case, the p-type or n-type impurity concentration in the channel formation region becomes lower than the detection limit of 1 × 10 ¹⁵ atoms / cm ³ in SIMS analysis.

It is considered that a semiconductor film used for a TFT is suitably a crystalline semiconductor such as an amorphous semiconductor, which can provide a high field-effect mobility. Here, a crystalline semiconductor includes a single crystal semiconductor, a polycrystalline semiconductor, or a microcrystalline semiconductor. The insulating layer is typically formed using a material such as silicon oxide, silicon nitride, or silicon oxynitride.

It is known that a thin film of the above-mentioned material manufactured by a known technique such as a CVD method (chemical vapor deposition method), a sputtering method, or a vacuum deposition method has an internal stress.
The internal stress has been further considered to be divided into an intrinsic stress inherent in the thin film and a thermal stress caused by a difference in thermal expansion coefficient between the thin film and the substrate. The thermal stress is generated in the heating process of the TFT manufacturing process, and its influence can be ignored by setting the process temperature. On the other hand, the mechanism of the generation of the intrinsic stress is not always clear, and it was thought that the phase change and the composition change due to the growth process of the thin film and the subsequent heat treatment were involved in a complicated manner.

In general, as shown in FIG. 2, when a thin film tries to shrink with respect to a substrate, the substrate is affected by the internal stress and is deformed with the thin film inward. I have. On the other hand, when the thin film is stretched, the substrate is compressed and deformed with the thin film facing outward, and this is called compressive stress. As described above, for the sake of convenience, the definition of the internal stress has been considered centering on the substrate. In this specification, the internal stress is described according to this definition. Also,
In this specification, tensile stress is defined as having a positive sign, and compressive stress is defined as having a negative sign.

It has been known that a crystalline semiconductor film produced from an amorphous semiconductor film by a method such as thermal crystallization or laser crystallization undergoes volume shrinkage during the crystallization process. The ratio depends on the state of the amorphous semiconductor film, but is said to be about 0.1 to 1%. As a result, a tensile stress is generated in the crystalline semiconductor film, and the magnitude thereof may reach about 1 × 10 ⁹ Pa. In addition, it has been known that the internal stress of an insulating film such as a silicon oxide film, a silicon nitride film, and a silicon oxynitride film varies variously from a compressive stress to a tensile stress depending on film forming conditions and subsequent heat treatment conditions.

When the stress of the active layer semiconductor film and the stress of the insulating film on the substrate side or the side opposite to the substrate in contact with the active layer semiconductor film are changed, the threshold voltage changes. Although the detailed reason for this is not clear so far, for example, when the active layer semiconductor film tries to contract, if stress acts in the direction in which the active layer semiconductor film is stretched, strain occurs in the crystal grain boundaries, and dislocations and dislocations occur in this region. It is considered that the generation of crystal defects and the generation of interface states accompanying the generation of dangling bonds occur. It is well known that crystal defects and interface states affect the threshold voltage. Therefore, the threshold voltage can be changed by changing the stress. Alternatively, when stress is applied to the active layer semiconductor film, the lattice constant, that is, the distance between adjacent semiconductor atoms constituting the semiconductor film changes, and the energy band structure of the semiconductor film changes with the change. It is thought that the voltage also changes.

Therefore, the threshold voltage can be controlled by appropriately changing the stress applied to the active layer. By the way, what has a direct correlation with the threshold voltage is the sum of the product of the stress and the film thickness of the second insulating film and the product of the stress and the film thickness of the active layer. The threshold voltage can also be controlled by changing the thickness of both or either of the first and second insulating layers.

FIG. 11 shows the sum of the product of the stress and the film thickness of the second insulating layer and the sum of the product of the stress and the film thickness of the active layer, and the absolute value of the drain voltage of the TFT of 1 V per 1 μm of the width of the channel forming region. It is a correlation curve of the gate voltage when the absolute value of the drain current is 1 pA. However, the characteristic curves in the figure assume that the p-channel TFT and the n-channel TFT have the same structure except for the impurity concentration of the active layer. Under this assumption, the magnitude of the X coordinate X0 at which the gate voltage becomes 0 V when the absolute value of the drain voltage is 1 V and the absolute value of the drain current is 1 pA per 1 μm of the width of the channel formation region is the same. Indicates that X0 is determined only by the sum of the product of the stress and the film thickness of the second insulating film and the product of the stress and the film thickness of the active layer. Further, the correlation curve becomes a straight line, and the sign of the slope is the same between the n-channel TFT and the p-channel TFT. Therefore, the distinction between the enhancement type and the depletion type is reversed at the same X coordinate. The absolute value of X0 in the correlation curve and the slope of the correlation curve take an arbitrary value depending on the product of the stress and the film thickness of the first insulating layer or the product of the stress and the film thickness of the active layer. By setting the stress and the film thickness of the second insulating layer to appropriate values, the gate voltage when the drain voltage has an absolute value of 1 V and the drain current has an absolute value of 1 pA per 1 μm of the width of the channel forming region is close to 0 V. , Preferably with an absolute value of 2
V or less.

By the way, even when the channel doping method is used for controlling the threshold voltage, the gate voltage when the absolute value of the drain voltage is 1 V and the absolute value of the drain current per 1 μm width of the channel forming region is 1 pA without channel doping. If the product of the stress and the film thickness of the second insulating layer and the active layer is set to an appropriate value so that the voltage is close to 0 V and preferably 2 V or less, the concentration of the impurity doped into the channel region can be reduced. Therefore, it is effective because deterioration in TFT characteristics due to channel doping can be suppressed.

[0024]

[Embodiment 1] An embodiment in which a channel doping method is not used will be described with reference to FIG.
3A and 3B, a gate electrode 302 is formed over a substrate 301 having an insulating surface, and a gate electrode 302 is formed thereon.
As one insulating layer, a silicon nitride film 303a having a tensile stress and a silicon nitride oxide film 303b having a compressive stress are stacked.

The active layer 304 is a crystalline semiconductor film formed by a method such as laser crystallization or thermal crystallization of an amorphous semiconductor film, and is not necessarily limited to a detailed manufacturing method, but is necessarily pulled. Has stress. Further, a channel formation region 304c, an LDD region 304b, a source region 304a, and a drain region 304d are provided as needed. The source electrode 306 and the drain electrode 307 are
A contact hole is formed in a part of the insulating layer 305.

In the channel formation region, the concentration of phosphorus or arsenic as an n-type impurity or the concentration of boron as a p-type impurity is
It is below the detection limit by MS analysis, and phosphorus and arsenic as an n-type impurity or boron as a p-type impurity is implanted at a high concentration of 1 × 10 ¹⁹ atoms / cm ³ or more in the source region and the drain region.

In FIG. 3A, the second insulating layer is a silicon oxynitride film having a compressive stress. The threshold voltage is controlled by the stress and the film thickness.

As shown in FIG. 3B, the second insulating layer may be formed by stacking a plurality of insulating films. FIG.
In (B), the second insulating layer 305a is a silicon nitride oxide film having a compressive stress, and a silicon oxide film serving as the second insulating layer 305b having a compressive stress is stacked thereon, so that more effective The stress could be controlled.

The product of the absolute value of the stress and the film thickness of the first insulating layer is sufficiently smaller than the product of the absolute value of the stress and the film thickness of the second insulating layer. The product of the stress from the insulating layer and the film thickness was dominant. The sum of the product of the stress [Pa] and the film thickness [m] in the second insulating layer and the product of the stress [Pa] and the film thickness [m] in the active layer is −8.0 × 10 ¹ to −1. 2
× 10 ² , and the absolute value of the drain current per 1 μm width of the channel formation region is 1p at the absolute value of the drain voltage of 1V.
The absolute value of the gate voltage at A was controlled to 2 V or less.

The n-channel TFT manufactured by the above-described steps was a depletion-type TFT, and the p-channel TFT was an enhancement-type TFT.

[Embodiment 2] In a CMOS circuit,
N-channel TFT and p-channel TFT on the same substrate
Both FTs are made. And the n-channel type T
For the FT and the p-channel type TFT, a circuit configuration of an enhancement type is often used. Therefore, in this embodiment, a method of controlling a threshold voltage and obtaining a desired TFT by appropriately setting a product of a stress and a film thickness in the second insulating layer without using the channel doping method is described. This will be described in Section 4.

Incidentally, as described in the detailed description of the invention, an n-channel type TF without channel doping is used.
In the T and p channel type TFTs, the distinction between the enhancement type and the depletion type is opposite to each other if the product of the stress and the film thickness of the second insulating film and the active layer is the same. Therefore, in order to fabricate either the enhancement type or the depletion type TFT on the same substrate, it is necessary to change the structure of the second insulating layer and make a difference in the product of the stress and the film thickness.

FIG. 4 shows a substrate 401 having an insulating surface.
A gate electrode 402 is formed thereon, and a silicon nitride film 403a having a tensile stress, which is a first insulating layer, is formed thereon.
And a silicon oxynitride film 403b having a compressive stress.

On the n-channel TFT side, the active layer 4
Reference numeral 04 denotes a semiconductor layer having a tensile stress, and a channel formation region 404c, an LDD region 404b,
A source region 404a and a drain region 404d are provided. Also, the active layer 4 on the p-channel type TFT side.
Reference numeral 05 denotes a semiconductor layer having a tensile stress, in which a channel formation region 405c, a source region 405a, and a drain region 405d are provided. Source electrodes 406, 408
And the drain electrodes 407 and 409 are connected to the second insulating layer 410
Is formed by forming a contact hole in a part of it.

The concentration of phosphorus or arsenic as an n-type impurity or the concentration of boron as a p-type impurity is 1 × 10 ¹⁵ atoms / cm ³ or less in the active layer channel formation region, and the n-type impurity is Is implanted at a high concentration of 1 × 10 ¹⁹ atoms / cm ³ or more.

By the way, in FIG.
Stacked between the second insulating layer 410 of T and the active layer 404 are an active layer protective film and a mask insulating film used at the time of impurity doping of the n-channel TFT. By leaving the etching without etching, the product of the thickness of the second insulating layer and the stress is different from that of the p-channel TFT.

As the stress applied to the n-channel type TFT,
The product of the stress [Pa] and the film thickness [m] of the protective film of the active layer and the product of the stress [Pa] and the film thickness [m] of the active layer used at the time of doping #. Is the n-channel type T
In FT and ^{-1.2 × 10 2 ~-1.4 ×} 10 2, whereas p
For a channel type TFT, -8.0 × 10 ^{1 to} 1,2 × 10 ²
Then, both the n-channel TFT and the p-channel TFT can be an enhancement-type TFT. The absolute value of the gate voltage is controlled to 2 V or less when the absolute value of the drain voltage is 1 V and the absolute value of the drain current per 1 μm of the width of the channel formation region is 1 pA.

[Embodiment 3] An embodiment in which the channel toughening method of the present invention is used will be described with reference to FIG. In a CMOS circuit, an n-channel TF
Both T-channel and p-channel TFTs are made, and the threshold voltage is controlled so that both are enhancement-type TFTs. However, when channel doping is not performed,
The stress and the film thickness of the insulating layer and the active layer 2 are the n-channel type T
When the FT and the p-channel TFT are made to be the same, as described in the detailed description of the invention, the absolute value of the drain current is 1 V and the absolute value of the drain current is 1 pA per 1 μm of the width of the channel forming region. In this case, the absolute value of the gate voltage can be controlled to be close to 0 V. However, not only the enhancement type TFT but also the depletion type TFT can be controlled.
Is also made. In this case, the n-channel type TF
T or channel doping is performed on the active layer of the depletion type TFT of the p-channel type TFT,
It is effective to control the threshold voltage so as to obtain an enhancement type TFT.

FIG. 16 shows a substrate 40 having an insulating surface.
1, a gate electrode 402 is formed thereon, and a silicon nitride film 403 having a tensile stress, which is a first insulating layer, is formed thereon.
a and a silicon oxynitride film 403b having a compressive stress are laminated.

On the side of the n-channel TFT, the active layer 4
Reference numeral 04 denotes a semiconductor layer having a tensile stress, and a channel formation region 404c, an LDD region 404b,
A source region 404a and a drain region 404d are provided. Also, the active layer 4 on the p-channel type TFT side.
Reference numeral 05 denotes a semiconductor layer having a tensile stress, in which a channel formation region 405c, a source region 405a, and a drain region 405d are provided. Source electrodes 406, 408
And the drain electrodes 407 and 409 are connected to the second insulating layer 410
Is formed by forming a contact hole in a part of it.

Here, the active layers 404 and 405 are semiconductor films formed at the same time and having the same thickness and stress.
The second insulating layers 410 and 411 are formed simultaneously and have the same thickness and quality. For example, p in FIG.
In order for the channel type TFT to become the enhancement type,
When the thickness and stress of the insulating layer and the active layer are set,
Channel doping is performed on the active layer channel forming region 404 of the n-channel TFT with a p-type impurity such as boron to control the threshold to an enhancement type. As a result, an enhancement-type n-channel TFT and a p-channel TFT can be formed in the same substrate.

In the above method, since the channel doping is not performed on the n-channel TFT, the active layer has good crystallinity without any crystal defects or interface states caused by the channel doping. Although the channel doping is performed on the p-channel TFT, the impurity concentration in the channel doping is 5 × 10 ¹⁷ atoms / cm ³ because the TFT is formed in consideration of the stress of the second insulating layer and the active layer. Since the threshold voltage can be controlled with the following sufficiently small amount, a TFT having an active layer having good crystallinity can be obtained.

[0043]

[Embodiment 1] This embodiment will be described with reference to FIGS. First, a glass substrate, for example, a # 1737 substrate manufactured by Corning Incorporated was prepared as the substrate 601. Then, a gate electrode 602 was formed over the substrate 601. Here, a tantalum (Ta) film was formed to a thickness of 200 nm by a sputtering method. In addition, the gate electrode 6
02 may have a two-layer structure of a tantalum nitride film (50 nm thick) and a tantalum film (250 nm thick).

Then, the first insulating layer 603 and the amorphous semiconductor layer 604 were successively formed without being sequentially opened to the atmosphere. First
Was formed of a nitrogen-rich silicon oxynitride film 603a (thickness: 50 nm) and a silicon oxynitride film (thickness: 125 nm). The nitrogen-rich silicon oxynitride film 603a is S
It was manufactured by a plasma CVD method from a mixed gas of iH ₄ , N ₂ O, and NH ₃ . Further, the amorphous semiconductor layer 604 is also formed by using a plasma CVD method at 20 to 100 nm, preferably 30 to 100 nm.
It was formed to a thickness of 75 nm. (FIG. 5 (B))

Then, a heat treatment was performed at 450 to 550 ° C. for 1 hour. By this heat treatment, the first insulating layer 603 is formed.
And the amorphous semiconductor layer 604 released hydrogen, and a tensile stress could be applied. After that, a crystallization step was performed on the amorphous semiconductor layer 604 to form a crystalline semiconductor layer 605. In the crystallization step here, a laser crystallization method or a thermal crystallization method may be used. In the laser crystallization method, for example, XeCl excimer laser light (wavelength 30)
8 nm) to form a linear beam, an oscillation pulse frequency of 30 Hz, and a laser energy density of 100 to 500.
mJ / cm ² , 96% overlap ratio of linear beam
Was performed to crystallize the amorphous semiconductor layer. Here, as the amorphous semiconductor layer is crystallized, volume contraction occurs,
The tensile stress of the formed crystalline semiconductor layer 605 increased. (FIG. 5 (C))

Here, in the case of performing channel doping, after forming an insulating layer in contact with the crystalline semiconductor layer 605, channel doping is selectively performed only on a TFT for which channel doping is performed using a resist mask. After performing the channel doping, the resist mask is peeled off, and an impurity is implanted into the insulating layer covering the active layer at the time of channel doping,
Since impurities in the insulating layer may diffuse into the active layer in a later step, the active layer is selectively removed using a hydrofluoric acid-based etchant.

Next, an insulating film 606 was formed in contact with the crystalline semiconductor layer 605 thus formed. Here, a silicon oxynitride film was formed to a thickness of 200 nm. After that, a resist mask 607 in contact with the insulating film 606 was formed by a patterning method using exposure from the back.
Here, the gate electrode 602 served as a mask, and the resist mask 607 could be formed in a self-aligned manner. Then, as shown in the figure, the size of the resist mask became slightly smaller than the width of the gate electrode due to light wraparound. (FIG. 5D) and the resist mask 607
After the insulating film 606 was etched by using to form a channel protective film 608, the resist mask 607 was removed. Through this step, the surface of the crystalline semiconductor layer 605 other than the region in contact with the channel protective film 608 was exposed. The channel protective film 608 has a function of preventing an impurity from being added to the channel region in a later impurity adding step. (FIG. 5E)

Next, a resist mask 609 covering a part of the n-channel TFT and a region of the p-channel TFT is formed by patterning using a photomask, and is formed in a region where the surface of the crystalline semiconductor layer 605 is exposed. A step of adding an impurity element imparting n-type was performed. And
A first impurity region (n ⁺ type region) 610a was formed. In this embodiment, since phosphorus is used as an impurity element for imparting n-type, phosphine (PH ₃ ) is used in the ion doping method, the dose is 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage is 10 kV. The resist mask 60
In the pattern No. 9, the width of the n ⁺ -type region was determined by appropriately setting by the practitioner, and an n ⁻ -type region and a channel forming region having a desired width could be easily obtained. (FIG. 6 (A))

After removing the resist mask 609, a mask insulating film 611 was formed. Here, a silicon oxynitride film (thickness: 50 nm) was formed by a plasma CVD method.
The silicon oxynitride film had a compressive stress. (FIG. 6
(B))

Next, a step of adding an impurity element imparting n-type to the crystalline semiconductor layer provided with the mask insulating film 611 on the surface is performed to form a second impurity region (n ⁻ -type region).
612 was formed. However, in order to add impurities to the crystalline semiconductor layer thereunder via the mask insulating film 611,
It is necessary to set appropriate conditions in consideration of the thickness of the mask insulating film 611. Here, the dose amount is 3 × 10 ¹³
atoms / cm ² , and the acceleration voltage was 60 kV. The second impurity region 612 thus formed functions as an LDD region. (FIG. 6 (C))

Next, a resist mask 614 covering the n-channel TFT was formed, and a step of adding an impurity element imparting p-type to a region where the p-channel TFT was formed was performed. Here, diborane (B
₂ H ₆ ) and boron (B) was added. The dose is 4
× 10 ¹⁵ atoms / cm ² and an acceleration voltage of 30 kV. (FIG. 6 (D))

By the way, after adding the p-type impurity, the resist mask covering the n-channel TFT was not removed, and the p-type impurity was removed.
By selectively removing the mask insulating film 611 and the channel protective film 608 covering the active layer of the channel TFT with a fluorine-based etchant, the structure of the second insulating layer in the n-channel TFT and the p-type TFT is changed. The threshold voltage may be controlled by making a difference in the stress applied to the active layer.
(FIG. 8A)

For example, when both an enhancement type TFT and a depletion type TFT are to be formed among the n-channel type TFTs on the same substrate, the TFT to be depleted after the impurity addition step is completed.
Other than the above, the mask insulating film and the channel protective film may be selectively removed with a fluorine-based etchant solution by covering the other portions with a resist mask.

Then, after performing a step of activating the impurity element by laser annealing or thermal annealing, a heat treatment (300 to 450 ° C., 1 hour) is performed in a hydrogen atmosphere to hydrogenate the whole (FIGS. 7 and 8 ( A)). Alternatively, hydrogenation may be performed using hydrogen that has been converted into plasma. After that, the channel protective film 608 and the mask insulating film 611 were selectively removed with a hydrofluoric acid-based etchant, and the crystalline semiconductor layer was etched into a desired shape by a known patterning technique. (FIG. 7,
8 (B))

Through the above steps, the source region 615, the drain region 616, and the LDD region 6 of the n-channel TFT are formed.
17, 618 and a channel formation region 619 are formed.
Source region 621, drain region 6 of channel type TFT
22, a channel formation region 620 was formed. Then
A second insulating layer was formed to cover the n-channel TFT and the p-channel TFT. The second insulating layer has a compressive stress
The silicon oxide film having 8.1 × 10 ⁸ Pa is 1000 n
m. (FIGS. 7, 8 (C))

Then, contact holes are formed to form source electrodes 624 and 627 and drain electrodes 625 and 627.
Was formed. Further, source electrodes 624 and 62 are formed on an insulating film 623 made of a silicon oxide film as a second insulating layer.
7. A silicon oxynitride film 623 was formed to cover the drain electrodes 625 and 627. After obtaining the state shown in FIGS. 7 and 8 (D), a heat treatment was finally performed in a hydrogen atmosphere, and the whole was hydrogenated to complete an n-channel TFT and a p-channel TFT. The hydrogenation process could also be realized by exposing it to a plasmated hydrogen atmosphere.

With the TFT manufactured by the above steps,
The absolute value of the drain voltage is 1 V and the width of the channel formation region is 1 μm.
Stress dependence of the absolute value of the gate voltage when the absolute value of the drain current per m is 1 pA (with respect to the gate voltage,
The dependency of the product of the stress and the film thickness of the second insulating layer and the sum of the product of the stress and the film thickness of the active layer were as shown in FIGS. Here, the values of the product of the three types of stress and the film thickness shown in FIG. 12 were obtained by the second insulating layer structure shown in Table 1.

[0058]

[Table 1]

FIG. 12A shows the dependence of the threshold voltage of the n-channel TFT and the stress of the second insulating layer × the film thickness, which are manufactured by the above-described TFT manufacturing method. Assuming that the measured data is on a certain straight line, and the straight line having the least error from the actually measured data (line segment) was obtained using the least squares method, the Fitting-Curve in FIG. Fitting-Curve
Is the expected curve. From the Fitting-Curve and the expected curve, the sum of the product of the stress [Pa] of the second insulating layer and the film thickness [m] and the product of the stress [Pa] of the active layer and the film thickness [m] is approximately -7.5. × 1
When it is between 0 ¹ and −1.1 × 10 ¹ , the drain voltage +
It was found that the absolute value of the gate voltage was 1 V or less when the drain current per 1 μm width of the channel formation region was 1 pA at 1 V. It was also found that both the enhancement type TFT and the depletion type TFT can be manufactured by setting the sum of the product of the stress and the film thickness of the second insulating layer and the product of the stress and the film thickness of the active layer to an appropriate value. .
Similarly, FIG. 12B shows the result of an experiment for manufacturing a p-channel TFT. The product of the insulating layer stress [Pa] and the film thickness [m], the stress of the active layer [Pa] and the film thickness [m] are also shown in FIG. Is approximately -8.5 ×
10 when in between ¹ ~-1.1 × 10 ^1, the absolute value of the gate voltage when the absolute value 1pA the drain current per width 1μm of the channel forming region is -1V the drain voltage 2
V, and that both enhancement-type TFTs and depletion-type TFTs can be manufactured.

[Embodiment 2] An example of a semiconductor device provided with an n-channel TFT and a p-channel TFT using the manufacturing process of Embodiment 1 without performing channel doping will be described with reference to FIG. FIG. 9 shows an inverter circuit which is a basic configuration of a CMOS circuit. By combining such inverter circuits, a basic circuit such as a NAND circuit or a NOR circuit can be formed, or a more complicated shift register circuit or buffer circuit can be formed. FIG.
9A is a diagram corresponding to a top view of a CMOS circuit, and FIG. 9B is a cross-sectional structure diagram taken along a dotted line AA ′ in FIG. 9A.

In FIG. 9B, an n-channel TFT
Both the p-channel TFT and the p-channel TFT are formed on the same substrate. In a p-channel TFT, a gate electrode 902 is formed, and a nitrogen-rich silicon oxynitride film 903 having a tensile stress and a silicon oxynitride film 904 having a tensile stress are provided thereon as a first insulating layer. Then, an active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and p ⁺ regions 912 (drain regions) and 915 (source regions) and a channel formation region 914 are provided.
A second insulating layer 917 is provided in contact with the semiconductor layer,
Here, a silicon oxide film 919 is formed. Then, a source electrode 920 and a drain electrode 918 are formed through contact holes provided in the silicon oxide film. On the other hand, in the active layer of the n-channel type TFT, the n ⁺ -type region 905 (source region), 911 (the drain region) and the channel forming region 909, between the n ⁺ -type region and the channel forming region n ^- type An area is provided. Then, on the active layer, the mask insulating film 92 used in the doping process is formed.
1 and the active layer protection film 922 are left unremoved, thereby receiving a larger stress than the p-channel TFT and controlling the threshold voltage. Further, similarly to the p-channel TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 and a drain electrode 918 are provided.

Such a CMOS circuit includes a peripheral drive circuit of an active matrix type liquid crystal display device and an EL (Elec
The present invention can be applied to a driving circuit of a troLuminescence display device, a reading circuit of a contact image sensor, and the like.

[Embodiment 3] An example of a semiconductor device provided with an n-channel TFT using the manufacturing process of Embodiment 1 without performing channel doping will be described with reference to FIG.
FIG. 10 shows an E / D MOS which is a basic configuration of an NMOS circuit.
(Enhancement / depression) Indicates an inverter circuit. A feature of the E / D MOS inverter is that both enhancement type and depletion type TFTs are included in one circuit. By combining such inverter circuits, basic circuits such as a NAND circuit and a NOR circuit can be obtained. Or a more complicated shift register circuit, buffer circuit, or the like can be configured as in the CMOS inverter circuit of the second embodiment. FIG. 10A is a diagram corresponding to a top view of the E / D MOS inverter circuit, and FIG.
FIG. 10B shows a cross-sectional structural view of A ′, and FIG.
(C) shows a circuit diagram.

In FIG. 10B, an enhancement type TFT and a depletion type TFT are formed on the same substrate. The depletion type TFT has a gate electrode 90
2 are formed thereon, and a nitrogen-rich silicon oxynitride film 903 having a tensile stress and a silicon oxynitride film 904 are provided thereon as a first insulating layer. Then, an active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and n ⁺ regions 911 (drain regions) and 915 (source regions) and a channel formation region 914 are provided. An n − -type region is provided between the drain region and the channel formation region as needed. A second insulating layer 917 is provided in contact with the semiconductor layer, and a silicon oxide film 919 is formed here. And through the contact hole provided in the silicon oxide film,
A drain electrode 920 is formed. On the other hand, the active layer of the enhancement type TFT includes n ⁺ -type regions 905 (source region) and 911 (drain region) and a channel formation region 909, and an n ⁻ -type region between the n ⁺ -type region and the channel formation region. Is provided. And on the active layer,
The mask insulating film 921 and the protective film 922 of the active layer used in the doping process are not removed and are left, so that a larger stress is applied than in the depletion type TFT, and the threshold voltage is controlled. Further, similarly to the depression type TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 is provided.

Such an E / D MOS circuit includes a peripheral driving circuit of an active matrix type liquid crystal display device and an EL (Electro luminescenc), like the CMOS circuit of the second embodiment.
e) It can be applied to a driving circuit of a type display device, a reading circuit of a contact type image sensor, and the like.

[Embodiment 4] An n-channel type TFT and a p-channel type TF which are enhancement type TFTs on the same substrate.
An example of a semiconductor device including T and in which channel doping is performed on a channel formation region of one of the TFTs will be described with reference to FIG. FIG. 17 shows a CMOS
1 shows an inverter circuit which is a basic configuration of a circuit. By combining such inverter circuits, a basic circuit such as a NAND circuit or a NOR circuit can be formed, or a more complicated shift register circuit or buffer circuit can be formed. FIG. 17A is a diagram corresponding to a top view of a CMOS circuit, and FIG. 17B is a cross-sectional structural view taken along a dotted line AA ′ in FIG.

In FIG. 17B, an n-channel type TF
Both T-channel and p-channel TFTs are formed on the same substrate
Have been. The p-channel type TFT has a gate electrode 902
Is formed thereon, and a tensile stress is formed thereon as a first insulating layer.
Nitrogen-rich silicon oxynitride film 903 having
And a silicon oxide film 904. And the first
Active layer consisting of crystalline semiconductor film formed in contact with insulating layer
And p⁺Regions 912 (drain region), 915 (saw
Region) and a p-type or n-type impurity concentration of 1 × 10 ^Fifteenatom
s / cm^ThreeA channel forming region 914 that is less than
ing. A second insulating layer 917 is provided in contact with this semiconductor layer.
Here, a silicon oxide film 919 is formed here.
You. The contact hole provided on the silicon oxide film
Source and drain electrodes 920 and 918
Has been established. On the other hand, in the active layer of an n-channel TFT,
Is n⁺Mold region 905 (source region), 911 (drain
Region), a channel forming region 909, and the n⁺Type area
N between the channel forming region^-Mold area is provided
You. The active layer channel forming region 909 has B
1 × 10 p-type impurities^Fifteenatoms / cm^Three5 × 10 or more¹⁷atoms
/cm^ThreeChannel doped at the following low concentration,
The drain voltage is +1 V and the width of the channel formation region is 1 μm.
Gate voltage when the drain current per unit absolute value is 1 pA
The pressure is controlled to the positive side. Furthermore, p-channel type T
As in the case of the FT, the second insulating layer 917 has a contact hole.
A source electrode 916 and a drain electrode 918
Is provided. The above is the channel for n-channel TFT.
In this example, the thickness of the second insulating layer and the active layer is
Depending on the stress setting, p-channel TFTs
You may go for a hoop.

Such a CMOS circuit includes a peripheral drive circuit of an active matrix type liquid crystal display device and an EL (Elec
The present invention can be applied to a driving circuit of a troLuminescence display device, a reading circuit of a contact image sensor, and the like.

[Embodiment 5] Both a first n-channel TFT as an enhancement TFT and a second n-channel TFT as a depletion TFT are provided on the same substrate, and one of them is doped with a channel. The performed semiconductor device will be described with reference to FIG. FIG. 18 shows the NM
1 shows an E / D MOS (enhancement / depletion) inverter circuit which is a basic configuration of an OS circuit. E
The feature of the / D MOS inverter is that both enhancement type and depletion type TFTs are included in one circuit, and by combining such inverter circuits, a basic circuit such as a NAND circuit or a NOR circuit can be obtained. It is the same as the CMOS inverter circuit of the second embodiment in that it can be configured and a more complicated shift register circuit or buffer circuit can be formed. FIG.
18A is a diagram corresponding to a top view of an E / D MOS inverter circuit, and FIG. 18B shows a cross-sectional structure diagram along a dotted line AA ′ in FIG. 18A, and FIG. Shows a circuit diagram.

In FIG. 18B, an enhancement type TFT and a depletion type TFT are formed on the same substrate. The depletion type TFT has a gate electrode 90
2 are formed thereon, and a nitrogen-rich silicon oxynitride film 903 having a tensile stress and a silicon oxynitride film 904 are provided thereon as a first insulating layer. Then, an active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and the n ⁺ regions 911 (drain region) and 915 (source region) and a p-type or n-type impurity concentration of 1 × 10 ¹⁵ at
A channel formation region 914 of less than oms / cm 3 is provided, and an n − type region is provided between the source and drain regions and the channel formation region as needed. A second insulating layer 917 is provided in contact with the semiconductor layer, and a silicon oxide film 919 is formed here.
Then, a drain electrode 920 is formed through a contact hole provided in the silicon oxide film. on the other hand,
The active layer of the enhancement type TFT has an n ⁺ type region 9.
05 (source region) and 911 (drain region) and a channel forming region 909, and an n ⁻ type region is provided between the n ⁺ type region and the channel forming region. Then, a p-type impurity such as B is added to the active layer channel forming region 909 by 1 ×.
The channel is doped at a low concentration of 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less, so that the gate at a drain voltage of +1 V and an absolute value of a drain current per channel width of 1 μm of 1 pA is 1 pA. The voltage is controlled to the positive side. Further, similarly to the depression type TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 is provided. The above is an example of channel doping an enhancement type TFT.
Depending on the thickness and stress of the second insulating layer and the active layer, channel doping may be performed on the depletion type TFT.

Such an E / D MOS circuit includes a peripheral drive circuit for an active matrix type liquid crystal display device and an EL (Electro luminescenc), like the CMOS circuit of the second embodiment.
e) It can be applied to a driving circuit of a type display device, a reading circuit of a contact type image sensor, and the like.

[Embodiment 6] In this embodiment, the TFT of the present invention is used.
A semiconductor device incorporating an active matrix type liquid crystal display device using circuits will be described with reference to FIGS. 13, 14, and 15. FIG.

Such semiconductor devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV and the like. 13 and 14 show examples of these.
Shown in

FIG. 13A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a voice input portion 9003 and a display portion 9004 including an active matrix substrate.

FIG. 13B shows a video camera, which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 910.
Consists of six. The present invention is directed to a display device 910 including a voice input unit 9103 and an active matrix substrate.
2. It can be applied to the image receiving unit 9106.

FIG. 13C shows a mobile computer or a portable information terminal.
02, an image receiving section 9203, operation switches 9204, and a display device 9205. The present invention relates to an image receiving unit 920.
3 and display device 9 including active matrix substrate
205 can be applied.

FIG. 13D shows a head-mounted display, which includes a main body 9301, a display portion 9302, and an arm portion 9.
303. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 13E shows a television set having a main body 940.
1, speaker 9402, display portion 9403, receiving device 9
404, an amplification device 9405 and the like. A liquid crystal display device or an EL display device can be applied to the display portion 9403.

FIG. 13F shows a portable book, which has a main body 95.
01, display portions 9502, 9503, storage medium 9504,
It is composed of an operation switch 9505 and an antenna 9506, and displays data stored on a mini disk (MD) or a DVD or data received by the antenna. The display portions 9502 and 9503 are direct-view display devices, and the present invention can be applied to the display portions.

FIG. 14A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display section 96.
03, and a keyboard 9604.

FIG. 14B shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display device 9702, and a speaker unit 97.
03, a recording medium 9704, and operation switches 9705. This device uses a DVD (Di) as a recording medium.
It is possible to watch music, watch a movie, play a game, or use the Internet by using a CD (g. Versatile Disc) or a CD.

FIG. 14C shows a digital camera, which comprises a main body 9801, a display portion 9802, an eyepiece portion 9803, operation switches 9804, and an image receiving portion (not shown).

FIG. 15A shows a front type projector, which comprises a display 3601 and a screen 3602. The present invention can be applied to a display device and other signal control circuits.

FIG. 15B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3. It is composed of a screen 3704. The present invention can be applied to a display device and other signal control circuits.

FIG. 15C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 15A and 15B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 15D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 15C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 15D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

The present invention can also be applied to an image sensor and an EL display device. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[0088]

As described above, by setting the product of the stress and the film thickness of the active layer or the product of the stress and the film thickness of the second insulating film to an appropriate value, the channel doping is not performed and the TFT of the TFT can be formed. It is possible to control the threshold voltage. This makes it possible to manufacture a TFT having better electrical characteristics without crystal defects caused by channel doping.

[0089]

[Brief description of the drawings]

FIG. 1 is a definition diagram of an enhancement type TFT and a depletion type TFT.

FIG. 2 is a diagram illustrating the definition of internal stress of a thin film.

FIG. 3 is a cross-sectional view of a TFT illustrating Embodiment 1;

FIG. 4 is a cross-sectional view of a TFT illustrating Embodiment 2;

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 9 is a top view, a cross-sectional view, and a circuit diagram of a CMOS circuit.

FIG. 10 is a top view, a cross-sectional view, and a circuit diagram of an E / DMOS circuit.

FIG. 11 is a correlation diagram between a product of a stress and a film thickness of a second insulating layer and a gate voltage which is a reference in this specification.

12 shows a result of an experiment for manufacturing a TFT in Example 1. FIG.

FIG. 13 is a diagram illustrating a sixth embodiment.

FIG. 14 is a diagram illustrating a sixth embodiment.

FIG. 15 is a diagram illustrating a sixth embodiment.

FIG. 16 illustrates an embodiment in the case of performing channel doping.

FIG. 17 shows a CMOS manufactured by performing channel doping.
3A and 3B are a top view, a cross-sectional view, and a circuit diagram of a circuit.

FIG. 18: E / DM fabricated by performing channel doping
3A and 3B are a top view, a cross-sectional view, and a circuit diagram of an OS circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 F term (Reference) 5F048 AB03 AB04 AC02 AC04 BA16 BB09 BB12 BB14 BC06 BD04 5F110 AA08 BB04 CC08 DD02 EE01 EE04 EE14 EE44 FF03 FF04 FF05 FF09 FF30 GG02 GG06 GG13 GG25 GG32 GG45 HJ01 HJ12 HJ23 HM15 NN03 NN14 NN22 NN23 NN28 NN78 PP01 PP03 PP04 PP35 QQ09 QQ12 QQ24 QQ25

Claims (15)

[Claims] An electrode formed on an insulating surface, a first insulating layer provided on the electrode, and an island-shaped semiconductor film provided on the first insulating layer. A TFT having an active layer and the second insulating layer provided in contact with the active layer is used, wherein the active layer has a tensile stress, and the second insulating layer has a compressive stress. A semiconductor device characterized in that: 2. At least a first TFT on the same insulating surface
And a second TFT, wherein the first TFT and the second TFT include an electrode formed on the insulating surface, a first insulating layer provided in contact with the electrode, An active layer made of an island-shaped semiconductor film provided in contact with the first insulating layer; and a second insulating layer provided in contact with the active layer, wherein the first TFT is an n-channel TFT. Wherein the second TFT is a p-channel TFT and the first TFT is
And the second TFT are enhancement-type TF
T, wherein the product of the stress and the film thickness of the second insulating layer of the first TFT is different from the product of the stress and the film thickness of the second insulating layer of the second TFT. Semiconductor device. 3. At least a first TFT on the same insulating surface
And a second TFT, wherein the first TFT and the second TFT include an electrode formed on the insulating surface, a first insulating layer provided in contact with the electrode, An active layer made of an island-shaped semiconductor film provided in contact with the first insulating layer; and a second insulating layer provided in contact with the active layer, wherein the first TFT is an n-channel TFT. Wherein the second TFT is a p-channel TFT and the first TFT is
TFT and the second TFT are depletion type TFTs.
Wherein the product of the stress and the film thickness of the second insulating layer of the first TFT is different from the product of the stress and the film thickness of the second insulating layer of the second TFT. apparatus. 4. At least a first TFT on the same insulating surface
And a second TFT, wherein the first TFT and the second TFT include an electrode formed on the insulating surface, a first insulating layer provided in contact with the electrode, An active layer made of an island-shaped semiconductor film provided in contact with the first insulating layer; and a second insulating layer provided in contact with the active layer, wherein the first TFT is an enhancement type TFT. The second TFT is a depletion type TFT, the first TFT and the second TFT are n-channel type TFTs, and the stress and film thickness of the second insulating layer of the first TFT are different. The semiconductor device is characterized in that the product is different from the product of the stress and the film thickness of the second insulating layer of the second TFT. 5. At least a first TFT on the same insulating surface
And a second TFT, wherein the first TFT and the TF
T is an active layer comprising an electrode formed on the insulating surface, a first insulating layer provided on the electrode, and an island-shaped semiconductor film provided on the first insulating layer. And a second insulating layer provided in contact with the active layer, wherein the first TFT is an enhancement type TFT, the second TFT is a depression type TFT, and the first TFT And the second TFT is a p-channel TFT, and the product of the stress and the film thickness of the second insulating layer of the first TFT is the stress and the film thickness of the second insulating layer of the second TFT. A semiconductor device characterized by being different from the product of 6. The semiconductor according to claim 1, wherein an n-type or p-type impurity concentration of a channel forming region of said active layer is less than 1 × 10 ¹⁵ atoms / cm ^3. apparatus. 7. At least a first TFT on the same insulating surface
And the second TFT. The first TFT and the second TFT
FT is an active layer comprising an electrode formed on the insulating surface, a first insulating layer provided on the electrode, and an island-shaped semiconductor film provided on the first insulating layer. When,
A second insulating layer provided on and in contact with the active layer, wherein the first TFT is an n-channel type TFT,
Is a p-channel TFT, and the first TF
T and the second TFT are enhancement type TFTs, and the product of the stress and the film thickness of the second insulating layer of the first TFT is the stress and the film thickness of the second insulating layer of the second TFT. A semiconductor device characterized by being equal to the product of: 8. At least a first TFT on the same insulating surface
And a second TFT, wherein the first TFT and the second TFT include an electrode formed on the insulating surface, a first insulating layer provided in contact with the electrode, An active layer made of an island-shaped semiconductor film provided in contact with the first insulating layer; and a second insulating layer provided in contact with the active layer, wherein the first TFT is an n-channel TFT. Wherein the second TFT is a p-channel TFT and the first TFT is
TFT and the second TFT are depletion type TF
T, wherein the product of the stress and the film thickness of the second insulating layer of the first TFT is equal to the product of the stress and the film thickness of the second insulating layer of the second TFT. apparatus. 9. At least a first TFT on the same insulating surface
And a second TFT, wherein the first TFT and the second TFT include an electrode formed on the insulating surface, a first insulating layer provided in contact with the electrode, An active layer made of an island-shaped semiconductor film provided in contact with the first insulating layer; and a second insulating layer provided in contact with the active layer, wherein the first TFT is an enhancement type TFT. The second TFT is a depletion type TFT, the first TFT and the second TFT are n-channel type TFTs, and the stress and film thickness of the second insulating layer of the first TFT are different. A semiconductor device, wherein the product is equal to the product of the stress and the film thickness of the second insulating layer of the second TFT. 10. At least a first TF on the same insulating surface.
T and a second TFT, wherein the first TFT and the second TFT
The TFT of the present invention is an active element comprising an electrode formed on the insulating surface, a first insulating layer provided on the electrode, and an island-shaped semiconductor film provided on the first insulating layer. A second insulating layer provided on and in contact with the active layer, wherein the first TFT is an enhancement type TFT, the second TFT is a depletion type TFT, and the first TFT is The TFT and the second TFT are p-channel TFTs, and the product of the stress and the film thickness of the second insulating layer of the first TFT is the stress and the film thickness of the second insulating layer of the second TFT. A semiconductor device characterized by being equal to a product of thickness. 11. An n-type or p-type impurity concentration in a channel forming region of one of the first TFT and the second TFT in the active layer, wherein the n-type or p-type impurity concentration is 1 ×. Less than 10 ¹⁵ atoms / cm ³ and the other active layer channel formation region has an n-type or p-type impurity concentration of 1 × 10
A semiconductor device having a density of ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less. 12. The n-channel type TFT according to claim 1, wherein the n-channel TFT has a drain voltage of +1 V and a gate voltage at a drain current value of 1 pA per 1 μm width of an active layer channel formation region. The p-channel TFT has an absolute value of 2 V or less, and the p-channel TFT has a drain voltage of -1 V and an absolute value of a gate voltage of 2 V or less when a drain current value per 1 μm width of an active layer channel formation region is 1 pA. A semiconductor device characterized by the above-mentioned. 13. The semiconductor device according to claim 1, wherein the first insulating layer is made of silicon oxide, silicon nitride,
A semiconductor device comprising a single-layer film selected from silicon oxynitride or a plurality of stacked films. 14. The semiconductor device according to claim 1, wherein the active layer comprises a single-layer film or a plurality of stacked films selected from an amorphous semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. Characteristic semiconductor device. 15. The semiconductor device according to claim 1, wherein the second insulating layer is made of silicon oxide, silicon nitride,
A semiconductor device comprising a single-layer film or a plurality of stacked films selected from silicon oxynitride.