JP2000223716A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the reliability the same as or higher than that of a MOS transistor and obtain a good characteristic both in an on-state region and an off-state region by overlapping a part of a second impurity region of one conductivity type with a first layer of a gate electrode. SOLUTION: In an n-channel TFT of a CMOS circuit, a channel formation region 348, first impurity regions 360, 361, and second impurity regions 349a, 349b, 350a, 350b are formed. The second impurity regions 349a, 350a overlapping with a gate electrode are formed in the length of 1.5 μm and the regions 349b, 350b not overlapping with the gate electrode are formed in the length of 1.5 μm. The first impurity region 360 works as a source region and the first impurity region 361 works as a drain region. As a result, TFTs suitable for different driving voltages can be fabricated in one process on one and the same substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter, referred to as TFTs) on a substrate having an insulating surface, and a method for manufacturing the same. For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with the electro-optical device. Note that, in this specification, a semiconductor device generally means a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic device equipped with the electro-optical device.

[0002]

2. Description of the Related Art Technical development for manufacturing an active matrix type liquid crystal display device by providing a TFT on a glass substrate or a quartz substrate has been actively promoted. Among them, a TFT in which a semiconductor film having a crystalline structure is used as an active layer (hereinafter referred to as a crystalline T
FT) has high mobility, so that it is possible to realize a high-definition image display by integrating functional circuits on the same substrate.

[0003] In this specification, the semiconductor film having the crystal structure means a single crystal semiconductor, a polycrystal semiconductor,
Japanese Patent Application Laid-Open No. 7-130652
JP, JP-A-8-78329, JP-A-10-1
JP-A-35468, JP-A-10-135469,
Alternatively, it includes the semiconductor disclosed in Japanese Patent Application Laid-Open No. 10-247735.

In order to construct an active matrix type liquid crystal display device, an n-channel type TFT of a pixel matrix circuit is required.
FT (hereinafter referred to as pixel TFT) alone is 100 to 20
It requires about 100,000, and further adding a functional circuit provided on the periphery requires more crystalline TFTs. The specifications required for the liquid crystal display device are strict, and in order to stably display an image, it is necessary first to ensure the reliability of each crystalline TFT.

The characteristics of a field-effect transistor such as a TFT include a linear region in which the drain current and the drain voltage increase in proportion, a saturation region in which the drain current is saturated even if the drain voltage increases, and a characteristic in which the drain voltage is applied. Ideally, it can be divided into a cut-off region where no current flows. In this specification, the linear region and the saturation region are called an on region of the TFT, and the cutoff region is called an off region. For convenience, the drain current in the ON region is called an ON current, and the current in the OFF region is called an OFF current.

The pixel TFT has an amplitude of 15 to 2 as a driving condition.
A gate voltage of about 0 V is applied. Therefore, it is necessary to satisfy the characteristics of both the ON region and the OFF region. on the other hand,
The peripheral circuit for driving the pixel matrix circuit is CMO
The configuration is based on the S circuit, and the characteristics of the ON region are mainly emphasized.

However, it is said that crystalline TFTs are still inferior to MOS transistors (transistors fabricated on a single crystal semiconductor substrate) used in LSIs and the like in terms of reliability. For example, when the crystalline TFT is driven continuously, a deterioration phenomenon such as a decrease in the field-effect mobility or the on-current or an increase in the off-current may be observed. The cause is a hot carrier injection phenomenon, in which hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

In the technical field of LSI, as a method of reducing the off-state current of a MOS transistor and relaxing a high electric field near the drain, a lightly doped drain (LDD) is used.
pedDrain) structures are known. In this structure, a low-concentration impurity region is provided outside a channel formation region, and this low-concentration impurity region is called an LDD region.

It is naturally known that an LDD structure is formed even with a crystalline TFT. For example, Japanese Patent Application Laid-Open No. 7-20221
No. 0 publication discloses that a gate electrode has a two-layer structure having different widths, an upper layer width is formed smaller than a lower layer width, and ion implantation is performed using the gate electrode as a mask.
An LDD region is formed by one ion implantation utilizing the difference in the depth of penetration of ions due to the difference in the thickness of the gate electrode. Further, the structure is such that the gate electrode overlaps directly above the LDD region.

[0010] Such a structure is called GOLD (Gate-drain).
Overlapped LDD structure, LATID (Large-tilt-angl)
e implanted drain) structure or ITLDD (Inver
seT LDD) structure. Then, the high electric field near the drain is relaxed to prevent the hot carrier injection phenomenon, and the reliability can be improved. For example, "Muts
uko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97
TECHNICAL DIGEST, p523-526, 1997 ”shows a GOLD structure with sidewalls made of silicon.
It has been confirmed that extremely superior reliability can be obtained as compared with TFTs having other structures.

However, the structure disclosed in the same paper has a problem that the off-state current becomes larger than that of a normal LDD structure, and a countermeasure is required.
In particular, in the pixel TFT forming the pixel matrix circuit,
When the off-current increases, power consumption increases and abnormalities appear in image display.
Cannot be applied as it is.

[0012]

SUMMARY OF THE INVENTION The present invention is a technique for solving such a problem, and achieves a reliability equal to or higher than that of a MOS transistor, and at the same time, has a good performance in both an ON region and an OFF region. Crystalline TF with excellent properties
It aims at realizing T. It is another object of the present invention to realize a highly reliable semiconductor device including a semiconductor circuit in which a circuit is formed using such a crystalline TFT.

[0013]

FIG. 18 shows the structure of a TFT and the Vg− obtained at that time based on the knowledge obtained so far.
5 is a diagram schematically showing Id (gate voltage-drain current) characteristics. FIG. 18A-1 shows the simplest structure of a TFT in which a semiconductor layer includes a channel formation region, a source region, and a drain region. FIG. 13B shows the characteristics of this TFT, where the + Vg side is the ON region of the TFT,
The Vg side is an off region. The solid line shows the initial characteristics, and the broken line shows the characteristics of deterioration due to the hot carrier injection phenomenon. In this structure, both the ON current and the OFF current are high and the deterioration is large. Therefore, for example, the TFT cannot be used as it is for a pixel TFT of a pixel matrix circuit.

FIG. 18 (A-2) shows LDD in (A-1).
A structure in which a low concentration impurity region serving as a region is provided,
An LDD structure that does not overlap with the gate electrode.
FIG. 11B shows the characteristics of the TFT, in which the off-state current can be suppressed to some extent, but the deterioration of the on-state current cannot be prevented. FIG. 18 (A-3) shows the LD.
The D region completely overlaps with the gate electrode, and is also called a GOLD structure. FIG.
3) is a characteristic corresponding to this, and the deterioration can be suppressed to a level where there is no problem, but the off-state current is higher on the -Vg side than in the structure of (A-2).

Therefore, FIGS. 18 (A-1), (A-2),
In the structure shown in (A-3), the characteristics of the ON region and the characteristics of the OFF region required for the pixel matrix circuit cannot be satisfied simultaneously, including the problem of reliability. But,
As shown in FIG. 18A-4, when the LDD region has a structure in which a portion where the LDD region overlaps with the gate electrode and a portion where the LDD region does not overlap are formed, the deterioration of the on-current can be sufficiently suppressed, and The off-state current can be reduced.

The structure shown in FIG. 18A-4 is derived from the following considerations. In the structure as shown in FIG. 18A-3, when a negative voltage is applied to the gate electrode of the n-channel TFT, that is, in the off region, in the LDD region formed so as to overlap the gate electrode. As the negative voltage increases, holes are induced at the interface with the gate insulating film, and a current path is formed by minority carriers connecting the drain region, the LDD region, and the channel region. At this time, if a positive voltage is applied to the drain region, holes flow to the source region side, which is considered to be a cause of an increase in off-state current.

In order to cut off such a current path halfway, it can be considered that an LDD region in which minority carriers are not accumulated even when a gate voltage is applied may be provided.
The present invention relates to a TFT having such a configuration,
The present invention relates to a circuit using.

Accordingly, the structure of the present invention provides a TF having a semiconductor layer on a substrate, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film.
In the semiconductor device in which T is formed, the gate electrode is formed on the first layer of the gate electrode formed in contact with the gate insulating film, and on the first layer of the gate electrode, A second layer of the gate electrode formed inside the first layer, and a third layer of the gate electrode formed in contact with the first layer of the gate electrode and the second layer of the gate electrode The semiconductor layer includes a channel forming region, a first impurity region of one conductivity type, and a second impurity region of one conductivity type formed between the channel forming region and the first impurity region. And a part of the one-conductivity-type second impurity region overlaps with a first layer of the gate electrode.

In another aspect of the invention, a first step of forming a semiconductor layer on a substrate having an insulating surface, a second step of forming a gate insulating film in contact with the semiconductor layer, A third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film;
Is etched into a predetermined pattern, and the second
A fourth step of forming a layer, a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, and a second layer of the conductive layer (A) and the gate electrode. A sixth step of forming a conductive layer (C) in contact with the substrate, and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a third layer of the gate electrode and the gate. A seventh step is to form a first layer of an electrode, and an eighth step is to add an impurity element of one conductivity type to a selected region of the semiconductor layer.

In another aspect of the invention, a first step of forming a semiconductor layer on a substrate having an insulating surface, a second step of forming a gate insulating film in contact with the semiconductor layer, A third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film;
Is etched into a predetermined pattern, and the second
A fourth step of forming a layer, a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, and a second layer of the conductive layer (A) and the gate electrode. A sixth step of forming a conductive layer (C) in contact with the substrate, and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a third layer of the gate electrode and the gate. A seventh step of forming a first layer of the electrode, an eighth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, Third of gate electrode
A ninth step of removing a part of the layer.

In another aspect of the present invention, a first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface; A second step of forming a gate insulating film on the semiconductor layer; a third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film; A) etching a predetermined pattern to form a second layer of the gate electrode; and a fifth step of adding an impurity element of one conductivity type to a selected region of the first semiconductor layer. A sixth step of forming a conductive layer (C) in contact with the conductive layer (A) and the second layer of the gate electrode; and forming the conductive layer (C) and the conductive layer (A). In a predetermined pattern to form a third layer of the gate electrode and a first layer of the gate electrode, An eighth step of adding a conductivity type impurity element to selected regions of the first semiconductor layer and the second semiconductor layer, and adding an impurity of a conductivity type opposite to one conductivity type to the second semiconductor layer. And a ninth step of adding to the selected region.

Such a TFT can be suitably used for an n-channel TFT or a pixel TFT of a CMOS circuit. In the structure of the TFT of the present invention, the first impurity region formed in the semiconductor layer functions as a source region or a drain region, and the second impurity region functions as an LDD region. Therefore, the concentration of the one conductivity type impurity element is lower in the second impurity region than in the first impurity region.

Also, one conductivity type impurity region provided at one end of the semiconductor layer, the gate insulating film, and a wiring formed from a first layer of the gate electrode to a third layer of the gate electrode. A storage capacitor may be formed from the storage capacitor, and the storage capacitor may be connected to a source or a drain of the TFT.

Further, the first layer of the gate electrode and the third layer of the gate electrode are formed of silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W),
One or more elements selected from molybdenum (Mo), or a compound containing the above elements, and the second layer of the gate electrode is selected from aluminum (Al) and copper (Cu). It is characterized by being one or more kinds of elements or a compound containing the above elements as a main component.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. As the substrate 101 having an insulating surface, a glass substrate, a plastic substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate or a stainless steel substrate having an insulating film such as a silicon oxide film formed on the surface may be used. It is also possible to use a quartz substrate.

A base film 102 is formed on the surface of the substrate 101 on which the TFT is to be formed. Base film 102
May be formed by a plasma CVD method or a sputtering method, and is preferably formed using a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The base film 102 is provided to prevent impurities from diffusing from the substrate 101 into the semiconductor layer. For example, a silicon nitride film is
After that, a two-layer structure in which a silicon oxide film is formed in a thickness of 50 to 200 nm may be employed.

The semiconductor layer formed in contact with the base film 102 is obtained by solidifying an amorphous semiconductor film formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method by a laser annealing method or a thermal annealing method. Crystallized by the phase growth method,
It is desirable to use a crystalline semiconductor. Further, a microcrystalline semiconductor film formed by the above film formation method can be used. The semiconductor material applicable here includes silicon, germanium, a silicon-germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can be used.

Alternatively, a semiconductor layer formed on the substrate 301 is an SOI (Silicon On Silicon) having a single crystal silicon layer formed thereon.
Insulators) It may be a substrate. Several types of SOI substrates are known depending on the structure and manufacturing method. Typically, SIMOX (Separation by Implan) is used.
ted Oxygen), ELTRAN (Epitaxial Layer Tra)
nsfer: a registered trademark of Canon Inc.), Smart-Cut (SOIT
(Registered trademark of EC company) can be used. Of course,
Other SOI substrates can be used.

FIG. 1 shows a cross-sectional structure of an n-channel TFT and a p-channel TFT. n-channel type TF
The gate electrodes of the T and p-channel TFTs include a first layer of the gate electrode, a second layer of the gate electrode, and a third layer of the gate electrode. First layer of gate electrode 1
13 and 116 are formed in contact with the gate insulating film 103. Then, the second layer 11 of the gate electrode formed to be shorter in the channel length direction than the first layer 11 of the gate electrode
4 and 117 are provided so as to overlap the first layers 113 and 116 of the gate electrode. The third layer of the gate electrode is 11
5 and 118 are first layers 113 and 116 of the gate electrode.
Are formed on the second layers 114 and 117 of the gate electrode.

The first layers 113 and 116 of the gate electrode are:
Silicon (Si), titanium (Ti), tantalum (T
a), tungsten (W), molybdenum (Mo), or a material containing these materials as components. For example, a W—Mo compound, tantalum nitride (Ta)
N) and tungsten nitride (WN). The thickness of the first layer of the gate electrode may be 10 to 100 nm, preferably 20 to 50 nm.

The second layers 114 and 117 of the gate electrode are preferably made of a material having a low resistivity and containing aluminum (Al) or copper (Cu) as a component. The second of the gate electrode
The thickness of the layer is 50 to 400 nm, preferably 100 to 2
The thickness may be set to 00 nm. The second layer of the gate electrode is formed for the purpose of reducing the electric resistance of the gate electrode,
The length may be determined in consideration of the length and the resistance value of the gate wiring or the bus line connected to the gate electrode, and a balance between them.

The third layers 115 and 118 of the gate electrode
Similarly to the first layer of the gate electrode, silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W),
It is formed of a material selected from molybdenum (Mo) or a material containing these materials as components. The thickness of the third layer of the gate electrode is 50 to 400 nm, preferably 100 to 200 n.
m.

In any case, the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode may be formed by forming a film of the above material by sputtering. A predetermined shape is formed by etching and dry etching. Here, in order to form the third layer of the gate electrode so as to cover the second layer of the gate electrode, it is necessary to control the thickness of the second layer of the gate electrode as described above. It is necessary to appropriately set the sputtering conditions. For example, it is an effective means to make the film forming speed of the formed film relatively slow.

As a structure of the gate electrode as shown in FIG. 1, the second layer of the gate electrode has a clad structure surrounded by the first layer of the gate electrode and the third layer of the gate electrode, so that the heat resistance is improved. Can be enhanced. As a material of the gate electrode,
It is desirable to use a low-efficiency material such as Al or Cu, but there is a problem in that heating at 450 ° C. or more causes hillocks or diffuses into a peripheral insulating film or semiconductor layer. However, such a phenomenon is caused by Si, Ti,
This can be prevented by using a material such as Ta, W, or Mo, or a clad structure surrounded by a material containing these materials.

The semiconductor layer of the n-channel TFT includes a channel forming region 104 and first impurity regions 107 and 108.
And second impurity regions 105, 106a, and 106b formed in contact with the channel formation region. An impurity element imparting n-type is added to both the first impurity region and the second impurity region. At this time, the concentration of the impurity element is 1 × 1
0 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , preferably 2 × 10 ²⁰ to
5 × 10 ²⁰ atoms / cm ³ , the concentration of the second impurity region is 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , typically 5 × 10 ¹⁹ atoms / cm ³
It is added at ^{10 17 ~5 × 10 1 8 atoms} / cm 3. First
Impurity regions 107 and 108 function as a source region and a drain region.

On the other hand, the third impurity regions 111, 112a and 112b of the p-channel TFT function as a source region or a drain region. And the third
The impurity region 112b contains an impurity element imparting n-type at the same concentration as the first impurity region, but is doped with an impurity element imparting p-type at a concentration 1.5 to 3 times that of the first impurity region. I have.

The impurity element to be added to the second impurity region is formed by a method in which an impurity element imparting n-type to be added is added to the semiconductor layer through the first layer 113 of the gate electrode and the gate insulating film 103. Things.

The second impurity regions 106a and 106b are
As shown in FIGS. 2A and 2B, a second impurity region 106a which overlaps with the gate electrode through the gate insulating film 103 and a second impurity region 106b which does not overlap with the gate electrode can be provided. That is, the LDD region overlapping the gate electrode and the LDD region not overlapping
An area is formed. The formation of this region can be divided into a first step of forming an impurity element of one conductivity type (formation of a second impurity region) and a second step of forming an impurity element of one conductivity type (first impurity region). ), And at this time, a photoresist may be used as a mask.

This is a very convenient method when fabricating circuits having different driving voltages on the same substrate. FIG.
3B illustrates an example of design values of a TFT used for a logic circuit portion, a buffer circuit portion, an analog switch portion, and a pixel matrix circuit of a liquid crystal display device. At this time,
In consideration of the driving voltage of each TFT, not only the channel length but also the second impurity region 106
a and the second impurity region 106b not overlapping the gate electrode
Can be set.

TFT of shift register circuit of drive circuit
Further, since the characteristics of the ON region are basically emphasized for the TFT of the buffer circuit, a so-called GOLD structure may be employed, and the second impurity region 106b which does not overlap with the gate electrode is not necessarily provided. However, if it is intentionally provided, it may be set in the range of 0.5 to 3 μm in consideration of the driving voltage.
In any case, it is preferable that the value of the second impurity region 106b which does not overlap with the gate electrode be increased as the driving voltage increases in consideration of the breakdown voltage.

In addition, since it is difficult to increase the off current of the analog switch and the TFT provided in the pixel matrix circuit, for example, when the driving voltage is 16 V, the channel length is 3 μm.
The thickness of the second impurity region 106a overlapping the gate electrode is set to 1.5 μm, and the thickness of the second impurity region 106b not overlapping the gate electrode is set to 1.5 μm. Of course, the present invention is not limited to the design values shown here, and may be determined appropriately by the practitioner.

As shown in FIG. 17, in the present invention, the first layer 1701 of the gate electrode, the second layer 1702 of the gate electrode, and the third layer 1703 of the gate electrode in the channel length direction. The length is closely related to the dimensions of the TFT to be manufactured. The length of the second layer 1702 of the gate electrode in the channel length direction substantially corresponds to the channel length L1. At this time, L1 may be set to a value of 0.1 to 10 μm, typically 0.2 to 5 μm.

The length L of the second impurity region 1705 is
6 can be arbitrarily set by masking with a photoresist as described above, but is preferably formed to have a thickness of 0.2 to 6 μm, typically 0.6 to 3 μm.

The length L4 at which the second impurity region 1705 overlaps the gate electrode depends on the first layer 17 of the gate electrode.
01 is closely related to the length L2. The length of L4 is
It is desirable that the thickness be 0.1 to 4 μm, typically 0.5 to 3 μm. The length L5 at which the second impurity region 1705 does not overlap with the gate electrode may not necessarily be provided as described above, but is usually 0.1 to 3 in some cases.
μm, typically 0.3 to 2 μm. Here, the lengths of L4 and L5 may be determined based on, for example, the driving voltage of the TFT as described above.

In FIG. 1, the channel forming region 10 is formed.
4 is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^{3 in} advance.
May be added at a concentration of. This boron is added to control the threshold voltage, and other elements can be used as long as the same effect can be obtained.

As described above, according to the present invention, the gate electrodes are formed by the first layers 113 and 116 of the gate electrodes, the second layers 114 and 117 of the gate electrodes, and the third layers 11 and 11 of the gate electrodes.
5 and 118, and the second layers 114 and 117 of the gate electrode become the first layer 11 of the gate electrode as shown in FIG.
It has a clad structure surrounded by 3,116 and third layers 115,118 of the gate electrode. At least an n-channel TFT is characterized in that a part of the second impurity region 106 provided in the semiconductor layer with the gate insulating film 103 interposed therebetween overlaps with such a gate electrode.

In the n-channel TFT, the second impurity region may be provided only on the drain region side (on the first impurity region 108 side in FIG. 1) with the channel forming region 104 as the center. When characteristics of both the ON region and the OFF region are required as in the pixel TFT of the pixel matrix circuit, the source side (the first impurity region 107 side in FIG. 1) and the channel forming region 104 are centered. It is desirable to provide both on the drain region side (the first impurity region 108 side in FIG. 1).

On the other hand, the channel forming region 109 and the third impurity regions 111, 112a, 1
12b is formed. Of course, the structure may be the same as that of the n-channel TFT of the present invention. However, since the p-channel TFT is inherently high in reliability, it is preferable to increase the on-current and balance the characteristics with the n-channel TFT. When the present invention is applied to a CMOS circuit as shown in FIG. 1, it is particularly important to balance these characteristics. However, the structure of the present invention is a p-channel type TFT.
There is no problem even if it is applied to.

When the n-channel TFT and the p-channel TFT are completed in this way, they are covered with a first interlayer insulating film 119, and the source wirings 120 and 121 and the drain wiring 122
Is provided. In the structure of FIG. 1, after these are provided, a silicon nitride film is provided as the passivation film 123. Further, a second interlayer insulating film 124 made of a resin material is provided. The second interlayer insulating film does not need to be limited to a resin material. For example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure surface flatness.

FIG. 1 shows an example of a CMOS circuit comprising a complementary combination of an n-channel TFT and a p-channel TFT.
The present invention can also be applied to an S circuit or a pixel matrix circuit of a liquid crystal display device.

The configuration of the present invention described above will be described in more detail with reference to the following embodiments.

[Embodiment 1] In this embodiment, a method of simultaneously manufacturing a pixel circuit and a CMOS circuit which is a basic form of a driving circuit provided around the pixel matrix circuit will be described.

In FIG. 3A, an alkali-free glass substrate typified by a Corning 1737 glass substrate is used as the substrate 301. Then, a base film 302 is formed on the surface of the substrate 301 where the TFT is to be formed by a plasma CVD method or a sputtering method. Although the base film 302 is not shown, a silicon nitride film is formed to a thickness of 25 to 100 nm, typically 50 nm, and a silicon oxide film is formed to a thickness of 50 to 300 n.
m, typically 150 nm thick.

In addition, SiH ₄ ,
A silicon oxynitride film made of NH ₃ and N ₂ O
~ 200 nm (preferably 50-100 nm), as well as Si
A silicon oxynitride film formed from H ₄ and N ₂ O
The layer is formed to have a thickness of 200 nm (preferably 100 to 150 nm).

Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 302 by a plasma CVD method. Although it depends on the content of hydrogen, the amorphous silicon film is preferably subjected to a dehydrogenation treatment by heating at 400 to 550 ° C. for several hours to reduce the content of hydrogen to 5 atomic% or less and to perform a crystallization step. . Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Here, since both the base film and the amorphous silicon film can be formed by the plasma CVD method, even if the base film and the amorphous silicon film are formed continuously in vacuum. good. After the formation of the base film, the step of not once exposing to the air atmosphere makes it possible to prevent surface contamination and reduce the variation in characteristics of the TFT to be manufactured.

In the step of crystallizing the amorphous silicon film, a known laser annealing method or thermal annealing method may be used. In this embodiment, a crystalline silicon film is formed by condensing a pulse oscillation type KrF excimer laser beam linearly and irradiating it on an amorphous silicon film.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous emission type excimer laser or argon laser is used as the light source. Also, YAG
Using a laser as a light source, its fundamental frequency, second harmonic,
The third harmonic and the fourth harmonic may be used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing a laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300 to
４００400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 80 to 98%.

In this embodiment, a crystalline silicon film is formed from an amorphous silicon film as a semiconductor layer. However, a microcrystalline silicon film may be used or a crystalline silicon film may be formed directly. .

The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 303, 304, and 305.
To form

Next, the island-shaped semiconductor layers 303, 304, 3
A gate insulating film 306 containing silicon oxide or silicon nitride as a main component is formed so as to cover layer 05. The gate insulating film 306 may be formed using a silicon oxynitride film with a thickness of 10 to 200 nm, preferably 50 to 150 nm, using N ₂ O and SiH ₄ as raw materials by a plasma CVD method. Here, it is formed to a thickness of 100 nm.

Then, a gate electrode including the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode is formed on the gate insulating film 306. First, a conductive layer (A) 307 and a conductive layer (B) 308 are formed. The conductive layer (A) 307 may be formed using a material selected from Ti, Ta, W, and Mo. However, a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. Further, the thickness of the conductive layer (A) 307 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, 50 nm
A Ti film is formed by a sputtering method with a thickness of.

Gate insulating film 306 and conductive layer (A) 307
The thickness control is important. This is because an impurity imparting n-type is added to the semiconductor layers 303 and 305 through the gate insulating film 306 and the conductive layer (A) 307 in a first impurity addition step which is performed later. Actually, the process conditions for the first impurity addition were determined in consideration of the thickness of the gate insulating film 306 and the conductive layer (A) 307 and the concentration of the impurity element to be added. It has been previously confirmed that the impurity element can be added to the semiconductor layer within the above-mentioned thickness range. However, if the thickness fluctuates by 10% or more from the set original value, the concentration of the added impurity decreases.

The conductive layer (B) preferably uses a material selected from Al and Cu. This is provided to reduce the electric resistance of the gate electrode.
It is formed to a thickness of 0 nm, preferably 100 to 200 nm. When using Al, pure Al may be used,
Element selected from Ti, Si, Sc is 0.1 to 5 atomic
% Added Al alloy may be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 306.

Here, an Al film to which 0.5 atomic% of Sc is added is formed to a thickness of 200 nm by a sputtering method (FIG. 3A).

Next, a step of forming a resist mask using a known patterning technique and removing a part of the conductive layer (B) 308 is performed. Here, the conductive layer (B) 308 is Sc
Is formed by an Al film to which 0.5 atomic% is added, so that the etching is performed by a wet etching method using a phosphoric acid solution.
Then, as shown in FIG. 3B, second layers 309, 310, 311, 312 of the gate electrode are formed from the conductive layer (B). The length in the channel length direction of the second layer of each gate electrode is 3 μm in the second layers 309 and 310 of the gate electrode forming the CMOS circuit, and the pixel matrix circuit has a multi-gate structure. The length of each of the second layers 311 and 312 of the gate electrode was set to 2 μm.

This step can be performed by a dry etching method. However, in order to remove an unnecessary region of the conductive layer (B) 308 with good selectivity without damaging the conductive layer (A) 307, a wet etching is performed. An etching method is preferred.

Further, the storage capacitor is provided on the drain side of the pixel TFT constituting the pixel matrix circuit. At this time, the capacitor wiring 313 of the storage capacitor is formed using the same material as the conductive layer (B).

Then, a region for forming a p-channel type TFT is described.
A resist mask 314 is formed in the region, and the first n-type
A step of adding an impurity element to be provided is performed. Crystalline semiconductor
As an impurity element that imparts n-type to the body material,
(P), arsenic (As), antimony (Sb), etc.
Here, phosphine is used with phosphorus.
(PH_Three) Is performed by an ion doping method. In this process
Through the gate insulating film 306 and the conductive layer (A) 307
To add phosphorus to the underlying semiconductor layer, the accelerating voltage is
Set it as high as 80 keV. Phosphorus added to the semiconductor layer
Concentration is 1 × 10 ¹⁶~ 5 × 10¹⁹atoms / cm^ThreeIn the range
It is preferable that 1 × 10¹⁸atoms / cm^ThreeToss
You. Then, a region 315 in which phosphorus is added to the semiconductor layer,
316, 317, 318, 319, 320 are formed
(FIG. 3 (B)).

After removing the resist mask 314, the conductive layer (A) 307 and the second layer 30 of the gate electrode are removed.
9, 310, 311 and 312 and the conductive layer (C) 3 serving as a third layer of the gate electrode by closely contacting with the wiring 313 of the storage capacitor.
21 are formed. The conductive layer (C) 321 is made of Ti, Ta,
It may be formed of a material selected from W and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. For example, the thickness of the conductive layer (C) 321 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ta film is formed with a thickness of 50 nm by a sputtering method (FIG. 3C).

Next, a resist mask is formed using a known patterning technique, and a step of removing part of the conductive layer (C) 321 and part of the conductive layer (A) 307 is performed. here,
This is performed by a dry etching method. The conductive layer (C) 321 is Ta, and the conditions of dry etching are 100 mT by introducing 80 SCCM of CF ₄ and 20 SCCM of O _2.
Orr is applied by supplying 500 W high frequency power. At this time, the etching rate of Ta is 60 nm / min. The condition for etching the conductive layer (A) 307 is Si
Introducing 40 SCCM of Cl ₄ , 5 SCCM of Cl ₂ and 180 SCCM of BCl ₃ , 80 mTorr, 1200 W
The high-frequency power is applied. At this time, the etching rate of Ti is 34 nm / min.

Although a slight residue may be observed after etching, it can be removed by washing with a solution such as SPX washing solution or EKC. Also, under the above etching conditions, the etching rate of the underlying gate insulating film 306 is 18 to 38 nm / min, and care must be taken because if the etching time is long, the etching of the gate insulating film proceeds.

Then, the first layers 322 and 3 of the gate electrode
23, 324, 325 and the third layer 327 of the gate electrode,
328, 329 and 330 are formed. The first layer of the gate electrode and the third layer of the gate electrode have the same length in the channel length direction, and the first layer of the gate electrode 322,
323 and the third layers 327 and 328 of the gate electrode are 6 μm
Formed to a length of Also, the first layer 32 of the gate electrode
4, 325 and the third layer 329, 330 of the gate electrode
It is formed to a length of μm (FIG. 4A).

Thus, a gate electrode including the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode is formed. Further, a storage capacitor is provided on the drain side of a pixel TFT constituting a pixel matrix circuit. At this time, the wirings 326 and 331 of the storage capacitor are formed from the conductive layer (A) and the conductive layer (C).

Then, as shown in FIG. 4B, a resist mask 332, 333, 334, 335, 336 is formed, and a second step of adding an n-type impurity element is performed. This is also performed by an ion doping method using phosphine (PH ₃ ). Also in this step, the gate insulating film 30
6 to add phosphorus to the underlying semiconductor layer through
The acceleration voltage is set as high as 80 keV. Then, the regions 337, 338, 339, 340, 3
41, 342, 343 are formed. The concentration of phosphorus in this region is higher than that in the first step of adding the impurity element imparting n-type, and is 1 × 10 ¹⁹ to 1 × 10 ^21.
atoms / cm ³ , preferably 1 × 10 ²⁰ ato
ms / cm ³ .

In this step, the resist mask 33
The lengths of 2, 333, 334, and 335 in the channel length direction are important in determining the structure of each TFT.
In particular, in an n-channel TFT, the length of the first and third layers of the gate electrode and the length of the resist mask do not overlap with the region where the second impurity region overlaps with the gate electrode. The area can be freely determined within a certain range. In this embodiment, the first layer 322 of the gate electrode
And the length of the third layer 327 is 6 μm,
Since the lengths of the layers 324 and 325 and the third layers 329 and 330 were 4 μm, the resist mask 332 was 9 μm.
And the resist masks 334 and 335 were formed with a length of 7 μm. Needless to say, the respective lengths described here are merely examples, and thus may be determined in consideration of the driving voltage of the TFT as described above.

Next, a step of covering the region where the n-channel TFT is to be formed with the resist masks 344 and 345 and adding the third impurity element imparting p-type to only the region where the p-channel TFT is to be formed. I do. As the impurity element imparting the p-type, boron (B), aluminum (A
l) and gallium (Ga) are known. Here, boron is added as an impurity element by ion doping using diborane (B ₂ H ₆ ). Also in this case, the acceleration voltage is set to 80 keV, and boron is added to a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 4C, the third impurity regions 346a,
46b, 347a and 347b are formed. Although the third impurity regions 346b and 347b contain phosphorus added in the previous step, there is no problem because boron is added at twice the concentration (FIG. 4C).

When the steps up to FIG. 4C are completed, FIG.
As shown by, the step of removing the resist masks 344 and 345 and forming the first interlayer insulating film 374 is performed. The first interlayer insulating film 374 has a two-layer structure. First, a 50-nm-thick silicon nitride film 374a is formed. The silicon nitride film is formed by a plasma CVD method, and SiH ₄ is
CM, the NH ₃ 40 SCCM, and the N ₂ was introduced 100 SCCM 0.7 Torr, to high-frequency power of 300 W. Subsequently, the silicon oxide film 374b is
The 500SCCM, the O ₂ was introduced 50SCCM 1Tor
A high-frequency power of 200 W is applied to form a film having a thickness of 950 nm. Thus, the first interlayer insulating film 374 having a total thickness of 1 μm is formed by the silicon nitride film 374a and the silicon oxide film 374b.

The silicon nitride film formed here is necessary for performing the next heat treatment step. In this embodiment, a gate electrode having a clad structure as described above is formed. In this structure, the second layer of the gate electrode formed of Al is surrounded by the first layer of the gate electrode formed of Ti and the third layer of the gate electrode formed of Ta. . Ta has the effect of preventing Al hillocks and seepage to the surroundings, but has the disadvantage that it is immediately oxidized when heated at 400 ° C. or higher at normal pressure. As a result, the electric resistance increases. However, if the surface is covered with the silicon nitride film 374a of the first interlayer insulating film, oxidation can be prevented.

The heat treatment step needs to be performed to activate the n-type or p-type imparting impurity element added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it is difficult to activate a region under the gate electrode. Therefore, here, the activation step is performed by a thermal annealing method. The conditions at this time are 300 to 700 ° C. in a nitrogen atmosphere, preferably 350 to 700 ° C.
550 ° C., here 450 ° C., for 2 hours.

Thereafter, the first interlayer insulating film 374 is patterned to form a contact hole reaching the source region and the drain region of each TFT. Then, the source wirings 375, 376, 377 and the drain wiring 37
8, 379 are formed. Although not shown, in this embodiment, this wiring is used as a wiring having a three-layer structure in which a 100 nm thick Ti film, a 300 nm thick Al film containing Ti, and a 150 nm thick Ti film are continuously formed by a sputtering method.

Then, the source wirings 375, 376, 37
7, a passivation film 380 is formed to cover the drain wirings 378, 379 and the first interlayer insulating film 374.
The passivation film 380 is a silicon nitride film having a thickness of 50 n.
m. Further, a second interlayer insulating film 381 made of an organic resin is formed to a thickness of about 1000 nm.
As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

Through the above steps, a gate electrode having a clad structure is formed, and a channel forming region 348, a first impurity region 360,
361, second impurity regions 349a, 349b, 350
a, 350b are formed. Here, in the second impurity region, the regions 349a and 350a overlapping with the gate electrode are 1.A.
A region (LDD) that does not overlap with the gate electrode has a length of 5 μm.
Regions) 349b and 350b are each formed to a length of 1.5 μm. Then, the first impurity region 360 functions as a source region, and the first impurity region 361 functions as a drain region.

In the p-channel type TFT, a gate electrode having a clad structure is similarly formed, and a channel formation region 362,
Third impurity regions 363a, 363b, 364a, 36
4b is formed. Third impurity regions 363a, 363
b is a third impurity region 364a, 3b as a source region.
64b becomes a drain region.

The pixel TFT of the pixel matrix circuit
Are channel formation regions 365, 369, first impurity regions 368, 372 and second impurity regions 366, 367,
370 and 371 are formed. The second impurity regions are formed in regions 366a, 367a, and 37 overlapping with the gate electrode.
Regions 366b, 367b that do not overlap with 0a, 371a,
370b and 371b.

Thus, as shown in FIG. 5, an active matrix substrate having a CMOS circuit and a pixel matrix circuit formed on a substrate 301 is manufactured. A storage capacitor is simultaneously formed on the drain side of the pixel TFT of the pixel matrix circuit.

[Embodiment 2] In this embodiment, as in Embodiment 1, another embodiment will be described in which a CMOS circuit which is a basic form of a pixel matrix circuit and a driving circuit provided therearound is simultaneously manufactured.

First, similarly to the first embodiment, the steps shown in FIGS. 3A to 3C and the steps shown in FIG. 4A are performed.

FIG. 6A shows a state in which a gate electrode is formed from the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode. The resist masks 601, 602, 60
3, 604 and 605 are formed, and a step of adding an impurity element imparting n-type is performed. Then, the first impurity region 6
06, 607, 608, 609, 610, 611, 61
2 is formed (FIG. 6B).

The resist mask 601, formed here,
Reference numeral 602 denotes a shape in which the LDD region is formed only on the drain region side of the TFT. In this case, a region for masking the second impurity region from above the gate insulating film is formed only on one side of the channel formation region.

The formation of such a resist mask is performed by using the CM
This is particularly effective for an n-channel TFT of an OS circuit. Since the LDD region is formed only on one side, the series resistance component of the TFT can be substantially reduced, and the on-current can be increased.

Both the GOLD structure and the LDD structure described above are provided to alleviate the high electric field near the drain region. Can be obtained enough.

Further, resist masks 613 and 614 are formed, and a step of adding an impurity element imparting p-type is performed in the same manner as in the first embodiment.
5b and 616 are formed. The third impurity region 615a contains the n-type impurity element added in the previous step (FIG. 6C).

Subsequent steps may be performed in the same manner as in the first embodiment. A source wiring 375, 376, 377, a drain wiring 378, 379, a passivation film 380, and a second interlayer insulating film 381 made of an organic resin are formed. The active matrix substrate shown in FIG. 7 is completed. And CMO
The channel formation region 61 is provided for the n-channel TFT of the S circuit.
7. First impurity regions 620 and 621 and second impurity regions 618 and 619 are formed. Here, the second impurity region is a region (GOLD region) 61 overlapping with the gate electrode.
9a and a region that does not overlap with the gate electrode (LDD region) 6
19b are respectively formed. Then, the first impurity region 620 serves as a source region,
Becomes the drain region.

The p-channel type TFT includes a channel forming region 622, third impurity regions 624a, 624b, and 623.
Is formed. The third impurity region 623 serves as a source region, and the third impurity regions 624a and 624b serve as drain regions. The pixel TFT of the pixel matrix circuit includes the channel formation regions 625 and 629 and the first impurity region 62.
8, 632 and second impurity regions 626, 627, 63
0, 631 are formed. This second impurity region includes regions 626a, 627a, 630a overlapping with the gate electrode.
Areas 626b, 627b, 630 that do not overlap with 631a
b, 631b.

[Embodiment 3] In this embodiment, as in Embodiment 1, another embodiment will be described in which a CMOS circuit which is a basic form of a pixel matrix circuit and a driving circuit provided therearound is simultaneously manufactured.

First, the steps shown in FIGS. 3A to 3C are performed as in the first embodiment.

In FIG. 8A, resist masks 801, 802, 80 are formed by using a known patterning technique.
3, 804, and 805 are formed, and a step of removing part of the conductive layer (C) 321 and part of the conductive layer (A) 307 is performed. Here, the etching is performed by the dry etching method as in the first embodiment.
Then, the first layers 851, 852, 85 of the gate electrode
3, 854, 855 and the third layer 856, 8 of the gate electrode
57, 858, 859, and 860. The first layer of the gate electrode and the third layer of the gate electrode have the same length in the channel length direction, and the first layers 851 and 852 of the gate electrode of the CMOS circuit and the third layer of the gate electrode are formed. 85
6, 857 are longer than the final shape and formed to a length of 9 μm. Also, the first of the gate electrodes of the pixel matrix circuit
The layers 853 and 854 and the third layers 858 and 8 of the gate electrode
59 is similarly formed to a length of 7 μm.

Further, the storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, wirings 855 and 860 for a storage capacitor are formed from the conductive layer (A) and the conductive layer (C).

Then, as in the first embodiment, a second step of adding an impurity element imparting n-type is performed. In this step, phosphorus is added to the semiconductor layer through a region of the gate insulating film which is not in contact with the gate electrode, so that regions 806, 807, 808, 811, and 812 to which phosphorus is added at a high concentration are formed. After completion of this step, the resist masks 801, 8
02, 803, 804, and 805 are removed (FIG. 8).
(A)).

Next, a photoresist film is formed again, and a patterning step by exposure from the back surface is performed. At this time, as shown in FIG. 8B, the gate electrode serves as a mask, and the resist masks 813, 814, and 81 are self-aligned.
5, 816 and 817 are formed. Exposure from the back side is performed using direct light and scattered light, and a resist mask is formed on the inside of the gate electrode as shown in FIG. 8B by adjusting exposure conditions such as light intensity and exposure time. can do.

The resist masks 813, 814, 815,
Using 816 and 817, the unmasked regions of the third layer of the gate electrode and the first layer of the gate electrode are removed by dry etching. Dry etching conditions are the same as in the first embodiment. After the etching is completed, the resist masks 813, 814, 815, 816, 817 are removed.

Then, as shown in FIG. 8C, the first layer 818, 819, 820, 821 of the gate electrode, the third layer 823, 824, 825, 826 of the gate electrode and the wiring of the storage capacitor 822 and 827 are formed. The first layer 85 of the gate electrode of the CMOS circuit is etched by etching.
1, 852 and the third layer 856, 857 of the gate electrode are 6
μm in length. The first layers 853 and 854 of the gate electrodes of the pixel matrix circuit and the third layers 858 and 859 of the gate electrodes are similarly formed to a length of 4 μm.

Further, a step of forming resist masks 828 and 829 in a region where an n-channel TFT is formed and adding a third impurity element imparting p-type is performed (FIG. 8).
(C)).

The subsequent steps may be performed in the same manner as in Embodiment 1, and the active matrix substrate shown in FIG. 5 can be manufactured.

[Embodiment 4] In this embodiment, as in Embodiment 1, another embodiment will be described in which a CMOS circuit, which is a basic form of a pixel matrix circuit and a driving circuit provided therearound, is simultaneously manufactured.

First, the steps from FIG. 3A to FIG. 3C are performed as in the first embodiment. Then, a gate electrode is formed as shown in FIG.

Next, a step of forming a resist mask using a known patterning technique and removing part of the conductive layer (C) 321 and the conductive layer (A) 307 is performed. Here, the etching is performed by a dry etching method. Conductive layer (C) 32
Reference numeral 1 denotes Ta, and the dry etching condition is CF
₄ 80SCCM, and the O ₂ was introduced 20SCCM 100m
This is performed by inputting high-frequency power of 500 W at Torr. At this time, the etching rate of the Ta film is 60 nm / min. The conditions for etching the conductive layer (A) 307 are as follows: SiCl ₄ is 40 SCCM, Cl ₂ is 5 SCCM, and B
Cl ₃ was introduced at 180 SCCM, and 80 mTorr, 1
This is performed by applying a high-frequency power of 200 W. At this time, Ti
The etching rate of the film is 34 nm / min.

Then, the first layers 322 and 3 of the gate electrode
23, 324, 325 and the third layer 327 of the gate electrode,
328, 329 and 330 are formed. The first layer of the gate electrode and the third layer of the gate electrode are formed to have the same length in the channel length direction.
23 and the third layers 327 and 328 of the gate electrode are formed to have a length of 6 μm here. The first layers 324 and 325 of the gate electrode and the third layers 329 and 33 of the gate electrode
0 is formed to a length of 4 μm.

Under the above etching conditions, the gate insulating film 306 formed of the silicon oxynitride film is also etched. The etching rate is 18 nm / min under the Ta film etching conditions. Usually, this is performed carefully so that the gate insulating film is not etched. However, this phenomenon can be positively used to reduce the thickness of the region of the gate insulating film which is not in contact with the gate electrode. This can be performed immediately if the etching time is directly increased in the step of etching the gate electrode.

However, in order to etch the gate insulating film, it is necessary to select a gas to be used, and a fluorine-based gas such as CF ₄ or NF ₃ gives a better result than a chlorine-based gas. .

Here, the etching is performed using a mixed gas of CF ₄ and O ₂ used when etching the Ta film. 8 for CF ₄
0SCCM, and the O ₂ was introduced 20SCCM 100mTo
This is performed by inputting a high-frequency power of 500 W at rr. Then, the gate insulating film 3 formed with a thickness of 100 nm
FIG. 9 (A) is etched by about two and a half minutes for
As shown in the figure, the region of the gate insulating film not in contact with the gate electrode can be reduced to a thickness of 50 nm.

Then, in the same manner as in the first embodiment, resist masks 332, 333, 334, 335, 336 are formed and 2
A second step of adding an impurity element imparting n-type is performed. At this time, regions 337, 338, 339, 340, 341, 342, and 342 to which an impurity element imparting n-type is added are added.
Since the gate insulating film 343 has a thickness of 50 nm, an impurity element can be efficiently added to the semiconductor layer.

The acceleration voltage in the ion doping method is set to 80 keV to 40 keV due to the thinner gate insulating film.
And damage to the gate insulating film and the semiconductor layer can be reduced (FIG. 9B).

Next, as shown in FIG. 9C, a process of forming resist masks 344 and 345 and adding an impurity element for imparting p-type is similarly performed. Regions 346a, 346b, and 3 to be added
The gate insulating film in contact with 47a and 347b has a thickness of 50n.
m, the acceleration voltage in the ion doping method can be reduced from 80 keV to 40 keV, and the impurity element can be efficiently added to the semiconductor layer.

The other steps may be in accordance with the first embodiment. The source wirings 375, 376, 377 and the drain wiring 37
8, 379, a passivation film 380, and a second interlayer insulating film 381 made of an organic resin are formed to complete the active matrix substrate shown in FIG. CMOS circuit n
In the channel type TFT, a channel formation region 348, first impurity regions 360 and 361, a second impurity region 349,
350 is formed. Here, as the second impurity region, regions 349a and 350a which overlap with the gate electrode and regions (LDD regions) 349b and 350b which do not overlap with the gate electrode are formed. Then, the first impurity region 360 functions as a source region, and the first impurity region 361 functions as a drain region. In the p-channel type TFT, similarly, a gate electrode having a clad structure is formed, and a channel formation region 36 is formed.
2, third impurity regions 363a, 363b, 364a,
364b is formed. Third impurity region 363a, 3
63b is a third impurity region 364 as a source region.
a and 364b are drain regions. Further, the pixel TFTs of the pixel matrix circuit have channel forming regions 365, 3
69, first impurity regions 368, 372 and second impurity regions 366a, 366b, 367a, 367b, 370
a, 370b, 371a, and 371b are formed. This second impurity region is formed in a region 366 overlapping with the gate electrode.
a, 367a, 370a, area 371 not overlapping with 371a
66b, 367b, 370b, and 371b.

[Embodiment 5] In this embodiment, a method of simultaneously manufacturing a CMOS circuit which is a basic form of a pixel matrix circuit and a driving circuit provided around the pixel matrix circuit will be described.

In FIG. 11A, an alkali-free glass substrate typified by a Corning 1737 glass substrate is used as the substrate 1101. And the substrate 11
A base film 1102 is formed on the surface on which the TFT No. 01 is formed by a plasma CVD method or a sputtering method. Base film 110
2 is not shown, but the silicon nitride film is 25-100
The silicon oxide film is formed to a thickness of 50 nm to 300 nm, typically 150 nm. Further, as the base film 1102, only a silicon nitride film or a silicon oxynitride film may be used.

Next, 50 nm is formed on the underlayer 1102.
An amorphous silicon film having a thickness of 2 is formed by a plasma CVD method. Although it depends on the content of hydrogen, the amorphous silicon film is preferably subjected to a dehydrogenation treatment by heating at 400 to 550 ° C. for several hours to reduce the content of hydrogen to 5 atomic% or less and to perform a crystallization step. . Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Here, both the base film and the amorphous silicon film are formed by the plasma CVD method. At this time, even if the base film and the amorphous silicon film are formed continuously in vacuum. good. After the formation of the base film, the step of not once being exposed to the air atmosphere makes it possible to prevent surface contamination and reduce the variation in the characteristics of the TFT to be manufactured.

Here, a crystalline silicon film used as a semiconductor layer is formed by a thermal crystallization method using a catalytic element. When a catalyst element is used, it is desirable to use the technology disclosed in JP-A-7-130652 and JP-A-8-78329.

Here, an example in which the technique disclosed in JP-A-7-130652 is applied to the present invention will be described with reference to FIGS. A silicon oxide film 1902 is formed over a substrate 1901, and an amorphous silicon film 1903 is formed thereover. A nickel acetate layer solution containing 10 ppm by weight of nickel is applied to the surface of the amorphous silicon film 1903 to form a nickel-containing layer 1904 (FIG. 19A).

Next, after the dehydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500-650 ° C. for 4-12 hours, for example, 550 ° C.
Is performed for 8 hours to form a crystalline silicon film 1905 (FIG. 19B).

The technique disclosed in Japanese Patent Application Laid-Open No. 8-78329 enables selective crystallization of an amorphous silicon film by selectively adding a catalytic element. When applying this technology to the present invention,
This will be described with reference to FIGS.

First, a silicon oxide film 2002 and an amorphous silicon film 2003 are formed on a glass substrate 2001, and a silicon oxide film 2004 is formed continuously. At this time, the thickness of the silicon oxide film 2004 is set to 150 nm.

Next, the silicon oxide film 2004 is patterned to selectively form the opening portion 2005, and thereafter, a nickel acetate solution containing 10 ppm by weight of nickel is applied. As a result, a nickel-containing layer 2006 is formed, and the nickel-containing layer 2006 contacts the amorphous silicon film 2003 only at the bottom of the opening 2005 (FIG. 2).
0 (A)).

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment at 570 ° C. for 14 hours is performed to form a crystalline silicon film 2007. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally from there. The crystalline silicon film 2007 thus formed is made up of a collection of rod-shaped or needle-shaped crystals, each of which grows in a specific direction when viewed macroscopically, and thus has uniform crystallinity. (FIG. 20B).

The catalyst elements that can be used in the above two technologies are, in addition to nickel (Ni), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), Elements such as platinum (Pt), copper (Cu), and gold (Au) may be used.

When a crystalline silicon film is formed by using the above-described technique and is patterned, the semiconductor layers 1103, 1104, and 1105 shown in FIG. 11 can be formed.

An example in which a crystalline silicon film is formed using a catalytic element and a gettering step of removing the catalytic element from the crystalline silicon film will be described.

This is a technique for removing the catalytic element used for crystallization of the amorphous silicon film after crystallization by using the gettering action of phosphorus. By using the same technology, the concentration of the catalytic element in the crystalline silicon film is reduced to 1 × 10 ¹⁷ atoms / cm ³
Hereinafter, it can be reduced preferably to 1 × 10 ¹⁶ atoms / cm ³ .

FIG. 21A shows a state in which a base film 2102 and a crystalline silicon film 2103 have been formed.
Then, a silicon oxide film 2104 for a mask is formed on the surface of the crystalline silicon film 2103 to a thickness of 150 nm, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus is performed to provide a region 2105 to which phosphorus is added in the crystalline silicon film.

In this state, 550-80
When heat treatment was performed at 0 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, a region 2105 to which phosphorus was added to the crystalline silicon film functioned as a gettering site and remained in the crystalline silicon film 2103. The catalytic element can be segregated in the region 2105 to which phosphorus is added.

Then, the silicon oxide film 210 for the mask is used.
4 and the region 2105 to which phosphorus is added by etching to remove the crystalline silicon film in which the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. Can be obtained. This crystalline silicon film corresponds to the semiconductor layers 1103 and 110 in FIG.
4, 1105.

Next, the island-like semiconductor layers 1103, 110
4 and 1105, a gate insulating film 1106 containing silicon oxide or silicon nitride as a main component is formed. The gate insulating film 1106 is formed of N ₂ O and S by a plasma CVD method.
iH ₄ 10 to 200 of the silicon nitride oxide film as a raw material
nm, preferably 50 to 150 nm. Here, it is formed to a thickness of 100 nm.

Then, a conductive layer (A) 1107 serving as a first layer of the gate electrode and a conductive layer (B) 1108 serving as a second layer of the gate electrode are formed on the surface of the gate insulating film 1106. The conductive layer (A) 1107 is made of Ti, Ta, W, Mo.
May be used, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. The thickness of the conductive layer (A) 1107 is 10 to 100.
nm, preferably 20 to 50 nm. Here, a Ti film having a thickness of 50 nm is formed by a sputtering method.

The conductive layer (B) serving as the second layer of the gate electrode
For 1108, it is preferable to use a material selected from Al and Cu. This is provided to reduce the electric resistance of the gate electrode, and is formed to a thickness of 50 to 400 nm, preferably 100 to 200 nm. When Al is used, pure Al may be used, or Ti, Si, Sc
Al containing 0.1-5 atomic% of an element selected from
An alloy may be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 1106.

Here, an Al film containing 0.5 atomic% of Sc is formed to a thickness of 200 nm by sputtering (FIG. 11A).

Next, a step of forming a resist mask using a known patterning technique and removing a part of the conductive layer (B) 1108 is performed. Here, the conductive layer (B) 1108 is formed of an Al film containing 0.5 atomic% of Sc, but can be formed by a wet etching method using a phosphoric acid solution. Then, as shown in FIG. 11B, the second layer 1109, 1110, 1111, 11
12 is formed. The length in the channel length direction of the second layer of each gate electrode is 3 μm in the second layer 1109 and 1110 of the gate electrode forming the CMOS circuit, and the pixel matrix circuit has a multi-gate structure. Thus, the length of each of the second layers 1111 and 1112 of the gate electrode is set to 2 μm.

Further, the storage capacitor is provided on the drain side of the pixel TFT constituting the pixel matrix circuit. At this time, the wiring 1113 of the storage capacitor is formed using the same material as the conductive layer (B).

Then, the first impurity element imparting n-type
Is added. Here, phosphorus is used
Fin (PH_Three) Is performed by an ion doping method. this
In the step, the gate insulating film 1106 and the conductive layer (A) 110
7, the semiconductor layers 1103, 1104, and 11 thereunder.
In order to add phosphorus to 05, the accelerating voltage is 80 keV.
Set higher. The concentration of phosphorus added to the semiconductor layer is
1 × 10¹⁶~ 5 × 10 ¹⁹atoms / cm^ThreeIs better to be in the range of
Good, here is 1 × 10¹⁸atoms / cm^ThreeAnd Soshi
And regions 1114 and 111 in which phosphorus is added to the semiconductor layer.
5, 1116, 1117, 1118, 1119, 112
0 and 1121 are formed (FIG. 11B).

Next, a step of covering the region for forming the n-channel TFT with the resist masks 1122 and 1123 and adding the third impurity element imparting p-type to only the region for forming the p-channel TFT. I do. Here, boron is added as an impurity element by ion doping using diborane (B ₂ H ₆ ). Again, the accelerating voltage is 80
As keV, boron is added at a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 11C, third impurity regions 1124 and 112 doped with boron at a high concentration.
5 are formed.

Then, the resist masks 1122, 112
3 is removed, the conductive layer (A) 1107, the second layer 1109, 1110, 1111, 1112 of the gate electrode and the wiring 1113 of the storage capacitor are brought into close contact with each other to form the conductive layer (C ) 1126 is formed. The conductive layer (C) 1126 may be formed of a material selected from Ti, Ta, W, and Mo, but may be a compound containing the above material as a component in consideration of electric resistance and heat resistance. For example, the thickness of the conductive layer (C) 1126 is 10 to 100 nm,
Preferably, it should be 20 to 50 nm. Here, a Mo-W film with a thickness of 50 nm is formed by a sputtering method. (FIG. 12 (A))

Next, a resist mask is formed by using a known patterning technique, and a step of removing a part of the conductive layer (C) 1126 and a part of the conductive layer (A) 1107 is performed. Here, the etching is performed by a dry etching method. Conductive layer (C) 11
26 is a Mo-W film, as a condition of dry etching is performed with Cl ₂ 80 SCCM introduced to 10 mTorr, in and high frequency power of 350 W. At this time, Mo-
The etching rate of the W film is 50 nm / min. Also,
The condition for etching the conductive layer (A) 1107 is SiC
l ₄ to 40 SCCM, a Cl ₂ 5 SCCM, a BCl ₃ 1
This is performed by introducing 80 SCCM and applying high frequency power of 80 mTorr and 1200 W. At this time, the etching rate of the Ti film is 34 nm / min.

Although a slight residue may be observed after etching, it can be removed by washing with a solution such as SPX washing solution or EKC. In addition, under the above etching conditions, the etching rate of the underlying gate insulating film 1106 is 18 to 38 nm / min, and care must be taken because if the etching time is long, the etching of the gate insulating film proceeds.

Then, the first layer 1127 of the gate electrode,
1128, 1129, and 1130 and third layers 1132, 1133, 1134, and 1135 of the gate electrode are formed. The first layer of the gate electrode and the third layer of the gate electrode have the same length in the channel length direction, and the first layers 1127 and 1128 of the gate electrode and the third layer 1 of the gate electrode have the same length.
Here, 132 and 1133 are formed to have a length of 6 μm. Further, the first layers 1129 and 1130 of the gate electrode and the third layers 1134 and 1135 of the gate electrode are formed to have a length of 4 μm (FIG. 12B).

In addition, a storage capacitor is provided on the drain side of the pixel TFT forming the pixel matrix circuit. At this time, the electrodes 1131 and 1136 of the storage capacitor are formed from the conductive layer (A) and the conductive layer (C).

Then, as shown in FIG. 12C, the resist masks 1137, 1138, 1139, 1140,
Step 1141 is performed to add a second impurity element imparting n-type. Here, phosphine (PH
_This is performed by the ion doping method using ₃ ). Also in this step, the acceleration voltage is set as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 1106. Then, the regions 1142 and 114 to which phosphorus is added
3, 1144, 1145, 1146, 1147, 114
8 is formed. The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and is preferably 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3. In this case, it is set to 1 × 10 ²⁰ atoms / cm ³ .

In this step, the resist mask 113
The length in the channel length direction of 7, 1138, 1139, 1140 is important in determining the structure of each TFT. In particular, in an n-channel TFT, the length of the first and third layers of the gate electrode and the length of the resist mask do not overlap with the region where the second impurity region overlaps with the gate electrode. The area can be freely determined within a certain range. In this embodiment, the first layer 1 of the gate electrode
127, 1128 and the third layer 1132, 1
133 has a length of 6 μm, and the first layer 1
129, 1130 and the third layer 1134, 1
Since the length of 135 is 4 μm, the length of the first and third layers of the gate electrode is 6 μm, so that the resist mask 1137 has a length of 9 μm and the resist mask 113 has a length of 9 μm.
9 and 1140 are formed with a length of 7 μm.

When the steps up to FIG. 12C are completed, the resist masks 1137, 1138, 1139, 114
0, 1141 are removed, and a step of forming a first interlayer insulating film 1168 is performed. The first interlayer insulating film 1168 has a two-layer structure. First, a silicon nitride film is formed to a thickness of 50 nm. The silicon nitride film is formed by a plasma CVD method. SiH ₄ is 5 SCCM, NH ₃ is 40 SCCM, N ₂
Is introduced at 100 SCCM, and high frequency power of 0.7 Torr and 300 W is supplied. Then, the silicon oxide film is introduced with 500 SCCM of TEOS and 50 SCCM of O _2, and is supplied with a high frequency power of 1 Torr and 200 W for 950 minutes.
A film is formed to a thickness of nm. Therefore, a first interlayer insulating film 1168 having a total thickness of 1 μm is formed.

The heat treatment step needs to be performed to activate the n-type or p-type imparting impurity element added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it is difficult to activate even a semiconductor layer below a gate electrode. Therefore, here, the activation step is performed by a thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550.
C., here 450 ° C., for 2 hours.

Thereafter, the first interlayer insulating film 1168 was patterned to form contact holes reaching the source region and the drain region of each TFT. And
Source wirings 1169, 1170, and 1171 and drain wirings 1172 and 1173 are formed. Although not shown, in this embodiment, this wiring is formed by a
An Al film containing i and a Ti film having a thickness of 300 nm and a Ti film having a thickness of 150 nm are successively formed by a sputtering method, and are used as three-layer wiring.

Then, the source wirings 1169, 1170,
1171, the drain wirings 1172 and 1173, and the passivation film 117 covering the first interlayer insulating film 1168.
4 is formed. The passivation film 1174 is formed using a silicon nitride film with a thickness of 50 nm. Further, a second interlayer insulating film 1175 made of an organic resin is
Formed to a thickness of As the organic resin film, polyimide,
Acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. here,
After applying to the substrate, use a polyimide that is thermally polymerized,
It is formed by firing at 300 ° C.

Through the above steps, a gate electrode having a clad structure is formed. In the n-channel type TFT of the CMOS circuit, the channel formation region 1149 and the first impurity region 115 are formed.
2, 1153, second impurity regions 1150a, 1150
b, 1151a and 1151b are formed. Here, the second impurity region is a region (GOLD) overlapping the gate electrode.
Regions) 1150a and 1151a have a length of 1.5 μm,
Region (LDD region) 1150 not overlapping with gate electrode
b and 1151b are each formed to a length of 1.5 μm. Then, the first impurity region 1152 serves as a source region, and the first impurity region 1153 serves as a drain region.

In the p-channel type TFT, similarly, a gate electrode having a clad structure is formed, and a channel formation region 115 is formed.
4. Third impurity regions 1155a1155b, 1156
a, 1156b are formed. Then, the third impurity regions 1155a and 1155b serve as source regions, and the third impurity regions 1156a and 1156b serve as drain regions.

The pixel TFT of the pixel matrix circuit
Are channel formation regions 1157 and 1161, first impurity regions 1160 and 1164, and second impurity region 115
8, 1159, 1162, 1163 are formed. Here, the second impurity region is a region 115 overlapping with the gate electrode.
Areas 1158b, 1159b, 1162b, 1163 that do not overlap with 8a, 1159a, 1162a, 1163a
b is formed.

In this way, as shown in FIG.
An active matrix substrate on which a CMOS circuit and a pixel matrix circuit are formed is manufactured. Further, a storage capacitor portion is simultaneously formed on the drain side of the n-channel TFT of the pixel matrix circuit.

[Embodiment 6] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described.

As shown in FIG. 16A, the second interlayer insulating film 3 is applied to the active matrix substrate in the state shown in FIG.
A light-shielding film 1601 and a third interlayer insulating film 1602 are formed on 81. The light-blocking film 1601 is an organic resin film containing a pigment,
It is preferable to use a metal film such as Ti or Cr. Further, the third interlayer insulating film 1602 is formed using an organic resin film such as polyimide. Then, a contact hole reaching the drain wiring 379 is formed in the third interlayer insulating film 1602 and the second interlayer insulating film 381, and a pixel electrode 1603 is formed. The pixel electrode 1603 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and the pixel electrode 16 is formed.
03 is formed.

The material for the transparent conductive film is etched with a hydrochloric acid-based solution. However, since a residue is easily generated in the etching of ITO, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) is used to improve the etching processability.
May be used. Indium zinc oxide alloys are characterized by having excellent surface smoothness and thermal stability as compared with ITO. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO :) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light.
Ga) can be used.

Next, as shown in FIG. 16B, an alignment film 1604 is formed on the third interlayer insulating film 1602 and the pixel electrode 160.
3 is formed. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A transparent conductive film 1606 and an alignment film 1607 are formed over the substrate 1605 on the opposite side. After the alignment film is formed, a rubbing treatment is performed so that the liquid crystal molecules are parallel-aligned with a certain pretilt angle.

Through the above steps, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the opposing substrate are pasted by a well-known cell assembling step via a sealing material or a spacer (both not shown). Match. After that, a liquid crystal material 1608 is injected between the two substrates,
Completely seal with a sealant (not shown). Accordingly, an active matrix liquid crystal display device illustrated in FIG. 16B is completed.

Next, the configuration of the active matrix type liquid crystal display device of this embodiment will be described with reference to FIGS. 14 and 15A and 15B. FIG. 14 is a perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel matrix circuit 1401 formed over a glass substrate 301, a scanning (gate) line driving circuit 1402,
A data (source) line driving circuit 1403 is provided. The pixel TFT 1400 of the pixel matrix circuit is an n-channel type T
The driving circuit is an FT, and a peripheral driving circuit is configured based on a CMOS circuit. The scanning (gate) line driving circuit 1402 and the data (source) line driving circuit 1403 are connected to the pixel matrix circuit 1401 by a gate wiring 1502 and a source wiring 1503, respectively.

FIG. 15A shows a pixel matrix circuit 140.
1 is a top view of substantially one pixel. FIG. The pixel matrix circuit has an n-channel type TFT which is a pixel TFT.
Is provided. A gate electrode 1520 formed continuously to the gate wiring 1502 intersects with the underlying semiconductor layer 1501 via a gate insulating film (not shown). Although not shown, the semiconductor layer includes a source region,
A drain region and a first impurity region are formed. On the drain side of the pixel TFT, a storage capacitor 1507 is formed from a semiconductor layer, a gate insulating film, and an electrode formed of the same material as the gate electrode. Further, a capacitor wiring 1521 connected to the storage capacitor 1507 is provided in parallel with the gate wiring 1502. FIG.
The cross-sectional structure along AA ′ shown in FIG. 5A corresponds to the cross-sectional view of the CMOS circuit shown in FIG.

On the other hand, in the CMOS circuit shown in FIG. 15B, a gate electrode 151 extending from a gate wiring 1515 is provided.
3 and 1514 intersect the semiconductor layers 1510 and 1512 thereunder via a gate insulating film (not shown), respectively. Although not shown, an n-channel type T
The FT semiconductor layer includes a source region, a drain region, and a first region.
Impurity regions are formed. In addition, p-channel type T
A source region and a drain region are formed in the FT semiconductor layer. As for the positional relationship, the cross-sectional structure along BB ′ corresponds to the cross-sectional view of the pixel matrix circuit illustrated in FIG.

In this embodiment, the pixel TFT 1400 has a double gate structure. However, the pixel TFT 1400 may have a single gate structure or a triple gate multi-gate structure. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of a gate electrode, the structure of a source region, a drain region, and other impurity regions of a semiconductor layer provided with a gate insulating film interposed therebetween. The practitioner may decide appropriately.

The active matrix substrate for manufacturing the active matrix type liquid crystal display device shown in this embodiment is not limited to the one shown in the first embodiment but is based on the steps shown in the second to fifth and seventh embodiments. Any active matrix substrate manufactured by the above method can be used.

[Embodiment 7] In this embodiment, a method for simplifying the gettering step in the method for manufacturing an active matrix substrate shown in Embodiment 5 will be described. First, Example 5
In FIG. 11, a semiconductor layer 1103 shown in FIG.
Reference numerals 1104 and 1105 denote crystalline silicon films manufactured using a catalytic element. At this time, since the catalyst element used in the crystallization step remains in the semiconductor layer, it is desirable to perform the gettering step. In the fifth embodiment, after the crystalline silicon film is obtained, phosphorus is added to a part of the crystalline silicon film to perform gettering, but here, the gettering step is not performed. Then, the catalytic element is removed from the channel forming region of the TFT by the method described below.

Here, FIGS. 11 (A) to 12 (C)
The process is performed as it is until the process shown in FIG. Then, the resist masks 1137, 1138, 1139, 1140, 114
Remove one.

At this time, phosphorus is added to the first impurity regions 1152, 1153, 1160, and 1164 of the n-channel TFT. The third of the p-channel TFTs
Phosphorus is similarly added to the impurity regions 1155b and 1156b. According to the fifth embodiment, the phosphorus concentration at this time is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

In this state, the gate insulating film and the gate electrode are covered with a silicon nitride film 1180 as shown in FIG. The silicon nitride film is formed by a plasma CVD method,
It is formed to a thickness of 00 nm, here 50 nm. A silicon oxynitride film may be used instead of the silicon nitride film.

In the fifth embodiment, the third layer of the gate electrode is M
It is formed of oW. In addition, Ti, Ta, Mo, W
Alternatively, it may be formed. These materials are relatively easily oxidized by heat treatment at atmospheric pressure or while purging nitrogen gas. In such a situation, if the surface is covered with silicon nitride, oxidation can be prevented.

In this state, 400 to 80 in a nitrogen atmosphere.
A heat treatment process is performed at 0 ° C. for 1 to 24 hours, for example, at 600 ° C. for 12 hours. By this step, the added impurity element imparting n-type and p-type can be activated. Further, the region to which phosphorus is added becomes a gettering site, and the catalyst element remaining after the crystallization step can be segregated. As a result, the catalyst element can be removed from the channel formation region. As a result, an effect of reducing off current in the completed TFT can be obtained.

After the step of FIG. 22 is completed, the subsequent steps are the same as those of the fifth embodiment to form a first interlayer insulating film, a source wiring and a drain wiring, a passivation film, and a second interlayer insulating film. By forming a state, an active matrix substrate can be manufactured.

[Embodiment 8] In this embodiment, another example of the circuit configuration of the CMOS circuit shown in FIG. 1 will be described with reference to FIG. Note that the terminals a, b, c, and d in the inverter circuit diagram of FIG. 23A and the top view of the inverter circuit of FIG. 23B correspond to each other.

FIG. 23B is a top view of the inverter circuit shown in FIG. FIG. 23C shows a cross-sectional structure taken along the line AA ′ of FIG.
409, 2409 ′, an n-channel TFT source wiring 2411, a p-channel TFT source wiring 2414,
It is composed of a common drain wiring 2413. Here, the gate electrodes 2409 and 2409 ′ are a first layer 2408 and 2408 ′ of the gate electrode, a second layer 2409 and 2409 ′ of the gate electrode, and a third layer 241 of the gate electrode.
0, 2410 'represent an integrated state.

An n-channel TFT of this inverter circuit
Is provided with a second impurity region 2402. Specifically, a second impurity region 2402a which overlaps with the gate electrode 2409 and a second impurity region (LDD region) 2402b which does not overlap are formed. Such a structure may be provided only on the drain side. Further, such an impurity region is not provided in the p-channel TFT.

[Embodiment 9] In the above-described liquid crystal display device of the present invention, various liquid crystals other than the nematic liquid crystal can be used. For example, 1998, SID, "Characteristics an
d Driving Schemeof Polymer-Stabilized Monostable F
LCD Exhibiting Fast Response Time and High Contrast
Ratio with Gray-Scale Capability "by H. Furue et
al., 1997, SID DIGEST, 841, "A Full-Color Thresh
oldless Antiferroelectric LCDExhibiting Wide Viewi
ng Angle with Fast Response Time "by T. Yoshida et
al., 1996, J. Mater. Chem. 6 (4), 671-673, "Thres
holdless antiferroelectricity in liquid crystals a
nd its application to displays "by S. Inui et al.
Alternatively, the liquid crystal disclosed in U.S. Pat. No. 5,594,569 can be used.

Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 24 shows the electro-optical characteristics of a monostable FLC in which the cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 24 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 24 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Tsuki, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol.
See page 0 for details.

As shown in FIG. 24, when such a ferroelectric mixed liquid crystal is used, it can be seen that low voltage driving and gradation display are possible. The liquid crystal display device of the present invention includes:
A ferroelectric liquid crystal having such electro-optical characteristics can also be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

[Embodiment 10] An active matrix substrate, a liquid crystal display device and an organic EL display device manufactured according to the present invention can be used for various electro-optical devices. The present invention can be applied to all electronic devices incorporating such an electro-optical device as a display unit. Examples of the electronic device include a mobile phone, a video camera, a portable information terminal, a goggle-type display, a player of a recording medium, a portable book, a personal computer, a digital camera, and a projector. Examples of these are shown in FIGS.

FIG. 25A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 25B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention can be applied to the display device 9102 and other signal control circuits.

FIG. 25C shows a portable information terminal, which comprises a main body 9201, an image input section 9202, an image receiving section 9203, operation switches 9204, and a display device 9205. The present invention can be applied to the display device 9205 and other signal control circuits.

FIG. 25D shows a goggle type display, which comprises a main body 9301, a display device 9302, and an arm 93.
03. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 25E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 9401, a display device 9402, and a speaker 9.
403, a recording medium 9404, and operation switches 9405. The recording medium is a DVD (Digital Versati
le Disc) and compact disc (CD)
Playback of music programs, video display, video games (or video games), information display via the Internet, and the like can be performed. The present invention can be suitably used for the display device 9402 and other signal control circuits.

FIG. 25F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 25G shows a personal computer, which includes a main body 9601 having a microprocessor, a memory, and the like, an image input portion 9602, a display device 9603, and a keyboard 9604. The present invention relates to a display device 96.
03 and other signal processing circuits can be formed.

FIG. 26H shows a digital camera, which comprises a main body 9701, a display device 9702, an eyepiece 9703, operation switches 9704, and an image receiving unit (not shown). The present invention can be applied to the display device 9702 and other signal control circuits.

FIG. 26A shows a front type projector, which comprises a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to a display device and other signal control circuits. FIG. 26B illustrates a rear type projector, which includes a main body 2701, a light source optical system and a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to a display device and other signal control circuits.

FIG. 26C shows the light source optical system and the display device 26 shown in FIGS. 26A and 26B.
01 and 2702 are shown as examples. A light source optical system and display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810.
It consists of. The projection optical system 2810 includes a plurality of optical lenses. FIG. 26C illustrates a liquid crystal display device 2808.
Although an example of a three-plate system using three is shown, the present invention is not limited to such a system, and a single-plate optical system may be used. In the optical path indicated by the arrow in FIG. 26C, a suitable optical lens, a film having a polarizing function, a film for adjusting a phase, an IR film, or the like may be provided. FIG. 26D shows the light source optical system 2 shown in FIG.
801 is a diagram showing an example of the structure of FIG. In this embodiment,
The light source optical system 2801 includes a reflector 2811 and a light source 28.
12, a lens array 2813, 2814, a polarization conversion element 2815, and a condenser lens 2816. FIG.
The light source optical system shown in FIG. 6D is an example, and is not limited to the illustrated configuration.

Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like.
As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Also,
The electronic apparatus according to the present embodiment can be realized by using any combination of the embodiment and any of Embodiments 1 to 9 and Embodiment 11.

[Embodiment 11] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 27A is a top view of an EL display device using the present invention. In FIG. 27A, 4010
Denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit.
And connected to the external device.

At this time, the cover member 600 is formed so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 27B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed.

The present invention relates to a TFT 4022 for a driving circuit,
It can be used for the pixel portion TF4023.

By using the present invention, the TFT 402 for the driving circuit
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. Pixel electrode 4027
Is a transparent conductive film, the TFT for the pixel portion has p
It is preferable to use a channel type TFT. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O) or a compound of indium oxide and zinc oxide. Then, the pixel electrode 4027
Is formed, an insulating film 4028 is formed, and the pixel electrode 40 is formed.
An opening is formed on 27.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Furthermore, a sealing material is provided inside the cover member 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0210] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

[0212] As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

[0213] However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 12] In this embodiment, an example in which an EL display device different from that of Embodiment 11 is manufactured by using the present invention will be described with reference to FIGS. 27A and 27B denote the same parts, and a description thereof will not be repeated.

FIG. 28A is a top view of the EL display device of this embodiment, and FIG. 28B is a cross-sectional view taken along line AA ′ of FIG.

In accordance with Embodiment 11, a passivation film 6003 is formed to cover the surface of the EL element.

[0218] Further, the filling material 6 is formed so as to cover the EL element.
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0219] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 13] In this embodiment, FIG. 29 shows a detailed sectional structure of a pixel portion of an EL display device, and FIG.
FIG. 30A shows a circuit diagram. FIG. 29, FIG.
Since 0 (A) and FIG. 30 (B) use the same reference numerals, they may be referred to each other.

In FIG. 29, a switching TFT 3002 provided on a substrate 3001 is formed by using the n-channel TFT of the present invention (see Examples 1 to 8). In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, it may be formed using the p-channel TFT of the present invention.

The current control TFT 3003 is formed using the n-channel TFT of the present invention. At this time, the drain wiring 30 of the switching TFT 3002
Reference numeral 35 is electrically connected to a gate electrode 3037 of the current controlling TFT by a wiring 3036. Also, 303
The wiring indicated by 8 is a gate wiring for electrically connecting the gate electrodes 3039a and 3039b of the switching TFT 3002.

At this time, it is very important that the current controlling TFT 3003 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which a GOLD region (second impurity region) is provided on the drain side of the current controlling TFT so as to overlap with the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 30
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 30A, the wiring which becomes the gate electrode 3037 of the current controlling TFT 3003 is in the region indicated by 3004 and the current controlling TFT 3003
Overlap with the drain wiring 3040 via the insulating film. At this time, a capacitor is formed in a region indicated by 3004. This capacitor 3004 is used for the current control TFT 30.
It functions as a capacitor for holding the voltage applied to the gate of the gate 03. Note that the drain wiring 3040 is connected to a current supply line (power supply line) 3006, and a constant voltage is constantly applied.

The first passivation film 3 is formed on the switching TFT 3002 and the current control TFT 3003.
041 is provided, and a flattening film 3042 made of a resin insulating film is formed thereon. TF using the flattening film 3042
It is very important to flatten the step due to T. Since an EL layer formed later is extremely thin, light emission failure may occur due to the presence of a step. Therefore, E
It is desirable to planarize the pixel layer before forming the pixel electrode so that the L layer can be formed as flat as possible.

Reference numeral 3043 denotes a pixel electrode (cathode of an EL element) made of a highly reflective conductive film, and a current control TF
It is electrically connected to the drain of T3003. In this case, an n-channel TF is used as the current control TFT.
It is preferable to use T. As the pixel electrode 3043, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.

Although there are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylenevinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of an organic EL material that can be used as a light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, the PED is formed on the light emitting layer 3045.
EL having a laminated structure provided with a hole injection layer 3046 made of OT (polythiophene) or PAni (polyaniline)
And layers. An anode 47 made of a transparent conductive film is provided on the hole injection layer 3046. In the case of this embodiment, since the light generated in the light emitting layer 3045 is emitted toward the upper surface (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, the formation is possible after forming a light-emitting layer or a hole-injection layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

At the point when the anode 3047 is formed, the EL element 3005 is completed. The EL element 30 referred to here
05 denotes a pixel electrode (cathode) 3043, a light emitting layer 3045,
It refers to a capacitor formed by the hole injection layer 3046 and the anode 3047. As shown in FIG.
Since 43 substantially corresponds to the area of the pixel, the entire pixel is EL
Functions as an element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In this embodiment, a second passivation film 3048 is further provided on the anode 3047. As the second passivation film 3048, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 29, and a switching TFT having a sufficiently low off-state current value and a current controlling portion having a strong resistance against hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment can be freely combined with the structures of the first to eighth embodiments. In addition, as the display unit of the electronic device of the tenth embodiment,
It is effective to use the L display device.

[Embodiment 14] In this embodiment, a structure in which the EL element 3005 in the pixel portion shown in Embodiment 13 is inverted will be described. FIG. 31 is used for the description. Note that the difference from the structure of FIG. 29 is only the EL element portion and the current controlling TFT, so that the other description will be omitted.

In FIG. 31, the current control TFT 310
Reference numeral 3 is formed using the p-channel TFT of the present invention. For the manufacturing process, Embodiments 1 to 8 may be referred to.

In this embodiment, the pixel electrode (anode) 3050
Is used as a transparent conductive film. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the bank 3051a made of an insulating film,
After the formation of 3051b, the light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 3053 made of potassium acetylacetonate (denoted as acacK) and a cathode 3054 made of an aluminum alloy are formed thereon. In this case, the cathode 305
4 also functions as a passivation film. Thus E
An L element 3101 is formed.

In the case of this embodiment, the light generated in the light emitting layer 3052 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 8.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the tenth embodiment.

[Embodiment 15] In this embodiment, FIG.
32A to 32C show an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, 3201 is a source wiring of the switching TFT 3202, 3203 is a gate wiring of the switching TFT 3202, 3204 is a current control TFT, 3205 is a capacitor, 3206 and 3208 are current supply lines, and 320
Reference numeral 7 denotes an EL element.

FIG. 32A shows an example in which a current supply line 3206 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3206. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 32B shows the current supply line 320.
8 is provided in parallel with the gate wiring 3203. Note that although FIG. 32B illustrates a structure in which the current supply line 3208 and the gate wiring 3203 are provided so as not to overlap with each other, if the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3208 and the gate wiring 3203 can share an occupied area, the pixel portion can have higher definition.

FIG. 32C shows that the current supply line 3208 is connected to the gate wiring 3203 similarly to the structure of FIG.
a, it is characterized in that two pixels are formed so as to be symmetric with respect to the current supply line 3208. It is also effective to provide the current supply line 3208 so as to overlap with one of the gate wirings 3203a and 3230b. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 8.
In addition, it is effective to use the EL display device having the pixel structure of this embodiment as the display unit of the electronic device of the tenth embodiment.

[Embodiment 16] FIG. 30 shown in Embodiment 13
In (A) and (B), the capacitor 3004 is provided to hold the voltage applied to the gate of the current controlling TFT 3003; however, the capacitor 3004 can be omitted. In the case of Embodiment 13, the current control TF
Since the n-channel TFT of the present invention as shown in Embodiments 1 to 8 is used as T3003, there is a GOLD region (second impurity region) provided so as to overlap the gate electrode via the gate insulating film. are doing. In this overlapping region, a parasitic capacitance generally called a gate capacitance is formed. In the present embodiment, this parasitic capacitance is
The feature is that it is actively used instead of 004.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the GOLD region overlap, the GOL included in the overlapping region is set.
It is determined by the length of the D area.

Further, FIG. 32 (A) shown in Embodiment 15
Similarly, in the structures (B) and (C), the capacitor 3
It is possible to omit 205.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 8.
Further, it is effective to use the EL display device having the pixel structure of the present embodiment as the display unit of the electronic apparatus of the tenth embodiment.

[0258]

According to the present invention, a stable operation can be obtained even when the n-channel TFT of the pixel matrix circuit is driven by applying a gate voltage of 15 to 20 V. As a result, a CMO made of crystalline TFT
A semiconductor device including an S circuit, more specifically, a pixel matrix circuit of a liquid crystal display device, and a liquid crystal display device with high reliability that can be used for a long time by improving the reliability of a driver circuit provided therearound could be obtained. .

Also, according to the present invention, the n-channel type TF
In the second impurity region formed between the T channel formation region and the drain region, the length of the region (LDD region) where the second impurity region does not overlap with the region (GOLD region) overlapping with the gate electrode is It can be easily made separately. More specifically, the second voltage varies depending on the driving voltage of the TFT.
It is also possible to determine the length of the region (LDD region) where the impurity region does not overlap with the region (GOLD region) where the impurity region overlaps with the gate electrode. This means that when the TFT operation is performed with different drive voltages in the same substrate, TFTs corresponding to the respective drive voltages can be manufactured in the same process.

Further, such a feature of the present invention is very suitable for an active matrix type liquid crystal display device in which a driving voltage and required TFT characteristics are different between a pixel matrix circuit and a driver circuit.

[Brief description of the drawings]

FIG. 1 is a sectional view of a TFT according to an embodiment.

FIG. 2 illustrates a positional relationship between a gate electrode and a second impurity region.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 14 is a perspective view of an active matrix substrate.

FIG. 15 is a top view of an active matrix circuit and a CMOS circuit.

FIG. 16 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device.

FIG. 17 illustrates a structure of a gate electrode.

FIG. 18 illustrates a structure and electric characteristics of a TFT.

FIG. 19 is a view showing a manufacturing process of a crystalline silicon film.

FIG. 20 illustrates a manufacturing process of a crystalline silicon film.

FIG. 21 is a diagram illustrating a manufacturing process of a crystalline silicon film.

FIG. 22 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 23 is an inverter circuit diagram, a top view, and a cross-sectional structure diagram.

FIG. 24 is a view showing light transmittance characteristics of a ferroelectric mixed liquid crystal.

FIG 25 illustrates an example of a semiconductor device.

FIG. 26 illustrates a configuration of a projector.

27A and 27B are a top view and a cross-sectional view of an active matrix EL display device.

28A and 28B are a top view and a cross-sectional view of an active matrix EL display device.

FIG. 29 is a cross-sectional view of a pixel portion of an active matrix EL display device.

30A and 30B are a top view and a circuit diagram of a pixel portion of an active matrix EL display device.

FIG. 31 is a cross-sectional view of a pixel portion of an active matrix EL display device.

FIG. 32 is a circuit diagram of a pixel portion of an active matrix EL display device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/092 H01L 29/62 G 27/08 331 29/78 613A 29/43 617L

Claims (20)

[Claims] A semiconductor device in which a TFT having a semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film is formed on a substrate. The gate electrode is formed on a first layer of the gate electrode formed in contact with the gate insulating film, and on the first layer of the gate electrode and inside the first layer of the gate electrode. A second layer of the gate electrode; a third layer of the gate electrode formed in contact with the first layer of the gate electrode and the second layer of the gate electrode; A channel formation region and a first conductivity type
And a second impurity region of one conductivity type formed between the channel forming region and the first impurity region, and a part of the second impurity region of one conductivity type. A semiconductor device which overlaps a first layer of the gate electrode. 2. The one-conductivity-type second impurity region according to claim 1, wherein the one-conductivity-type second impurity region has a one-conductivity-type impurity element concentration. Semiconductor device characterized by being lower than the above. 3. The semiconductor device according to claim 1, wherein an impurity region of one conductivity type provided at one end of the semiconductor layer, the gate insulating film, a first layer of the gate electrode and a first electrode of the gate electrode. A semiconductor device, wherein a storage capacitor is formed from a wiring formed from a third layer, and the storage capacitor is connected to a source or a drain of the TFT. 4. A semiconductor device having a pixel TFT,
The gate electrode of the pixel TFT is formed on the first layer of the gate electrode formed in contact with the gate insulating film, and on the first layer of the gate electrode and inside the first layer of the gate electrode. A second layer of the gate electrode to be formed, and a third layer of the gate electrode formed in contact with the first layer of the gate electrode and the second layer of the gate electrode. The semiconductor layer includes a channel formation region, a first impurity region of one conductivity type, and a second impurity region of one conductivity type formed between the channel formation region and the first impurity region. And a part of the one-conductivity-type second impurity region overlaps a first layer of the gate electrode. 5. An n-channel TFT and a p-channel TFT
Wherein the gate electrode of the n-channel TFT is formed on the first layer of the gate electrode formed in contact with the gate insulating film and on the first layer of the gate electrode. And a second layer of the gate electrode formed inside the first layer of the gate electrode, and formed in contact with the first layer of the gate electrode and the second layer of the gate electrode. A third layer of a gate electrode, wherein the semiconductor layer of the n-channel TFT includes a channel formation region, a first impurity region of one conductivity type, the channel formation region and the first impurity region. A second impurity region of one conductivity type formed therebetween, and a part of the second impurity region of one conductivity type overlaps a first layer of the gate electrode; The semiconductor layer of the TFT has a channel formation region and A third impurity region in contact with the channel formation region, the third impurity region being in contact with the channel formation region and containing an impurity element having a conductivity type opposite to the one conductivity type; A semiconductor device having a region containing an impurity element and an impurity element having a conductivity type opposite to one conductivity type. 6. A semiconductor device having a pixel TFT and a CMOS circuit formed by an n-channel TFT and a p-channel TFT, wherein the gate electrodes of the pixel TFT and the n-channel TFT are:
A first layer of the gate electrode formed in contact with the gate insulating film; and a second layer of the gate electrode formed on the first layer of the gate electrode and inside the first layer of the gate electrode. Eye, a first layer of the gate electrode and a second layer of the gate electrode.
A third layer of a gate electrode formed in contact with the first layer, the semiconductor layer of the pixel TFT and the n-channel TFT includes a channel formation region, a first impurity region of one conductivity type, A second impurity region of one conductivity type formed between the channel formation region and the first impurity region; and a part of the second impurity region of one conductivity type is a gate electrode. And the semiconductor layer of the p-channel TFT has a channel formation region and a third impurity region in contact with the channel formation region, and the third impurity region is The semiconductor device includes a region which is in contact with the channel formation region and includes an impurity element having a conductivity type opposite to the one conductivity type, and a region including the impurity element having one conductivity type and an impurity element having a conductivity type opposite to the one conductivity type. Characteristic semiconductor device. 7. The semiconductor device according to claim 4, wherein the one-conductivity-type impurity region provided at one end of the semiconductor layer, the gate insulating film, and a first to a gate electrode of the gate electrode. A semiconductor device, wherein a storage capacitor is formed from a wiring formed from a third layer and the storage capacitor is connected to a source or a drain of the pixel TFT. 8. The semiconductor device according to claim 1, wherein the first layer of the gate electrode and the third layer of the gate electrode are formed of silicon (Si), titanium (Ti), Tantalum (Ta), tungsten (W), molybdenum (M
o) a semiconductor device comprising one or more elements selected from the group consisting of: 9. The semiconductor device according to claim 1, wherein the second layer of the gate electrode is made of aluminum (A).
1) or one or more elements selected from copper (Cu), or a compound containing the element as a main component. 10. The semiconductor device according to claim 1, wherein the semiconductor device is a display device using an organic electroluminescent material. 11. The semiconductor device according to claim 1, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera,
A semiconductor device, which is one selected from a digital video disc player, a goggle type display, and a projector. 12. A first step of forming a semiconductor layer on a substrate having an insulating surface; a second step of forming a gate insulating film in contact with the semiconductor layer; A third step of sequentially forming a conductive layer (A) and a conductive layer (B); etching the conductive layer (B) into a predetermined pattern;
A fourth step of forming a second layer of the gate electrode; a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer; the conductive layer (A) and the gate electrode A sixth step of forming a conductive layer (C) in contact with the second layer of (a), etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern, A seventh step of forming a third layer and a first layer of a gate electrode; and an eighth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer. Of manufacturing a semiconductor device. 13. A first step of forming a semiconductor layer on a substrate having an insulating surface; a second step of forming a gate insulating film in contact with the semiconductor layer; A third step of sequentially forming a conductive layer (A) and a conductive layer (B); etching the conductive layer (B) into a predetermined pattern;
A fourth step of forming a second layer of the gate electrode; a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer; the conductive layer (A) and the gate electrode A sixth step of forming a conductive layer (C) in contact with the second layer of (a), etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern, A seventh step of forming a third layer and a first layer of the gate electrode, an eighth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, A ninth step of removing a part of the first layer and part of the third layer of the gate electrode. 14. A first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface; and a gate insulating layer on the first semiconductor layer and the second semiconductor layer. A second step of forming a film; a third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film; and etching the conductive layer (B) into a predetermined pattern. do it,
A fourth step of forming a second layer of the gate electrode; a fifth step of adding an impurity element of one conductivity type to a selected region of the first semiconductor layer; A sixth step of forming a conductive layer (C) in contact with the second layer of the gate electrode; and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a gate. A seventh step of forming a third layer of the electrode and a first layer of the gate electrode; and adding an impurity element of one conductivity type to selected regions of the first semiconductor layer and the second semiconductor layer. And a ninth step of adding an impurity of a conductivity type opposite to one conductivity type to a selected region of the second semiconductor layer. Method. 15. A first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface; and a gate insulating layer on the first semiconductor layer and the second semiconductor layer. A second step of forming a film; a third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film; and etching the conductive layer (B) into a predetermined pattern. do it,
A fourth step of forming a second layer of the gate electrode; a fifth step of adding an impurity element of one conductivity type to a selected region of the first semiconductor layer; A sixth step of forming a conductive layer (C) in contact with the second layer of the gate electrode; and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a gate. A seventh step of forming a third layer of the electrode and a first layer of the gate electrode; and adding an impurity element of one conductivity type to selected regions of the first semiconductor layer and the second semiconductor layer. An eighth step of removing; a ninth step of removing a part of the first layer of the gate electrode and a part of the second layer of the gate electrode; A method of manufacturing a semiconductor device, comprising: a tenth step of adding to a selected region of a second semiconductor layer. . 16. A first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface; and a gate insulating layer on the first semiconductor layer and the second semiconductor layer. A second step of forming a film; a third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film; and etching the conductive layer (B) into a predetermined pattern. do it,
A fourth step of forming a second layer of the gate electrode; a fifth step of adding an impurity element of one conductivity type to a selected region of the first semiconductor layer; A sixth step of adding a conductive type impurity to a selected region of the second semiconductor layer; and a conductive layer (C) in contact with the conductive layer (A) and the second layer of the gate electrode. And forming the third layer of the gate electrode and the first layer of the gate electrode by etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern. An eighth step; and a ninth step of adding an impurity element of one conductivity type to selected regions of the first semiconductor layer and the second semiconductor layer. Method. 17. The semiconductor device according to claim 12, wherein the first layer of the gate electrode and the third layer of the gate electrode are formed of silicon (Si), titanium (T
i) one or more elements selected from tantalum (Ta), tungsten (W), molybdenum (Mo);
Alternatively, a method for manufacturing a semiconductor device, which is formed using a compound containing the above element as a component. 18. The method according to claim 12, wherein the second layer of the gate electrode comprises one or more elements selected from aluminum (Al) and copper (Cu); Alternatively, a method for manufacturing a semiconductor device is formed using a compound containing the above element as a main component. 19. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor device is a display device using an organic electroluminescent material. 20. The semiconductor device according to claim 12, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera,
A method for manufacturing a semiconductor device, which is one selected from a digital video disc player, a goggle type display, and a projector.