JP2001117533A - Matrix type picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix type picture display device capable of displaying even a plurality of pictures whose signal formats are different on a composite screen. SOLUTION: A panel 170 is divided into two blocks 170a, 170b since row electrodes are divided roughly at the center part of the left and right side of the panel. Driving circuits which are respectively constituted of S/P conversion circuits 14a, 14b, pulse width modulator/drivers 15a, 15b and scanning drivers 16a, 16b and video signal processing circuits which process video signals which are to be displayed by the driving circuits and which are respectively constituted of decoders 11a, 11b to control circuits 13a, 13b are respectively provided with respect to the blocks 170a, 170b. Since this display device has horizontal and vertical compressing and expanding circuits 18a, 18b in the video signal processing circuits, video signals are compressed or expanded in accordance with the pixels of the panel 170.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix having a matrix type display panel having a row electrode and a column electrode, and a plurality of pixels arranged in a matrix at intersections of the row electrode and the column electrode. More particularly, the present invention relates to a matrix type image display device capable of displaying a plurality of images of different signal formats on a composite screen in a plasma display, a liquid crystal display, an electroluminescence display, a field emission display, and the like.

[0002]

2. Description of the Related Art As an example of an image display device for displaying a composite screen, a configuration using a cathode ray tube (CRT) will be described.
This will be described with reference to FIG. In FIG. 5, the horizontal compression circuit 1
, A main screen video signal and a synchronization signal (hereinafter referred to as an input synchronization signal) separated from the main screen video signal are input. The horizontal compression circuit 1 compresses and outputs the main screen image signal in the horizontal direction, and outputs a synchronization signal (hereinafter referred to as an output synchronization signal) having a fixed phase relationship with the input synchronization signal. The compressed main screen image signal is input to one input terminal of the multiplexer circuit 4.

The scan converter circuit 2 receives a sub-screen video signal and a synchronizing signal (hereinafter referred to as an input synchronizing signal) separated from the sub-screen video signal. The scan converter circuit 2 compresses the sub-screen video signal using the input synchronization signal, and writes the compressed data to the image memory 3. Then, the scan converter circuit 2 reads the output synchronization signal from the horizontal compression circuit 1 and reads out the compressed data from the image memory 3 as a synchronization signal. As a result, the scan converter circuit 2 outputs a sub-screen video signal that is phase-synchronized with the main screen video signal. The synchronously converted sub-screen image signal is input to the other input terminal of the multiplexer circuit 4.

The multiplexer circuit 4 includes a horizontal compression circuit 1
The main screen video signal which has been subjected to the horizontal compression processing and the sub-screen image signal which has been synchronously converted from the scan converter circuit 2 are time-divided and output within a horizontal period. The output of the multiplexer circuit 4 is input to the CRT 5. The output synchronization signal from the horizontal compression circuit 1 is input to the deflection circuit 6, and the deflection circuit 6 drives the CRT 5. Thereby, CR
At T5, an image based on the main screen video signal and an image based on the sub-screen image signal are displayed on a composite screen. In FIG. 5, the main screen video signal and the sub screen image signal are component signals or R, G, B signals, and the signals are shown as one system here.

Here, a specific configuration of the horizontal compression circuit 1 will be described with reference to FIG. In FIG. 6, the main screen video signal is compressed to a predetermined size in the horizontal direction by a horizontal pre-filter 1a and a horizontal compression interpolation filter 1b.
The compressed data is written to the line memory 1c and sequentially read. The horizontal pre-filter 1a is for reducing aliasing noise generated due to compression.

At this time, horizontal compression interpolation processing by the horizontal compression interpolation filter 1b and write control of the line memory 1c are controlled by a horizontal compression control circuit 1d based on an input synchronization signal separated from the main screen video signal by synchronization.
The read control of the line memory 1c is controlled by the read control circuit 1e based on the input synchronization signal. From the read control circuit 1e, an output synchronization signal having a constant phase with respect to the input synchronization signal and having the same frequency is output to the outside. The input synchronization signal and the output synchronization signal are composed of horizontal and vertical synchronization signals, respectively.

Next, a specific configuration of the scan converter circuit 2 will be described with reference to FIG. In FIG.
The sub-screen video signal is compressed to a predetermined size in the horizontal and vertical directions by the horizontal / vertical pre-filter 2a and the horizontal / vertical compression interpolation filter 2b, and the compressed data is written to the image memory 3 and sequentially read. The horizontal / vertical pre-filter 2a is for reducing aliasing noise generated due to compression. Each of the horizontal / vertical pre-filter 2a and the horizontal / vertical compression / interpolation filter 2b has a built-in line memory, and performs vertical compression processing. It should be noted that the vertical compression processing is necessary for displaying the main screen and the sub-screen having the same size side by side, by adjusting the number of lines of the sub-screen video signal to the number of lines of the main screen video signal. Therefore, if the number of lines of the sub-screen video signal is the same as the number of lines of the main screen video signal, it is not necessary to perform the vertical compression processing.

At this time, the horizontal / vertical compression interpolation filter 2b
The writing control of the image memory 3 is controlled by the horizontal / vertical compression control circuit 2c based on the input synchronization signal separated from the sub-screen video signal. The image memory 3
Is controlled based on a read synchronization signal which is an output synchronization signal from the horizontal compression circuit 1.
e.

FIG. 8 shows a display example of a composite screen displayed on the CRT 5. Here, a case where a wide-type CRT having an aspect ratio of 16: 9 is used as the CRT 5 is shown.
The left screen in the figure is based on the main screen video signal, and the right screen in the figure is based on the sub-screen video signal. Main screen video signal is horizontal frequency, vertical frequency (field frequency)
Are 15.75 kHz and 60 Hz, respectively. The horizontal compression circuit 1 compresses the horizontal direction slightly more than 50%, and the deflection circuit 6 compresses the number of lines in the vertical direction to 480 lines. The sub-screen video signal also has horizontal and vertical frequencies of 15.75 kHz and 60 Hz, respectively, in synchronization with the main screen video signal. The scan converter circuit 2 compresses the horizontal direction to slightly less than 50% and reduces the number of lines in the vertical direction. Compressed to 400.

[0010]

The above-described conventional image display apparatus has the following problems. First, NTSC image signal and VGA (Video Graphics
A composite screen cannot be displayed with a personal computer image signal (Array: 31.5 kHz) or the like (hereinafter, referred to as a personal computer image signal). Horizontal frequency of NTSC image signal is 1
The horizontal frequency of a personal computer image signal such as VGA is 30 times that is twice or more than 5.75 kHz.
４０40 kHz. Therefore, the PC image signal is input to the horizontal compression circuit 1 and the NT signal is input to the scan converter circuit 2.
SC image signal is input, and conversely, N
It is not possible to input a TSC image signal and input a personal computer image signal to the scan converter circuit 2. this is,
For the following reasons.

The scan converter circuit 2 converts an input video signal into a specific format, in the above example, NTSC
Converted to image signal format. When a personal computer image signal is input as a main screen image signal, the output is 15.75 since the horizontal frequency is 31.5 kHz.
The phase of the scan converter circuit 2 operating in the vicinity of kHz cannot be synchronized. That is, in the configuration of FIG. 5, since the output side of the scan converter circuit 2 is phase-synchronized only near the horizontal frequency of the NTSC image signal, the condition is that both the main screen image signal and the sub-screen image signal are NTSC image signals. As described above, the configuration shown in FIG. 5 has a problem that video signals of different formats cannot be displayed on a composite screen.

Further, when the frame or field frequency of the main screen video signal is different from the frame or field frequency of the sub-screen video signal, in the configuration of FIG. 5, the frame (field) frequencies are close to each other in a fixed relationship or synchronized. If you do not, you can not respond. This is because the frame (field) frequencies are close to each other in a fixed relationship,
Alternatively, if they are not synchronized, a temporal overtaking / overtaking phenomenon occurs in the writing and reading operations of the video signal in the image memory 3.

The frequency at which this phenomenon occurs is related to the difference in frame (field) frequency between the main screen video signal and the sub-screen video signal. When the frequency of the sub-screen video signal is high, frame (field) thinning is performed, and when the frequency of the sub-screen video signal is low, frame (field) duplication occurs. This phenomenon has been a cause of a deterioration in image quality because the flow of a series of operations is instantaneously disturbed particularly in the case of moving images.

Furthermore, there are various formats for the personal computer image signal, and there is a problem that the capacity of the image memory 3 must be changed according to the format in a fixed system conversion. There is also a problem that the image memory 3 having the maximum capacity required for the system conversion must be provided in advance.

In the above example, the case of an image display device using a CRT has been described. However, if the conventional composite screen display method is used as it is for a matrix type image display device, it has exactly the same problems as described above. Becomes The present invention has been made in view of such a problem, and can display different images on a composite screen, does not deteriorate image quality, does not require a large-capacity image memory, and has a plurality of different signal formats. It is an object of the present invention to provide a matrix-type image display device that can also display a composite image on a composite screen.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention has a plurality of electrodes each having a row electrode and a column electrode, and having an intersection between the row electrode and the column electrode as a pixel. In a matrix-type image display device including a matrix-type display panel (170 to 172) in which pixels are arranged in a matrix, a plurality of the matrix-type display panels are obtained by dividing at least one of the row electrodes and the column electrodes. Blocks (170a, 170b, 171)
a to 171d, 172a, 172b), and driving circuits (14a to 14d, 15a to 15d, 20a, 20b,
21a, 21b, 22a, 22b) and video signal processing circuits (11a to 13a, 11b to 13b, A to D, A ',
B ′) is provided to provide a matrix-type image display device.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a matrix type image display device according to the present invention will be described with reference to the accompanying drawings. FIG.
Is a block diagram showing a first embodiment of the matrix type image display device of the present invention, FIG. 2 is a block diagram showing a second embodiment of the matrix type image display device of the present invention, and FIG. 3 is a matrix type image display of the present invention. Block diagram showing a third embodiment of the device,
FIG. 4 is a block diagram showing a basic configuration example of a matrix type image display device.

First, the basic configuration of the matrix type image display device will be described with reference to FIG. Here, a structure and operation using a field emission display panel driven by a line-sequential scanning method as a matrix display panel will be described. The field emission display panel 17 (hereinafter, panel 17) in FIG. 4 has a row electrode and a column electrode, and a plurality of pixels having a pixel at an intersection of the row electrode and the column electrode are arranged in a matrix of m rows × n columns. It is arranged in. That is, the display screen includes m display lines of n dots, and m row electrodes are provided for each display line of each row, and n column electrodes are provided for each column, corresponding to this pixel arrangement. Configuration.

In FIG. 4, a composite video signal is input to a decoder 11, and the decoder 11 separates and outputs luminance signals (R, G, B) of three primary colors and horizontal and vertical synchronization signals. R, G, B signals are parallel / serial (P
/ S) is input to the conversion circuit 12, and the horizontal and vertical synchronization signals are input to the control circuit 13.

The control circuit 13 generates various timing signals synchronized with the horizontal and vertical synchronizing signals, and supplies them to circuit components such as a column electrode driving circuit and a row electrode driving circuit, which will be described later. The control circuit 13 is initialized with a vertical synchronization signal, generates a vertical address by counting the horizontal synchronization signal, and generates a vertical address; a dot clock generation circuit that generates a dot clock phase-synchronized with the horizontal synchronization signal; A horizontal address generation circuit which is initialized by a horizontal synchronization signal and generates a horizontal address by counting a dot clock.

The P / S conversion circuit 12 generates serial signals arranged in the corresponding order of each pixel (fluorescent substance) of the panel 17 and inputs the serial signals to the serial / parallel (S / P) conversion circuit 14. The S / P conversion circuit 14 converts the input serial signal into a parallel signal for each row in the panel 17 and outputs a pulse width modulator (PWM) / driver 15
To enter. The PWM / driver 15 generates a drive pulse having a pulse width corresponding to the luminance of the R, G, B signals, and supplies the generated drive pulse to the column electrode of the panel 17. Thus, the panel 17 is driven in the column direction. The S / P conversion circuit 14 and the PWM / driver 15 are column electrode driving circuits of the panel 17.

The scan driver 16 generates a scan pulse for line-sequentially scanning the panel 17 based on the horizontal and vertical addresses from the control circuit 13, and supplies the scan pulse to the row electrodes of the panel 17. Thus, the panel 17 is driven in the row direction. The scan driver 16 is a row electrode drive circuit of the panel 17.

As described above, in the row where the scan driver 16 selectively supplies the scan pulse to the panel 17, the PWM
Only the pixel supplied with the drive pulse from the driver 15 emits electrons for a period corresponding to the pulse width of the drive pulse, and the phosphor emits light. When the scanning driver 16 sequentially moves the row to which the scanning pulse is supplied, the panel 17 is sequentially scanned in the row direction, and a two-dimensional image is formed on the panel 17. In addition, PWM / driver 1
When the voltage modulation is used instead of the pulse width modulation by 5, the drive pulse has a voltage value corresponding to the luminance of the video signal.

Next, first to third embodiments of the matrix type image display device according to the present invention will be described in order.

<First Embodiment> First, the structure of the panel used in the first embodiment will be described. In FIG. 1, the panel 170 is divided into two blocks in the left-right direction by dividing the row electrodes at substantially the right and left central portions, and the left block 170a and the right block 170b are integrated. One panel 170 is formed. Then, as described later, the left and right blocks 170a, 170
It is characterized in that a row electrode drive circuit and a column electrode drive circuit are provided for each b. Further, if the block 170a is used for the main screen and the block 170b is used for the sub-screen, the main-screen and sub-screen blocks 170a and 170b are respectively provided with a video signal processing circuit for the main screen video signal and Are provided independently of each other. As a result, the left and right blocks 170a and 170b display images independently of each other.

In FIG. 1, a composite video signal which is a main screen video signal is input to a decoder 11a, and the decoder 11a separates luminance signals (R, G, B) of three primary colors and horizontal and vertical synchronization signals. Output. The R, G, and B signals are input to the horizontal / vertical compression / expansion circuit 18a. The horizontal / vertical compression / expansion circuit 18a compresses or expands the input R, G, B signals in the horizontal or vertical direction according to the number of pixels of the main screen block 170a. The output of the horizontal / vertical compression / expansion circuit 18a is input to the P / S conversion circuit 12a and the selection circuit 19.

Decoder 11a, horizontal / vertical compression / expansion circuit 1
8a, a P / S conversion circuit 12a, and a control circuit 13a are video signal processing circuits that process main screen video signals. S / P
The conversion circuit 14a and the PWM / driver 15a are column electrode driving circuits that drive the main screen block 170a.
The scanning driver 16a is a row electrode driving circuit that drives the main screen block 170a. P / S conversion circuit 12a,
The operations of the control circuit 13a, the S / P conversion circuit 14a, the PWM / driver 15a, and the scanning driver 16a are the same as those in FIG. The operation of the selection circuit 19 will be described later.

On the other hand, a composite video signal which is a sub-screen video signal is input to the decoder 11b.
b separates and outputs luminance signals (R, G, B) of three primary colors and horizontal and vertical synchronization signals. The R, G, and B signals are input to the horizontal / vertical compression / expansion circuit 18b. The horizontal / vertical compression / expansion circuit 18b compresses or expands the input R, G, B signals in the horizontal or vertical direction according to the number of pixels of the sub-screen block 170b. The output of the horizontal / vertical compression / expansion circuit 18b is input to the P / S conversion circuit 12b via the selection circuit 19.

Decoder 11b, horizontal / vertical compression / expansion circuit 1
8b, a P / S conversion circuit 12b, and a control circuit 13b are video signal processing circuits that process sub-screen video signals. S / P
The conversion circuit 14b and the PWM / driver 15b are column electrode driving circuits that drive the sub-screen block 170b.
The scanning driver 16b is a row electrode driving circuit that drives the sub-screen block 170b. P / S conversion circuit 12b,
The operations of the control circuit 13b, the S / P conversion circuit 14b, the PWM / driver 15b, and the scanning driver 16b are the same as those in FIG.

In the above configuration, in order to display a composite screen of the main screen video signal and the sub-screen video signal on the panel 170, the selection circuit 19 selects the output of the horizontal / vertical compression / expansion circuit 18b and performs P / S It is supplied to the conversion circuit 12b. In this case, the main block video signal is displayed in the left block 170a, and the sub-screen video signal is displayed in the right block 170b. Since the video signal processing circuit for the main screen video signal and the video signal processing circuit for the sub-screen video signal are independent of the input stage, there is no need for synchronous conversion processing when displaying a composite screen. Therefore, even if the format of the main screen video signal and the sub-screen video signal is different like the NTSC image signal and the PC image signal, or the horizontal frequency and the frame (field) frequency are different, the composite screen is displayed without deterioration of the image quality. can do. Further, an image memory for synchronous conversion processing is not required.

Further, in the above configuration, a single screen can be displayed. To display the main screen video signal on the panel 170 as a single screen, the selection circuit 19 may select the output of the horizontal / vertical compression / expansion circuit 18a and supply it to the P / S conversion circuit 12b. Horizontal / vertical compression / expansion circuit 1
At 8a, the input R, G, B signals are compressed or expanded in the horizontal or vertical direction according to the number of pixels of the entire panel 170. The signal of the portion to be displayed in the block 170a is directly input to the P / S conversion circuit 12a, and the signal of the portion to be displayed in the block 170b is input to the P / S conversion circuit 12b via the selection circuit 19.
Thus, a single screen can be displayed.

<Second Embodiment> In a panel 171 used in the second embodiment shown in FIG. 2, the row electrodes are divided at substantially right and left central parts, and the column electrodes are also divided at substantially vertical central parts. ,
It is divided into four blocks. Upper left block 1
71a, the upper right block 171b, the lower left block 171c, and the lower right block 171d are integrated into one.
One panel 171 is formed. A row electrode driving circuit and a column electrode driving circuit are provided for each of the four blocks 171a to 171d, and a video signal processing circuit for a main screen video signal or a sub screen video signal is independently provided in each of the four blocks 171a to 171d. It is characterized by having. As a result, the four blocks 171a to 171d display images independently of each other.

In FIG. 2, the upper left block 171a
A decoder 11a, a horizontal / vertical compression / expansion circuit 18a, and a P / S conversion circuit 12a are provided for a column electrode drive circuit including a S / P conversion circuit 14a and a PWM / driver 15a and a row electrode drive circuit including a scan driver 16a. , A video signal processing circuit A for a main screen video signal, comprising a control circuit 13a. S / P conversion circuit 14b and PWM / driver 15 for driving upper right block 171b
The video signal processing circuit B for the first sub-screen video signal is connected to the column electrode drive circuit consisting of b and the row electrode drive circuit consisting of the scan driver 16b.

Further, an S / P conversion circuit 14c for driving the lower left block 171c and a PWM / driver 15c
A video signal processing circuit C for a second sub-screen video signal is connected to a column electrode drive circuit composed of a column electrode drive circuit and a row electrode drive circuit composed of a scan driver 16c. Lower right panel 1
A column electrode drive circuit including an S / P conversion circuit 14d and a PWM / driver 15d for driving the scan driver 71d;
A video signal processing circuit D for a third sub-screen video signal is connected to the row electrode drive circuit composed of 6d. The configuration of the video signal processing circuits B to D for the sub-screen video signal is the same as that of the video signal processing circuit A for the main screen video signal.

In the first embodiment described above, the panel is divided into two by dividing the row electrodes into right and left. In the second embodiment, the panel is divided into four by dividing both the row electrodes and the column electrodes. The panel may be divided into upper and lower parts by dividing the electrodes, or at least one of the row electrodes and the column electrodes may be further divided so as to divide the panel into more blocks. Further, the sizes of the blocks of the divided panel may be different from each other. How to divide the image may be determined depending on how the main screen image signal and the sub screen image signal are displayed, and the number of divisions and the manner of division may be set as appropriate. Further, each block 170a, 170b,
If the video signal to be displayed is fixed in any of 171a to 171d, the horizontal / vertical compression / decompression circuit does not need to be provided in all video signal processing circuits.

<Third Embodiment> In the first and second embodiments, the display device using the line-sequential scanning type panel has been described. However, in the third embodiment, the plane-sequential scanning type such as the plasma display panel is used. Of the display device of FIG. Since the driving method of the plasma display panel is well known, detailed description thereof is omitted here. The plasma display panel has a three-electrode structure of an address electrode, an X electrode, and a Y electrode. Address driving is performed by a column electrode and one row electrode, and thereafter, an AC voltage is applied between the X and Y electrodes in a row direction. Apply and perform sustain discharge to display.

In the prior art, X and Y electrodes were drawn to the left and right of the plasma display panel. In contrast, in the present invention, as shown in FIG. , Y electrodes are drawn out to the left and right.

In FIG. 3, the plasma display panel 172 (hereinafter, panel 172) is divided into two blocks in the left-right direction by dividing the row electrodes at substantially the right and left central portions. And the right block 172b are integrated into one panel 17
2 are formed. The address driver 20a is connected to the left block 172a, and the right block 172a.
The address driver 20b is connected to b. An X driver 21a and a Y driver 22a are alternately connected in the row direction of the electrodes to the left block 172a, and the X driver 21b and the Y driver 2 are also connected to the right block 172b.
2b are alternately connected in the row direction of the electrodes. And
In each of the left and right blocks 172a and 172b, a video signal processing circuit A 'for a main screen video signal and a video signal processing circuit B' for a sub-screen video signal are independently provided. As a result, the left and right blocks 172a and 172b display images independently of each other.

When only the row electrodes of the panels 170 and 172 are divided as in the first and third embodiments,
Since the column electrode drive circuit is only divided in the horizontal direction,
The number of integrated circuits (ICs) constituting the column electrode driving circuit is substantially the same as the conventional one, and the cost does not increase. The row electrode drive circuit includes left and right blocks 170a, 170b, 17
2A and 172b, the number of ICs constituting the row electrode driving circuit is doubled. However, there is a secondary effect that the voltage drop due to the row electrode resistance can be halved.

[0040]

As described in detail above, the matrix type image display device of the present invention is a matrix type display panel in which at least one of a row electrode and a column electrode is divided into a plurality of blocks. The driving circuit for driving each block of the matrix type display panel and the video signal processing circuit for processing a video signal to be displayed by the driving circuit are provided for each of the plurality of blocks. Can display different images from each other. Also, there is no deterioration in image quality, no large-capacity image memory is required, and the horizontal and vertical scanning frequencies are different from each other, such as interlaced signals and non-interlaced signals, and NTSC image signals and personal computer image signals. A plurality of images having the same signal format can be displayed on the composite screen.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating a basic configuration example of a matrix type image display device.

FIG. 5 is a block diagram illustrating a configuration example of an image display device that displays a composite screen using a cathode ray tube.

6 is a block diagram showing a specific configuration of the horizontal compression circuit 1 in FIG.

FIG. 7 is a block diagram showing a specific configuration of a scan converter circuit 2 in FIG.

FIG. 8 is a diagram showing a display example of a composite screen.

[Explanation of symbols]

11a, 11b Decoder 12a, 12b Parallel / Serial Conversion Circuit 13a, 13b Control Circuit 14a-14d Serial / Parallel Conversion Circuit (Column Drive Circuit) 15a-15d Pulse Width Modulator / Driver (Column Drive Circuit) 16a-16d Scan Driver ( Row driving circuit) 18a, 18b Horizontal / vertical compression / expansion circuit 19 Selection circuit 20a, 20b Address driver 21a, 21b X driver 22a, 22b Y driver 170-172 Matrix type display panel 170a, 170b, 171a-171d, 172a,
172b block AD, A ', B' video signal processing circuit

Claims (2)

[Claims] 1. A matrix-type image display device comprising a matrix-type display panel having a row electrode and a column electrode, and a plurality of pixels arranged in a matrix at intersections of the row electrode and the column electrode. In the above, a panel divided into a plurality of blocks by dividing at least one of the row electrode and the column electrode is used as the matrix display panel, and each block of the matrix display panel is used for each of the plurality of blocks. And a video signal processing circuit for processing a video signal to be displayed by the drive circuit. 2. The video signal processing circuit according to claim 1, wherein at least one of said video signal processing circuits is provided with a horizontal / vertical compression / expansion circuit for compressing / expanding said video signal in a horizontal or vertical direction. Matrix image display device.