JP4529443B2 - Display device and driving method of display device - Google Patents

Description

  The present invention relates to a display device and a display device driving method, and more particularly to a large display device configured by bonding a plurality of small display devices on a large substrate and a driving method of the display device.

  In recent years, panel-type (thin) display devices in which pixels including self-luminous elements (self-luminous elements) typified by organic EL (Electro Luminescence) elements are arranged in a matrix have attracted attention as high-luminance displays. ing. These self-light-emitting display devices are self-light-emitting elements, so that a backlight like a liquid crystal display device is unnecessary and the entire display panel can be thinned to about 1 to 2 mm. It has the advantages of high response, fast response speed, high brightness, high contrast, and low power consumption, and is regarded as a promising candidate for next-generation displays.

  Among self-luminous display devices, organic EL display devices using, for example, organic EL elements as self-luminous elements of pixels are now becoming small displays for mobile devices (portable information devices) such as digital cameras and mobile phones. In the future, application to medium- and large-sized displays such as monitors for PCs (personal computers) and televisions is considered. In recent years, the market for large-sized televisions with a diagonal size exceeding 30 to 60 inches using liquid crystal display devices and plasma display devices has been expanded, and the demand for larger panel-type (thin) display devices has further increased. ing.

  In order to satisfy these demands, it is necessary to develop innovative technologies that have never existed before. However, in the case of an organic EL display device, it is difficult to increase the size of the device. The reason for this is that, for example, as the substrate size increases, the equipment becomes larger, the cost increases, and it is difficult to uniformly form the organic EL film on the large screen. It is difficult to make uniform. In the case of an active matrix display device, a TFT (Thin Film Transistor) is usually used as an active element for driving an organic EL element in a pixel. However, as the screen becomes larger, the yield such as pixel defects becomes worse. Therefore, one of the problems is that productivity cannot be obtained.

  In order to solve these problems, a technique for configuring a large screen by pasting a plurality of small panels on a tile has been tried (for example, see Patent Document 1). Patent Document 1 discloses a technique for manufacturing a large organic EL display device by bonding a plurality of small display devices including a plurality of organic EL elements on a large substrate. In such a bonded structure of display devices, an arbitrary size display device can be manufactured by arranging an arbitrary number of display devices.

Japanese Patent Laid-Open No. 2002-372928

  As described above, in a large display device configured by bonding a plurality of small display devices on a large substrate, various characteristics such as brightness and color of the small display device are different for each small display device. When a single large display device is configured by pasting them together, there is a problem that the joints of the pasted portions are recognized due to different characteristics of the small display devices.

  As a technique for making the joint inconspicuous, a method of correcting the luminance and color of the display image is conceivable. By performing the correction for each small display device, the joint can be made inconspicuous. As a method of performing the correction, for example, by using a dedicated correction IC (Integrated Circuit) specialized for the correction for each small display device, it is possible to easily and inexpensively correct the brightness and color of the panel. It is possible to realize.

  Among these correction ICs, correction ICs equipped with a PLL (Phase Locked Loop) function for adjusting the phase and frequency of the output signal with respect to the input signal are used for each small display device. When the image data signal output from the correction IC is combined with the image data signal of one display image, the jitter of the display image (left and right display blur) is caused by the phase difference between the image data signals generated between the correction ICs. Will occur. This is considered to be caused by the following.

(1) The characteristics of the PLL mounted on the correction IC are different.
(2) When a plurality of correction ICs are driven in parallel, the PLLs of the correction ICs operate independently (asynchronously), and thus cannot be synchronized with each other. This is a phenomenon that naturally occurs because the specification is not such that the correction IC can be used in parallel for multiple use.
(3) The characteristics of the PLL active filter (LPF) are different.
(4) Since the reference clock for adjusting the phase and frequency of the output signal of the correction IC is supplied from outside the IC, the reference clock signal is not When the correction IC is reached, the waveforms of the reference clock signals are slightly different from each other, and a phase difference is generated.

  More specifically, referring to FIG. 12, when four correction ICs are operated in parallel, a signal (synchronization signal) output from a correction IC in charge of a part other than the display screen A serving as a synchronization reference of the subsequent processing circuit. , The image data signal) changes with respect to the output signal of the display screen A every ± 1 CLK of the clock signal that is the reference of the circuit operation every 1V (one vertical period). When the C / D image data signal is combined on one screen, ± 1 CLK jitter (display blur) occurs in the display screens B, C, and D.

  As a method for solving these problems, a frame memory and a PLL are formed in a circuit portion that synthesizes an image signal output from these correction ICs into one image signal, and a circuit that adjusts each phase error is provided. However, since the circuit becomes complicated and the circuit scale becomes large, it cannot be easily realized and the cost becomes high.

  The present invention has been made in view of the above-mentioned problems, and the object of the present invention is to join the end face portions that are bonded together when a larger display area is obtained by bonding a plurality of small display devices. The phase difference between the signals generated between the correction ICs when the image signal output from the image correction IC provided for each display device is combined with the image signal of one display image. Another object of the present invention is to provide a display device capable of suppressing the jitter (left and right display blur) of a display image caused by the above-described problem and a method for driving the display device.

  In order to achieve the above object, in the present invention, a plurality of display means in which pixels are arranged in a matrix form are arranged adjacent to each other to form a single display area, and the plurality of display means In the display device having a plurality of image correction units provided correspondingly and performing signal correction on a plurality of individually input image signals, the plurality of image signals output from each of the plurality of image correction units Jitter suppression means for correcting the phase difference between them and suppressing jitter caused by the phase difference is provided, and the composition processing is performed on the plurality of image signals after the phase correction is performed by the jitter suppression means. .

  In the above configuration, the plurality of image correction units perform processing for correcting the luminance, color, and the like of the display image. The image correcting means is provided for each of the plurality of display means, and the image correcting means performs correction processing such as luminance and color on the image that each displays, thereby bonding the plurality of display means adjacent to each other. It is possible to make the joint of the end face portion inconspicuous. Further, the jitter suppression unit generates jitter (left and right display jitters) of the display image caused by the phase difference when the image signals output from the plurality of image correction units are combined with the image signal of one display image. (Blurring) is suppressed.

  According to the present invention, when a larger display area is obtained by laminating a plurality of small display devices, it is possible to make the joints of the bonded end surface portions inconspicuous and to provide an image provided for each display device. Jitter (display blur on the left and right) of the display image caused by the phase difference between the signals of the correction means can be suppressed with a very simple circuit configuration.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing a display device according to an embodiment of the present invention. The display device 10 according to the present embodiment is a large display device configured by bonding, for example, four small display devices 12 to 15 on a large substrate 11.

  In FIG. 1, the small display devices 12 to 15 have a plurality of scanning lines 16 to 19 and a plurality of data lines 20 and 21 orthogonal to the scanning lines 16 to 19, and the scanning lines 16 and 17 are perpendicular to each other. Are wired continuously in the direction (vertical direction in the figure), and are bonded so that the scanning lines 18 and 19 are continuously wired in the vertical direction, and the large display device is composed of the four small display devices 12 to 15 as a whole. 10 is constituted.

  Around the small display devices 12-15, two scanning line driving circuits 22-25 are provided along the left and right sides, and data line driving circuits 26, 27 are provided along the upper and lower sides. The scanning line driving circuits 22 to 25 and the data line driving circuits 26 and 27 are configured to operate in synchronization with each other. One end of each of the scanning lines 16 to 19 is connected to the output end of each row of the scanning line driving circuits 22 to 25. One end of each of the data lines 20 and 21 is connected to an output end of each column of the data line driving circuits 26 and 27.

  The scanning line driving circuits 22 to 25 are configured by, for example, shift registers, and sequentially output driving signals to the scanning lines 16 to 19 for selecting and driving the pixels of the small display devices 12 to 15 in units of rows. The data line driving circuits 26 and 27 supply data signals corresponding to the luminance information to the respective pixels in the row selected by the scanning line driving circuits 22 to 25 via the data lines 20 and 21. Thereby, each pixel in the small display devices 12 to 15 emits light and image display is performed, and one image is displayed on the entire four small display devices 12 to 15.

  FIG. 2 is a schematic configuration diagram illustrating a specific example of the small display devices 12 to 15. In this specific example, an active matrix organic EL display device using, for example, an organic EL element which is a self-luminous element as a pixel display element is shown as an example. The active matrix organic EL display device according to this example includes a pixel array unit 32 in which pixels 31 are arranged in a matrix as a main component.

  In FIG. 2, the pixel 31 has a field effect transistor, for example, a polysilicon TFT (Thin Film Transistor) or an amorphous silicon TFT 34 as an active element for driving the organic EL element 33 to emit light, on the substrate on which these TFTs 34 are formed. In this configuration, the organic EL element 33 is formed. The organic EL element 33 is formed with a plurality of first electrodes made of a transparent conductive film provided on a substrate, and a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are formed on at least one of the first electrodes. It has a structure in which an organic layer is formed by sequentially depositing and a second electrode made of a metal is formed on the organic layer, and light is emitted by applying a DC voltage between the first electrode and the second electrode. Light is emitted when electrons and holes recombine in the layer.

  In the pixel array unit 32, for example, three scanning lines 35-1 to 35-n corresponding to three colors of R (red), G (green), and B (blue) with respect to the arrangement of the pixels 31 in n rows and m columns. 36-1 to 36-n, 37-1 to 37-n are wired for each row, and data lines 38-1 to 38-m, 39-1 to 39-m, 40-1 to 40-m are provided. Wired for each column. The scanning lines 35-1 to 35 -n, 36-1 to 36 -n, and 37-1 to 37 -n correspond to the scanning lines 16 to 19 in FIG. 1, and the data lines 38-1 to 38 -m, 39. -1 to 39-m and 40-1 to 40-m correspond to the data lines 20 and 21 in FIG.

  When the active matrix organic EL display device having the above configuration is used as the small display devices 12 to 15, the data line driving circuits 26 and 27 in FIG. 1 are connected to the data lines 20 and 21 (data lines 38-1 to 38-m). , 39-1 to 39-m, 40-1 to 40-m), a current writing type or voltage writing type driving circuit configuration in which luminance information is written to each of the pixels 31 in the form of a current value or a voltage value. It becomes.

  For example, the display device 10 according to the present embodiment configured by the four small display devices 12 to 15 described above is equipped with a PLL function for adjusting the phase and frequency of the output signal with respect to the input signal. Jitter that suppresses jitter (left and right display blur) of a display image generated by a phase difference between signals in the image correction circuits as well as having an image correction circuit for correcting the luminance and color of the image for each of the small display devices 12 to 15. A suppression circuit is provided.

  FIG. 3 is a block diagram showing an example of the configuration of the image correction circuit and the jitter suppression circuit provided corresponding to the four small display devices 12 to 15. Normally, the image correction circuit is integrated into an IC, and is provided for each of the small display devices 12 to 15 as an image correction IC.

  As shown in FIG. 3, four image correction ICs 41 to 44 are provided corresponding to the four small display devices 12 to 15. When the display screens A to D shown in FIG. 12 are associated, the image correction IC 41 displays the display screen A, the image correction IC 42 displays the display screen B, the image correction IC 43 displays the display screen C, and the image correction IC 44 displays the display screen. Each D will be borne. The image correction ICs 41 to 44 receive an image data signal and a synchronization signal (vertical synchronization signal Vsync, horizontal synchronization signal Hsync).

  Each of the image correction ICs 41 to 44 adjusts the phase and frequency of the output signal with respect to the input signal, specifically, the synchronization signal input to the image correction ICs 41 to 44 and the synchronization output from the image correction ICs 41 to 44. A PLL circuit for always synchronizing with the signal is provided, and processing for correcting luminance, color, and the like is performed on the input image data signal.

  FIG. 4 is a block diagram showing a basic configuration of the PLL circuit. As apparent from FIG. 4, the PLL circuit includes a phase comparator 61, a low-pass filter (LPF) 62, a voltage controlled oscillator (VCO) 63, and a frequency divider 64.

  The phase comparator 61 compares the phase difference between the reference signal f1 and the comparison signal f2, and outputs the comparison result as a pulse signal corresponding to the phase difference between the reference signal f1 and the comparison signal f2. Here, when the phase of the comparison signal f2 is delayed compared to the reference signal f1, a pulse for increasing the frequency is output. Conversely, when the phase of the comparison signal f2 is advanced compared to the reference signal f1, the frequency is decreased. Output a pulse.

  The low-pass filter 62 is called a loop filter, and smoothes and outputs the output pulse of the phase comparator 61 to an analog signal close to direct current. The voltage value of the output voltage increases as the duty ratio of the output pulse of the phase comparator 61 increases. The output voltage of the low pass filter 62 is given to the voltage controlled oscillator 63 as its control voltage. The voltage controlled oscillator 63 oscillates at a frequency corresponding to the control voltage. In order for the output frequency of the voltage controlled oscillator 63 to be constant, the input of the voltage controlled oscillator 63 needs to be an analog signal and a DC signal with a constant voltage. For this purpose, a low-pass filter 62 is provided.

  The frequency divider 64 divides the output frequency of the voltage controlled oscillator 63 by 1 / N using a counter or the like. Here, when the output frequency fout of the voltage controlled oscillator 63 is Nf1, the frequency divider 64 obtains the comparison signal f2 (f1 = f2) by dividing the output frequency fout by 1 / N, and sends it to the phase comparator 61. give. In the PLL loop of this phase comparator 61 → low pass filter 62 → voltage controlled oscillator 63 → frequency divider 64, the phase of the two input signals (reference signal f1 and comparison signal f2) of the phase comparator 61 are the same. That is, the control is performed so that the frequencies of the two input signals are the same (f1 = f2).

  By the way, when the four image correction ICs 41 to 44 including the PLL circuit as described above are operated in parallel, for example, when the image correction IC 41 is used as a synchronization reference of the processing circuit in the subsequent stage, each PLL circuit included in the image correction ICs 42 to 44 is used. Are not configured to operate in synchronization with each other, the signals (synchronization signals, image data signals) output from the image correction ICs 42 to 44 other than the image correction IC 41 are the signals output from the image correction IC 41. On the other hand, a phase shift occurs.

  Specifically, as shown in FIGS. 5 to 7, the horizontal synchronization signal Hsync− output from the image correction ICs 42 to 44 with respect to the falling timing of the vertical synchronization signal Vsync-A output from the image correction IC 41. The phase of each falling timing of B to Hsync-D changes by ± 1 CLK of the clock signal serving as a reference for circuit operation every frame (1 V; 1 vertical period). Along with this phase shift, when the image data signals of the image correction ICs 41 to 44 are combined into one screen, ± 1 CLK jitter (display blur) is caused in the display screens B, C, and D that the image correction ICs 42 to 44 bear. (See FIG. 12). Here, 1CLK corresponds to one pixel at the time of horizontal scanning.

  In order to suppress the jitter of the display image, a jitter suppression circuit 50 is provided for the image correction ICs 41 to 44 as shown in FIG. The jitter suppression circuit 50 includes a delay circuit 51 and phase correction circuits 52 to 54. The jitter suppression circuit 50 can be configured inexpensively and easily using a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Allay), or the like.

  In the jitter suppression circuit 50, the delay circuit 51 delays the image data signal A output from the image correction IC 41 by 1 CLK (unit time) corresponding to one pixel. The image data signal A delayed by 1 CLK becomes a synchronization reference when the subsequent image data signal synthesis circuit 45 synthesizes the image. The phase correction circuits 52 to 54 detect respective phase differences between the vertical synchronization signal Vsync-A output from the image correction IC 41 and the horizontal synchronization signals Hsync-B to Hsync-D output from the image correction ICs 42 to 44, respectively. The image data signal A and each of the image data signals B to D are synchronized by correcting each phase of the image data signals B to D output from each of the phase correction circuits 52 to 54 according to the phase difference. I do.

  These synchronized image data signals A to D are supplied to the image data signal synthesis circuit 45. The image data signal synthesis circuit 45 synchronizes the image data signals A to D synchronized with the jitter suppression circuit 50 and the image data signal A based on the image synthesis control signal generated by the image synthesis control signal generation circuit 46. The composition process is performed as a reference. As a result, an image synthesis signal obtained by synthesizing four images into one image can be obtained.

  Each of the phase correction circuits 52 to 54 includes a phase correction signal generation circuit 61 and a phase delay circuit 62 as shown in FIG. The phase correction signal generation circuit 61 detects the detection timing of the falling timing of the vertical synchronization signal Vsync-A output from the image correction IC 41 and the horizontal synchronization signals Hsync-B to Hsync-D output from the image correction ICs 42 to 44. A phase correction signal for correcting the phase of the image data signals B to D output from the image correction ICs 42 to 44 is generated based on each detection pulse at the falling timing. The phase delay circuit 62 performs phase correction by delaying the image data signals B to D output from the image correction ICs 42 to 44 in accordance with the phase correction signal generated by the phase correction signal generation circuit 61.

  FIG. 9 is a block diagram illustrating an example of a specific configuration of the phase correction signal generation circuit 61. As is clear from FIG. 9, the phase correction signal generation circuit 61 according to this example includes a JK flip-flop 611, an AND circuit 612, an n-bit counter 613, an inverter 614, and n-bit comparators 615 to 617. Yes.

  The JK flip-flop 611 uses the detection pulse of the falling timing of the vertical synchronization signal Vsync-A output from the image correction IC 41 as a J input, and the horizontal synchronization signals Hsync-B to Hsync-D output from the image correction ICs 42 to 44. Each of the detection pulses at the falling timing is set as a K input, and a clock CLK-A synchronized with the vertical synchronization signal Vsync-A is used as a clock (CLK) input.

  The AND circuit 612 has the Q output of the JK flip-flop 611 as one input, and the output of the n-bit counter 613 inverted by the inverter 614 as the other input. The n-bit counter 613 uses the detection pulse of the falling timing of the vertical synchronization signal Vsync-A as a clear (CLR) input, the output of the AND circuit 612 as an enable (ENA) input, and the clock CLK-A as a clock input. The n-bit comparators 615 to 617 use the count value of the n-bit counter 613 as a comparison input.

  In the phase correction signal generation circuit 61 configured as described above, the JK flip-flop 611 receives the detection pulse of the fall timing of the vertical synchronization signal Vsync-A and each detection pulse of the fall timing of the horizontal synchronization signals Hsync-B to Hsync-D. Based on this, a high-level phase difference detection period signal is output in synchronization with the rising timing of the clock CLK-A. The n-bit counter 613 counts the Hi level period of the phase difference detection period signal output from the JK flip-flop 611 in synchronization with the clock CLK-A every frame. The count value A−CLK of the n-bit counter 613 has a difference of ± 1 CLK at the maximum, as is apparent from the above description.

  Here, for example, when the count value A-CLK from the falling timing of the vertical synchronizing signal Vsync-A to the falling timing of the horizontal synchronizing signals Hsync-B to Hsync-D is based on X (see FIG. 5), in addition to a comparator that detects X count values A-CLK, a comparator that detects X + 1 count values A-CLK and a comparison that detects X-1 count values A-CLK. A vessel is required. The n-bit comparators 615 to 617 distinguish (select) the count value A-CLK of the n-bit counter 613. That is, since the count value A-CLK of the n-bit counter 613 has a maximum difference of ± 1 CLK, any one of the comparators 615 to 617 is always active every frame.

  Specifically, the n-bit comparator 615 outputs the Hi level phase correction signal (1) when the count value A-CLK is the decode value: X + 1. This phase correction signal (1) indicates that it is delayed by 1 CLK with respect to the reference value X. The n-bit comparator 616 outputs the Hi level phase correction signal (2) when the count value A-CLK is the decode value: X. This phase correction signal (2) indicates that the phase is not shifted from the reference value X. The n-bit comparator 617 outputs the Hi level phase correction signal (3) when the count value A-CLK is the decode value: X-1. This phase correction signal (3) indicates that the signal is advanced by 1 CLK with respect to the reference value X. FIG. 10 shows a timing relationship between the vertical synchronization signal Vsync-A and the phase correction signals (1) to (3).

  FIG. 11 is a block diagram showing an example of a specific configuration of the phase delay circuit 62. As is apparent from FIG. 11, the phase correction circuit 62 according to this example includes an AND circuit 621, a D flip-flop 622, an AND circuit 623, D flip-flops 624 and 625, an AND circuit 626, and an OR circuit 627. ing.

  The AND circuit 621 uses the image data signals B to D output from the image correction ICs 42 to 44 as one input and the phase correction signal (1) generated by the phase correction signal generation circuit 61 as the other input. The D flip-flop 622 uses the image data signals B to D output from the image correction ICs 42 to 44 as data (D) inputs and the clock CLK-A as a clock input. The AND circuit 623 has the Q output of the D flip-flop 622 as one input and the phase correction signal (2) generated by the phase correction signal generation circuit 61 as the other input.

  The D flip-flop 624 uses the image data signals B to D output from the image correction ICs 42 to 44 as data inputs and the clock CLK-A as a clock input. The D flip-flop 625 uses the Q output of the D flip-flop 624 as a data input and the clock CLK-A as a clock input. The AND circuit 626 has the Q output of the D flip-flop 625 as one input and the phase correction signal (3) generated by the phase correction signal generation circuit 61 as the other input. The OR circuit 627 has three outputs from the AND circuits 621, 623, and 626.

  In the phase delay circuit 62 configured as described above, a delay amount set in advance by the phase correction signals (1) to (3) output from the phase correction signal generation circuit 61 of FIG. (2) (1 CLK advanced / 1 CLK delayed) is reflected in the image data signals B to D. That is, the AND circuit 621, 623, 626 takes the logical product of the phase correction signals (1) to (3) and the image data signals B to D shown in FIG. Since only the output of one AND circuit is active (in this example, the Hi level), an image data signal whose phase has been corrected can be obtained.

  By applying the phase correction processing by the phase correction circuits 52 to 54 described above to the image data signals B to D output from the image correction ICs 42 to 44, the phases of all the image data signals A to D are matched. be able to.

  As described above, in order to adjust the phase and frequency of the output signal with respect to the input signal in the large display device 10 configured to obtain a larger display area by bonding the four small display devices 12 to 15, for example. Image correction ICs 41 to 44 that are equipped with a PLL function and correct the luminance and color of the display image are provided for each of the display devices 12 to 15. By performing a correction process such as the above, it is possible to make the joints of the bonded end face portions inconspicuous.

  Further, by providing a jitter suppression circuit 50 that corrects the phase difference between the image data signals output from the image correction ICs 41 to 44 and suppresses jitter caused by the phase difference, the output from the image correction ICs 41 to 44 is performed. When the generated image data signal is combined with the image data signal of one display image, the jitter (display blur on the left and right) of the display image caused by the phase difference is complicated. Without using a circuit, it can be automatically and instantaneously (real-time) suppressed with a very simple logic circuit configuration.

  In the above embodiment, an organic EL display device using an organic EL element as a display element of a pixel is used as a small display device and applied to a display device in which a plurality of these small display devices are bonded to a large substrate. Although the case has been described as an example, the present invention is not limited to this. The present invention is not limited to a self-luminous element other than an organic EL element or a self-luminous element, and a liquid crystal cell is used as a pixel display element. The present invention can be applied to all display devices in which a plurality of small display devices are used.

  The display device according to the present invention is particularly used as a large television having a diagonal size exceeding 30 inches to 60 inches.

It is a schematic block diagram which shows the display apparatus which concerns on one Embodiment of this invention. It is a schematic block diagram which shows the specific example of the pixel array part of a small display device. It is a block diagram which shows an example of a structure of an image correction IC and a jitter suppression circuit. It is a block diagram which shows the basic composition of the PLL circuit contained in an image correction IC. 6 is a timing chart (part 1) showing a phase relationship between horizontal synchronization signals Hsync-B to Hsync-D with respect to a vertical synchronization signal Vsync-A. FIG. 10 is a timing chart (part 2) illustrating a phase relationship between horizontal synchronization signals Hsync-B to Hsync-D with respect to a vertical synchronization signal Vsync-A. 12 is a timing chart (part 3) illustrating a phase relationship between the horizontal synchronization signals Hsync-B to Hsync-D with respect to the vertical synchronization signal Vsync-A. It is a block diagram which shows an example of a structure of the phase correction circuit in a jitter suppression circuit. It is a block diagram which shows an example of a specific structure of the phase correction signal generation circuit in a phase correction circuit. 6 is a timing chart for explaining the operation of the phase correction signal generation circuit. It is a block diagram which shows an example of the specific structure of the phase delay circuit in a phase correction circuit. It is explanatory drawing of the subject of a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Large display apparatus, 11 ... Large substrate, 12-15 ... Small display apparatus, 16-19 ... Scan line, 20, 21 ... Data line, 22-25 ... Scan line drive circuit, 26, 27 ... Data line drive circuit , 31 ... pixel, 32 ... pixel array section, 33 ... organic EL element, 34 ... TFT (thin film transistor), 41 to 44 ... image correction IC (circuit), 45 ... image data signal synthesis circuit, 46 ... image synthesis control signal generation Circuit: 50 ... Jitter suppression circuit, 51 ... Delay circuit, 52-54 ... Phase correction circuit, 61 ... Phase correction signal generation circuit, 62 ... Phase delay circuit

Claims (6)

A display device in which a plurality of display means in which pixels are arranged in a matrix is arranged adjacent to each other to form a single display area,
A plurality of image correction means provided corresponding to the plurality of display means, and performing signal correction on a plurality of individually input image signals;
A jitter suppression unit that corrects a phase difference between the plurality of image signals output from each of the plurality of image correction units and suppresses jitter caused by the phase difference;
And synthesis processing as the image synthesizing signal of one image to be displayed a plurality of image signals phase-corrected by the plurality of display means by said jitter suppression means, to supply the image synthesizing signal to the plurality of display devices A display device comprising a combining means. Each of the plurality of image correction units includes a PLL circuit that synchronizes a synchronization signal input to the plurality of image correction units and a synchronization signal output from the plurality of image correction units. the display device according to claim 1,. The jitter suppression unit detects a phase difference between a delay unit that delays one image signal of the plurality of image signals by a predetermined time and a remaining image signal of the plurality of image signals with respect to the one image signal. The display device according to claim 1 , further comprising: a phase correction unit that corrects the phase difference in units of the predetermined time. A plurality of display means in which pixels are arranged in a matrix form are arranged adjacent to each other to form one display area, and a plurality of display means provided corresponding to the plurality of display means and individually inputted A driving method of a display device having a plurality of image correction means for performing signal correction on the image signal of
A first step of correcting a phase difference between the plurality of image signals output from each of the plurality of image correction units to suppress jitter caused by the phase difference;
Synthesizing processing the plurality of image signal phase-corrected by the first step as the image synthesizing signal of one image to be displayed by said plurality of display means, for supplying the image synthesizing signal to the plurality of display devices And a second step of driving the display device. Each of the plurality of image correction units includes a PLL circuit that synchronizes a synchronization signal input to the plurality of image correction units and a synchronization signal output from the plurality of image correction units. the driving method of a display device according to claim 4,. In the second step, one image signal of the plurality of image signals is delayed by a predetermined time, and a phase difference between the remaining image signals of the plurality of image signals with respect to the one image signal is detected, 5. The display device driving method according to claim 4 , wherein the phase difference is corrected in units of the predetermined time.

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