JP2001007220A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a gate electrode, a resistor film and the like exhibiting no variations in resistance. SOLUTION: A first RTA process is performed after phosphorus ions are implanted into part of a polysilicon film. After boron ions are implanted into another part of the polysilicon film, the resulting polysilicon film is patterned to form a gate electrode 8 and a resistor film 13. After a TEOS film is deposited, the TEOS film is patterned to form a silicidizing mask 10a having an opening for a silicidizing region Rsi. Then, annealing is performed to activate boron in an oxygen-containing atmosphere, thereby forming an oxide film 31 on the gate electrode 8 in the region Rsi and a highly doped source/drain region 6. The film 31 suppresses the outward diffusion of impurities, and hence suppresses impurity ions breaking through the electrode 8 when ion implantation for promoting silicidization is subsequently performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a polysilicon member formed by patterning a polysilicon film.

[0002]

2. Description of the Related Art Conventionally, a device having a polysilicon member which needs to be silicided, such as a gate electrode of a MOS transistor or an electrode of a capacitor, and a high withstand voltage transistor having a resistive film of a resistive element and a dielectric breakdown protection function. There is a semiconductor device having a polysilicon member that does not need to be silicided as in the case of the gate electrode described above.

Here, a description will be given of a conventional manufacturing process of a semiconductor device having a MOS transistor having a gate electrode requiring silicidation and a high breakdown voltage MOS transistor not requiring silicidation as a conventional semiconductor device.

First, a non-doped polysilicon film is formed on a substrate, and portions of the non-doped polysilicon film are doped with phosphorus, which is an n-type impurity, and boron, which is a p-type impurity, by ion implantation in separate implantation regions. I do.
This doping may be performed after forming the gate electrode of each transistor or before forming the gate electrode. In particular, when it is desired to reduce the resistance by doping with a high-concentration impurity, it may be performed both before and after patterning the polysilicon film.

Next, annealing (RTA) for activating the implanted impurities is performed. Then, the entire surface of the substrate is subjected to plasma processing to form a TEO for forming a selective etching mask.
An S film is deposited and patterned by wet etching or the like to form a selective etching mask covering the non-silicided region and opening the silicided region.

Next, ion implantation of impurities for promoting silicidation (for pre-amorphization) is performed from above the selective etching mask into the gate electrode which is a polysilicon member in the silicidation region. In the case of the salicide process, ion implantation of impurities for promoting silicidation is also performed in the source / drain regions.

Then, a high melting point metal film is deposited on the substrate,
The silicide film is formed by reacting the metal constituting the high melting point metal film with the polysilicon constituting the gate electrode (in the salicide process, the polysilicon constituting the gate electrode and the silicon constituting the source / drain regions). . At this time, in the non-silicided region, a silicide film is not formed because a selective etching mask is interposed between the high melting point metal film and the gate electrode or the source / drain region. Further, after the unreacted portion of the high melting point metal film is removed by etching, heat treatment for phase transition of the silicide film is performed.

By the above steps, a MOS transistor having a polysilicon electrode whose upper part is silicided,
A semiconductor device is formed in which a high-breakdown-voltage transistor having a gate electrode that is not silicided is provided over a common substrate.

Incidentally, the polysilicon resistor film of the resistance element is often formed on the element isolation insulating film in the non-silicidized region. In that case, in the above configuration, the selective etching mask covers the polysilicon resistor film.

[0010]

However, the semiconductor device formed by the conventional manufacturing process has the following disadvantages.

First, there is a problem that the resistance value of the polysilicon film, for example, the gate resistance of the gate electrode in a MOS transistor and the resistance value of a resistor in a resistance element may vary. This is because the impurity doped into the gate electrode diffuses (out diffusion) into the atmosphere during the heat treatment for activation. As a result, the impurity concentration in the doped polysilicon film decreases, so that the resistance value becomes larger than the set value.

Second, especially in a MOS transistor formed in a silicidation region, an impurity implanted for promoting silicidation penetrates a gate electrode and reaches the inside of a substrate, so that the threshold voltage of the MOS transistor is reduced. There was a problem of dispersion.

Thirdly, there is a problem that the resistance value varies due to the formation of holes after impurities in the polysilicon member escape during activation annealing. further,
When the upper portion of the polysilicon member is silicided, vacancies are generated in the silicide film, and the resistance value of the silicide film cannot be sufficiently reduced.

A first object of the present invention is to provide a semiconductor device in which a polysilicon member is disposed in each of a silicidized region and a non-silicidized region, and in which a variation in resistance of the polysilicon member and a threshold voltage of a MOS transistor are provided. It is an object of the present invention to provide a method of manufacturing a semiconductor device having a small variation in the thickness.

A second object of the present invention is to provide a semiconductor device having a polysilicon member, in which a means for suppressing the generation of vacancies in the polysilicon member due to outdiffusion of impurities is provided, thereby reducing the resistance value of the silicide film. Is to suppress the increase in

[0016]

According to a first method of manufacturing a semiconductor device of the present invention, there is provided a silicidation region in which a MOS transistor in which the upper portions of a gate electrode and a high-concentration source / drain region are silicided is arranged; A method of manufacturing a semiconductor device having a non-silicided region in which an element having a polysilicon member whose upper portion is not silicided is disposed, wherein a gate insulating film and a polysilicon film are formed on a semiconductor substrate ( a), a step (b) of implanting n-type impurity ions for reducing the resistance value into a part of the polysilicon film using a mask having an opening in the n-type impurity implantation region, and activating the n-type impurity. (C) of performing a first heat treatment for performing the first heat treatment, and after the step (c), using a mask having an opening in the p-type impurity implantation region, forming the other portions of the polysilicon film. The p-type impurity ions for resistance reduction step of injecting the (d), after the step (d) to,
Patterning the polysilicon film to form a gate electrode of the MOS transistor in the silicided region and forming the polysilicon member in the non-silicided region; A step (f) of implanting impurity ions for forming a drain region, a step (g) of forming an insulating film on the substrate after the step (f), and a selective etching mask on the insulating film. (H) and a step of forming a silicide mask that covers the non-silicided region and is opened above the silicided region by patterning the insulating film using the selective etching mask ( i) and, after the step (i), a step (j) of performing a second heat treatment for activating the p-type impurity.
And after the step (j), the M
A step (k) of implanting impurity ions for promoting silicidation into the gate electrode and the high-concentration source / drain regions of the OS transistor; and after the step (k), the gate electrode and the high-concentration MOS transistor in the silicidation region (L) converting the upper portion of the source / drain region into a silicide.

According to this method, the high-concentration region of the n-type impurity is eliminated by the first heat treatment, and at the time of the second heat treatment, the impurity doped in the polysilicon member in the non-silicidized region is removed. Out diffusion can be prevented. Therefore, it is possible to reliably prevent the resistance value of the polysilicon member (for example, the resistor film of the resistance element) disposed in the non-silicidation region from varying. In addition, since the number of steps does not increase, an increase in manufacturing cost can be avoided.

In the first method of manufacturing a semiconductor device, the first heat treatment is performed in an atmosphere containing oxygen, so that an oxide film is formed on the region of the polysilicon film into which the n-type impurity has been implanted. As a result, out diffusion of the n-type impurity during the heat treatment is suppressed. That is, it is possible to suppress the variation in the resistance value of the polysilicon film due to the out-diffusion of the n-type impurity, and the variation in the resistance value of the polysilicon film due to the holes left as a result of the out-diffusion of the n-type impurity.

The partial pressure of oxygen in the atmosphere containing oxygen in the first heat treatment is preferably 5 to 30%.

In the first method of manufacturing a semiconductor device, the second heat treatment is performed in an atmosphere containing oxygen, so that the gate electrode and the high-concentration source / drain regions exposed in the silicidation region are exposed. Since an oxide film is formed on the substrate, out diffusion of n-type impurities in these regions is suppressed. That is, it is possible to suppress variations in the resistance values of these regions. In addition, due to the presence of the oxide film, variation in the threshold voltage of the MOS transistor caused by impurity ions for promoting silicidation in the subsequent step (k) penetrating through the gate electrode in the silicidation region and reaching the semiconductor substrate is reduced. Can be suppressed.

The partial pressure of oxygen in the atmosphere containing oxygen in the second heat treatment is preferably 5 to 30%.

In the first method of manufacturing a semiconductor device, in the step (h), the selective etching mask is formed of a resist film, and after the step (i), the step (j) is performed. Before, by further comprising a step of removing the resist film by ashing with oxygen plasma, an oxide film can be formed on the gate electrode and the high-concentration source / drain regions while also removing the resist film. Variations in the resistance values of the gate electrode and the high-concentration source / drain regions as described above can be suppressed, and variations in the threshold voltage of the MOS transistor in the silicidation region can be suppressed.

In the first method for manufacturing a semiconductor device, in the step (h), the selective etching mask is formed of a resist film, and after the step (i), the selective etching mask is formed in the step (j). Before removing the resist film with an aqueous solution of sulfuric acid and hydrogen peroxide, the method further comprises the step of plasma oxidizing the surface of the gate electrode and the high-concentration source / drain region in the silicidation region. And an oxide film can be formed on the high-concentration source / drain regions. Therefore, it is possible to suppress the variation in the resistance values of the gate electrode and the high-concentration source / drain regions as described above and to reduce the MOS transistor in the silicidation region. Variations in the threshold voltage can be suppressed.

In the first method of manufacturing a semiconductor device, in the step (b), at least one of a resistor film of a resistance element and a gate electrode of a high breakdown voltage transistor may be used as a polysilicon member of the element in the non-silicided region. Either can be formed.

According to a second method of manufacturing a semiconductor device of the present invention,
The method includes a step (a) of ion-implanting an impurity for reducing a resistance value into a polysilicon layer on a semiconductor substrate, and a step (b) of heat-treating the substrate in an atmosphere containing oxygen.

According to this method, an oxide film is formed on the polysilicon layer, so that out-diffusion of impurities during the heat treatment is suppressed. That is, it is possible to suppress the variation in the resistance value of the polysilicon layer due to the out-diffusion of the impurity and the variation in the resistance value of the polysilicon layer due to the holes left as a result of the out-diffusion of the impurity.

In the second method of manufacturing a semiconductor device, when the polysilicon layer is a gate electrode of a MOS transistor, after the step (b), an impurity for promoting silicidation is introduced into the polysilicon layer. In the case where the method further comprises a step (c) of introducing and a step (d) of silicidizing the upper portion of the polysilicon layer after the step (c), a silicidation step is performed after that in addition to the above-mentioned effects. Can be suppressed from penetrating the gate electrode during the pre-amorphization ion implantation. That is, variation in the threshold voltage of the MOS transistor can be suppressed.

In the second method for fabricating a semiconductor device, when the polysilicon layer is a resistor of a resistance element, the resistance value of the resistor film is accurately allowed by suppressing out diffusion of impurities. It can be within the range.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
FIG. 4C is a cross-sectional view illustrating a step of manufacturing the semiconductor device of the present embodiment.

Before the process shown in FIG. 1A, the processing is performed according to the following procedure. First, a trench type element isolation insulating film 2 surrounding each transistor formation region is formed on a Si substrate 1. This element isolation insulating film 2 is formed, for example, by the following steps. A protective oxide film on the substrate,
After the formation of the silicon nitride film, the trench formation region of the protective oxide film and the silicon nitride film is selectively removed. Then, the trench is formed by etching the Si substrate 1 using the remaining portion of the silicon nitride film as an etching mask. After that, after depositing a silicon oxide film on the substrate, the silicon oxide film is buried in the trench by performing CMP until the silicon nitride film is exposed, thereby forming the isolation insulating film 2. Thus, the Si substrate 1 is largely divided into the silicided region Rsi and the non-silicided region Rnsi by the element isolation insulating film 2. In the non-silicided region Rnsi, a high-breakdown-voltage nMOSFET forming region Rnn for forming a high-breakdown-voltage n-channel MOS transistor arranged in the input circuit is provided. The silicidation region Rsi is an n-channel type MO.
It is further divided into an nMOSFET formation region Rsn for forming an S transistor and a pMOSFET formation region Rsp for forming a p-channel MOS transistor. Thereafter, impurity ions are implanted into the regions Rnn, Rsn, and Rsp to form well regions 3a, 3b, and 3c corresponding to the transistors formed in the regions. That is, the p-type well region 3 is formed in the high breakdown voltage nMOSFET formation region Rnn.
a, a p-type well region 3b is formed in the nMOSFET formation region Rsn, and an n-type well region 3c is formed in the pMOSFET formation region Rsp.

In general, the high-breakdown-voltage MOS transistor arranged in the input circuit is often only an n-channel MOS transistor.
In some cases, both a transistor and a p-channel MOS transistor are provided.

Next, gate oxide films 7a and 7b made of a silicon oxide film (thermal oxide film) and a polysilicon film are sequentially formed in a region of the Si substrate 1 surrounded by the isolation insulating film 2. In this state, the polysilicon is not doped. The gate oxide film 7a of the high breakdown voltage transistor formed in the non-silicided region Rnsi is generally thicker than the gate oxide film 7b of the normal MOSFET formed in the silicided region Rsi. For example, normal M
The thickness of the gate oxide film 7a of the OS transistor is about 5 nm, while the thickness of the gate oxide film 7b of the high breakdown voltage MOS transistor is about 10 nm.

Next, of the polysilicon film, pMOSFE
With the portion located in the T formation region Rsp covered with a resist mask, phosphorus as an n-type impurity is doped into the polysilicon film by ion implantation. At this time, the high breakdown voltage nMOSFET formation region R in the non-silicidation region Rnsi
nn is also doped by phosphorus ion implantation. After that, annealing for activating phosphorus (the first R
TA).

Next, of the polysilicon film, nMOSFE
T forming region Rsn and high withstand voltage nMOSFET forming region Rnn
Is covered with a resist mask, boron as a p-type impurity is doped into the polysilicon film by ion implantation. Here, annealing (second RTA) for activating boron is not performed.

Thereafter, the gate electrodes 8 of the n-channel and p-channel MOS transistors and the high-breakdown-voltage MOS transistor are formed by patterning the polysilicon film. Thereafter, ion implantation of impurities for forming the LDD region 5, formation of a side wall 9 made of a silicon oxide film, and ion implantation of impurities for forming the high-concentration source / drain regions 6 are performed.

Then, as shown in FIG. 1A, a TEOS film 10 is deposited on the entire surface of the substrate by plasma CVD. Thereby, the entire non-silicided region Rnsi and the silicided region Rsi are covered with the TEOS film 10.

Thereafter, annealing (R) for activating boron in the gate electrode of the p-channel type MOS transistor is performed.
TA treatment) at 750 ° C. for 5 seconds.

Next, in a step shown in FIG. 1B, a resist mask 20 covering the non-silicidation region Rnsi is formed on the substrate by a photolithography step. Then, the TEOS film 10 is wet-etched using the resist mask 20 as an etching mask, so that the non-silicided region Rnsi of the TEOS film 10 is formed.
This is used as the TEOS mask 10a except for the portion located at the position, and the other portion is removed. As a result, the silicidation region Rsi
The surfaces of the MOSFET gate electrode 8 and the high-concentration source / drain regions 6 are exposed. Note that hydrofluoric acid is used for the wet etching solution.

Next, in order to easily silicify the surface portions of the gate electrode 8 and the high-concentration source / drain regions 6, the surface portions of these regions are pre-amorphized. That is, with the resist mask 20 removed,
Arsenic ions (As ⁺ ) are applied to the gate electrode 8 and the high-concentration source / drain region 6 from above the TEOS mask 10a.
The dose amount is about 1 × 10 ¹⁴ cm ¹² and the implantation energy is about 2
The injection is performed under the condition of 0 keV. Thereby, the gate electrode 8
In addition, a region near the surface of the high-concentration source / drain region 6 is made amorphous, so that silicide is easily formed.

Next, in the step shown in FIG. 1C, a metal film made of titanium (or cobalt film) having a thickness of 50 nm is deposited on the entire surface of the substrate. At this time, a sputtering method using titanium (or cobalt) as a target is used.

Next, heat treatment is performed at 650 ° C. for 30 minutes to convert titanium (or cobalt), polysilicon forming the gate electrode 8 and single crystal silicon forming the high concentration source / drain region 6. By reacting, the gate electrode 8 and the high concentration source / drain region 6
Are silicided to form titanium silicide films 11a and 11b.

Thereafter, when the TEOS mask 10a is removed, the non-silicidized region Rnsi has a high breakdown voltage nMOSFE.
T is a normal nMOSFET in the silicidation region Rsi.
And a semiconductor device in which pMOSFETs are arranged.

According to the present embodiment, an annealing step (second RTA) for activating impurities in a portion of a gate polysilicon film which is to be a gate electrode of a normal p-channel MOS transistor, and the TEOS film 10 Is changed from the conventional process. In other words, annealing (first RTA) for phosphorus activation in a portion of the polysilicon film for a gate which is to be a gate electrode of a normal nMOSFET and a high withstand voltage nMOSFET is performed by TE
This is performed before the OS film 10 is deposited. That is, due to the implantation of the n-type impurity ions (phosphorus ions), a portion of the polysilicon film including the n-type impurity at an extremely high concentration exists in the surface portion of the nMOSFET formation region Rnn. In this state, if the polysilicon film is etched to form a gate electrode or the like, a portion containing an n-type impurity at an extremely high concentration promotes an etching action more than other portions, and anisotropy is impaired. There is a possibility that a side-etched portion is formed at the upper end of the electrode or the like. On the other hand, in the present embodiment, the first RTA causes the n-type impurity to diffuse into the polysilicon film from a portion containing the n-type impurity (phosphorus) at a very high concentration near the surface of the polysilicon film 12. I do. Therefore, since the concentration of the n-type impurity in the surface portion of the polysilicon film is reduced, when the polysilicon film is later etched to form a gate electrode or the like,
Side etching at the upper end of the gate electrode or the like can be prevented.

On the other hand, immediately after boron, which is a p-type impurity, is implanted into the polysilicon film, the TEOS film 10 covers the entire surface of the substrate without performing annealing (second RTA) for impurity diffusion. Annealing is performed. Therefore, a normal p-channel type M caused by out diffusion of impurities in the second RTA is used.
Variation in gate resistance of the OS transistor can be suppressed. Therefore, a semiconductor device having stable electric characteristics can be obtained.

(Second Embodiment) FIGS. 2A to 2C,
FIGS. 3A and 3B and FIGS. 4A to 4C are cross-sectional views illustrating the steps of manufacturing the semiconductor device according to the second embodiment of the present invention.

First, processing is performed according to the following procedure before reaching the step shown in FIG. First, a trench type element isolation insulating film 2 surrounding each transistor formation region is formed on a Si substrate 1. This element isolation insulating film 2
Are formed by the same procedure as that described in the first embodiment. Then, the Si substrate 1 is largely divided into a non-silicided region Rnsi and a silicided region Rsi by the element isolation insulating film 2. Here, in the present embodiment, the non-silicided region Rnsi is a high-breakdown-voltage nMOSFET forming region Rnn in which a high-breakdown-voltage n-channel MOS transistor provided in the input circuit is provided.
It is divided into a high-breakdown-voltage pMOSFET formation region Rnp in which a high-breakdown-voltage p-channel MOS transistor is provided, and a resistance-element formation region Rnr in which a resistance element is provided in a region above the isolation insulating film 2. Further, the silicidation region Rsi is
nM for forming an n-channel MOS transistor
It is further divided into an OSFET formation region Rsn and a pMOSFET formation region Rsp for forming a p-channel MOS transistor. Thereafter, each region Rsn, Rsp, Rn
n, Rnp are implanted with impurity ions to form well regions 3x, 3y, 3z,
3w is formed. That is, the nMOSFET formation region R
In the sn and high breakdown voltage nMOSFET formation region Rnn, p-type well regions 3x and 3z are formed, and in the pMOSFET formation region Rsp and the high breakdown voltage pMOSFET formation region Rnp, n-type well regions 3y and 3w are formed, respectively.

Next, gate oxide films 7a and 7b made of a silicon oxide film (thermal oxide film) and a polysilicon film 12 are sequentially formed in a region of the Si substrate 1 surrounded by the isolation insulating film 2. The gate oxide film 7a of the high breakdown voltage transistor formed in the non-silicided region Rnsi is generally thicker than the gate oxide film 7b of the normal MOSFET formed in the silicided region Rsi. For example, normal MOS
The thickness of the gate oxide film 7a of the transistor is about 5 nm, while the thickness of the gate oxide film 7b of the high breakdown voltage MOS transistor is about 10 nm.

Next, on the polysilicon film 12, the pMOSFET formation region Rsp of the polysilicon film and the high breakdown voltage p
A resist mask 21 is formed to cover the portions located in the MOSFET formation region Rnp and the resistance element formation region Rnr and to open above the portions located in the nMOSFET formation region Rsn and the high breakdown voltage nMOSFET formation region Rnn. Then, using the resist mask 21 as an implantation mask, phosphorus ions (P
⁺ ) Injection. That is, in the polysilicon film 12, the nMOSFET formation region Rsn and the high withstand voltage nMOSF
A region included in the ET formation region Rnn is doped with phosphorus.

Then, with the resist mask 21 removed, annealing for activation (first RTA) is performed. At this time, the RTA process is performed in a temperature range of 750 ° C. to 850 ° C. in an atmosphere containing oxygen (O ₂ ) and nitrogen (N ₂ ). The oxygen partial pressure is, for example, 5 to 20%. Specifically, for example, the partial pressure of oxygen can be adjusted by the flow ratio of nitrogen and oxygen. At this time, the polysilicon film 1
2 has a thickness of 3 to 4 nm on the exposed portion.
An ultra-thin oxide film 30 (silicon oxide film) is formed.
The formation of this oxide film 30 allows the first R
Out diffusion of phosphorus doped in the polysilicon film 12 during TA is suppressed.

Also, due to the implantation of n-type impurity ions (phosphorus ions), a portion containing an extremely high concentration of n-type impurities is present on the surface of each of the regions Rsn and Rnn. In this state, if the polysilicon film is etched to form a gate electrode or the like, a portion containing an n-type impurity at an extremely high concentration promotes an etching action more than other portions, and anisotropy is impaired. There is a possibility that a side-etched portion is formed at the upper end of the electrode or the like. On the other hand, in the present embodiment, each region Rsn, R
At nn, the n-type impurity diffuses into the polysilicon film 12 from a portion containing the n-type impurity (phosphorus) at a very high concentration near the surface of the polysilicon film 12. Therefore, since the concentration of the n-type impurity in the surface portion of the polysilicon film 12 is reduced, it is possible to prevent side etching at the upper end portion of the gate electrode and the like when the polysilicon film is etched later to form a gate electrode and the like. Can be.

Next, in the step shown in FIG. 2B, the n
A resist mask 22 is formed to cover the portions located in the MOSFET formation region Rsn and the high breakdown voltage nMOSFET formation region Rnn, and to open above the portions located in the pMOSFET formation region Rsp, the high breakdown voltage pMOSFET formation region Rnp, and the resistance element formation region Rnr. . Then, the resist mask 22
Using p as an implantation mask, p
Implantation of boron fluoride ion (BF ₂ ⁺ ), which is a type impurity ion. That is, p of the polysilicon film 12
The regions included in the MOSFET formation region Rsp, the high breakdown voltage pMOSFET formation region Rnp, and the resistance element formation region Rnr are doped with boron. Here, annealing (second RTA) for activating boron is not performed.

The portion of the polysilicon film 12 located in the resistance element formation region Rnr is replaced with n-type impurities instead of p-type impurities.
Ion implantation of type impurities may be performed. In that case, in the state shown in FIG. 2A, a portion of the resist mask 21 located in the resistance element formation region Rnr is opened. Then, after the resist mask 21 is removed, an oxide film is formed on the polysilicon film 12 by the first RTA in an atmosphere containing oxygen, so that the out-diffusion of the n-type impurity is suppressed, and the resistance element is removed. Can be accurately set within an allowable range.

Next, in the step shown in FIG. 2C, after removing the resist mask 22, a mask (not shown) for forming a gate electrode and a resistor film is formed, and this forming mask is used as an etching mask. The gate electrode 8 of each MOSFET and the resistive film 13 of the resistive element are formed by patterning the polysilicon film by using the above. Thereafter, after removing the formation mask, ion implantation of impurities for forming the LDD region 5, formation of a sidewall 9 made of a silicon oxide film on the side surface of the gate electrode 8, and removal of the high-concentration source / drain region 6 are performed. Ion implantation of impurities for formation is performed. At this time, in the normal process, the oxide film 3 formed on the polysilicon film 12 is
0 is removed by, for example, etch back for forming a sidewall.

Next, in the step shown in FIG. 3A, TEOS 10 is deposited on the entire surface of the substrate by plasma CVD. In the first embodiment, annealing is performed immediately after this, but in this embodiment, annealing is not performed.

Next, in the step shown in FIG.
A resist mask 23 is formed on the EOS film 10 so as to cover the non-silicided region Rnsi and open the silicided region Rsi. Then, wet etching is performed using the resist mask 23 as an etching mask to remove a portion of the TEOS film 10 included in the silicidation region Rsi. As a result, a TEOS mask 10a having an opening in the silicidation region Rsi is formed, and the source / drain region 6 and the surface of the gate electrode of each MOS transistor in the silicide formation region Rsi are exposed.

Next, in the step shown in FIG. 4A, the resist mask 23 is made of sulfuric acid / hydrogen peroxide (sulfuric acid + hydrogen peroxide + water).
750 ° C. after removal by washing with
The second RTA process is performed in a temperature range of from about 850 ° C. to an atmosphere containing oxygen (O ₂ ) and nitrogen (N ₂ ). The oxygen partial pressure (O ₂ / (O ₂ + N ₂ )) is, for example, 5 to 20%,
Specifically, nitrogen and oxygen are flowed at a flow ratio of N ₂ : O ₂ = 5: 1. At this time, an oxide film 31 is formed on a portion not covered by the TEOS mask 10a, that is, on the gate electrode 8 and the source / drain region 6 of the MOS transistor in the silicide formation region Rsi. By this oxide film 31, n during the second RTA process is reduced.
N-type impurity (phosphorus) and p-type impurity (boron) in gate electrode 8 of channel-type and p-channel-type MOS transistors
Out diffusion is suppressed, and penetration of As ⁺ is also suppressed at the time of arsenic ion (As ⁺ ) implantation during the subsequent preamorphous formation.

Next, in the step shown in FIG. 4B, the gate electrode 8 and the high-concentration source in the silicidation region Rsi are formed in order to facilitate silicidation of the surface of the gate electrode 8 and the high-concentration source / drain region 6. Perform ion implantation for pre-amorphizing the surface of the drain region 6. That, TEOS mask 10a is used as an implantation mask, an As ⁺ ion to the gate electrode 8 and the heavily doped source and drain regions 6 and a dose of about 1 × 10 ¹⁴
The implantation is performed under the conditions of cm ⁻² and implantation energy of about 20 keV. As a result, the regions near the surfaces of the gate electrode 8 and the high-concentration source / drain regions 6 are made amorphous, so that silicide is easily formed. Since the dose in the ion implantation at this time is extremely smaller than the dose in the ion implantation into the polysilicon film and the source / drain regions, the conductivity due to impurities implanted into the polysilicon film and the source / drain regions is reduced. Will not be compromised.

The ion species implanted at this time is silicon
It has a function to make the area to be made amorphous
As long as it is enough,⁺ Not only for example
Ge ⁺ Ions using ions of relatively large atoms such as
An injection may be performed.

Next, in the step shown in FIG. 4C, a metal film made of titanium (or cobalt film) having a thickness of 40 nm is deposited on the entire surface of the substrate. At this time, a sputtering method using titanium (or cobalt) as a target is used. At this time, the oxide film 31 is often removed spontaneously, but a step of removing the oxide film 31 by etching or holding at a high temperature in a vacuum before sputtering can be added.

Next, heat treatment is performed at 650 ° C. for 30 minutes to form titanium (or cobalt) forming the metal film, polysilicon forming the gate electrode 8, and high-concentration source / drain regions 6. By reacting with single crystal silicon, the surface portions of the gate electrode 8 and the high concentration source / drain regions 6 are silicided to form titanium silicide films 11a and 11b. Then, the unreacted metal film is removed.

Subsequent steps are as described in the first embodiment. When the TEOS mask 10a is removed, in the silicidation region Rsi, the gate electrode 8 and the high-concentration source / drain whose surfaces are silicided are formed. N-channel MOS transistor having region 6 and p
A channel type MOS transistor is formed. In the non-silicided region Rnsi, a high-breakdown-voltage n-channel MOS transistor having a non-silicided gate electrode 8 and a high-concentration source / drain region 6 and a high-breakdown-voltage p
A channel type MOS transistor and a resistance element having a resistance film 13 that is not silicided are formed.

The present embodiment is different from the first embodiment in that the first and second RTA processes are performed in an atmosphere containing oxygen, and that the TEOS film 10 is patterned to form a TEOS mask 10a. Is formed, and then ion implantation for pre-amorphization is performed. As a result, the following effects can be obtained.

First, the first RTA process is performed in an atmosphere containing oxygen, so that the polysilicon film 1 is formed.
Oxide film 30 is formed on 2. Therefore, during the first RTA process, out diffusion of the n-type impurity can be suppressed. As a result, it is possible to effectively prevent the conductivity from deteriorating due to the reduction of the n-type impurity doped in the polysilicon film. In addition, if holes are formed in the polysilicon film due to the n-type impurities coming out of the polysilicon film 12, the resistance value of the polysilicon film increases. In addition, since the holes are not silicided later, the resistance of the silicide layer also increases. That is, as a whole, there is a possibility of causing a problem that the resistance value of the polysilicon film varies, but such a problem can be solved by suppressing out diffusion of the n-type impurity by the presence of the oxide film 30. Can be.

Next, by performing the second RTA process in an atmosphere containing oxygen, the variation in the resistance value of the gate electrode and the high-concentration source / drain region 6 due to the suppression of the out diffusion of the n-type and p-type impurities. The following effects are obtained in addition to the suppression effect. That is, the impurity concentration originally doped in each of the well regions 3x, 3y, 3z, 3w for controlling the threshold value of the MOS transistor is extremely lower than the impurity concentration in the source / drain region 6. Therefore, when As ⁺ penetrates through the gate electrode 8 and reaches the channel region in the Si substrate 1 during ion implantation for pre-amorphization, the MOS
It was found that the threshold voltage of the transistor fluctuated. Therefore, as in the present embodiment, by forming the oxide film 31 on the gate electrode 8 by the second RTA process, ions (As ⁺ ) implanted for pre-amorphization penetrate the gate electrode 8. Reaching the channel region (due to channeling). That is, it is possible to prevent the threshold voltage from fluctuating due to the penetration of impurities of the n-channel MOS transistor formed in the silicidation region Rsi.

On the other hand, in the non-silicidation region Rnsi, the heat treatment is performed while being covered with the TEOS film mask 10a, so that the out diffusion of the n-type and p-type impurities can be surely suppressed.

Further, only the activation of the n-type impurity among the impurities doped in the polysilicon film 12 by the first RTA process is performed, and the activation of the p-type impurity doped in the polysilicon film 12 is performed. Therefore, it is possible to suppress the p-type impurity from diffusing and entering the gate oxide films 7a and 7b and the Si substrate 1. That is, a p-channel MOS transistor and a high-breakdown-voltage p-channel MOS transistor
It is possible to prevent deterioration of the conductivity of the gate electrode 8 of the transistor, deterioration of the insulating properties of the gate oxide films 7a and 7b, fluctuation of the threshold voltage, and the like.

Here, data on the effect of performing the RTA process in an atmosphere containing oxygen will be described.

FIGS. 5A to 5C show SEM images of the upper surface of a sample subjected to RTA processing under three conditions to confirm the effect of RTA processing in an atmosphere containing oxygen.
It is the figure which copied the image. A gate electrode made of polysilicon is provided on the upper surface of the sample shown in FIGS.
A sidewall made of an oxide film surrounding the periphery of the gate electrode and a surface of the silicon substrate on which the high-concentration source / drain regions are formed appear.

FIG. 5A shows that only N ₂ is supplied at a flow rate of 5.0 sl.
The upper surface state of the sample when the RTA process is performed while flowing at cm. FIG. 5 (b) shows a top state of the sample when subjected to RTA process while flowing the flow rate of N _{2/0 2} as 5.0 / 0.3slcm. FIG. 5 (c), the flow rate of the N _{2/0 2} 5.0 / 20.0sl
2 shows the state of the upper surface of the sample when the RTA process was performed while flowing the sample as cm. As shown in FIG.
When the RTA process is performed while flowing only N ₂ ,
It can be seen that holes are formed in the gate electrode made of the polysilicon layer due to the removal of impurities. On the other hand, as shown in FIGS. 5B and 5C, when the RTA process is performed while flowing N ₂ and O ₂ , holes exist in the gate electrode made of the polysilicon layer. Absent. That is, it was confirmed that by performing the heat treatment (RTA treatment in the present embodiment) in an atmosphere containing oxygen, the out-diffusion of impurities in the polysilicon layer can be surely suppressed.

FIG. 6 is a diagram showing O in the RTA process._Two Against partial pressure
Of threshold voltage of n-channel MOS transistor
And source / drain of p-channel MOS transistor
Of drain current due to lower impurity concentration in the
It is a figure which shows a fall. In the figure, the horizontal axis is O_Two Partial pressure
((O_Two / (N_Two + O_Two )), And the vertical axis is n-channel
Voltage (V) of p-type MOS transistor and p-channel
Saturation drain current (μA /
μm). As shown in FIG. _Two Partial pressure
2.5% or less, n-channel MOS transistor
Shift of the threshold voltage of_Two About partial pressure
If it exceeds 40%, the p-channel MOS transistor becomes saturated.
The sum drain current is significantly reduced. That is, O_Two Partial pressure
Increases, an oxide film is formed thicker on the substrate,
At the same time, boron which is a p-type impurity in the source / drain regions
Is absorbed into the oxide film,
Source and drain regions increase in electrical resistance
Current decreases.

FIG. 7 shows the variation in resistance due to the generation of vacancies in the polysilicon layer and the variation in resistance due to insufficient removal of the oxide film on the polysilicon layer with respect to the O ₂ partial pressure during the RTA process. FIG. In the figure, the horizontal axis represents the O ₂ partial pressure ((O ₂ / (N ₂ + O ₂ )), and the vertical axis represents the sheet resistance (Ω / s) of the silicide layer and the polysilicon layer.
q. ). As shown in the figure, when the O ₂ partial pressure becomes 2.5% or less, the variation in sheet resistance of the silicide layer and the polysilicon layer due to the generation of vacancies increases, and the O ₂ partial pressure becomes about 40%. Is exceeded, the oxide film on the polysilicon layer becomes thicker, and the sheet resistance of the silicide layer and the polysilicon layer due to insufficient removal of the oxide film in the subsequent process becomes large. Note that adding an additional oxide film removing step complicates the process,
If possible, it is preferable not to provide an oxide film removing step.

From the data shown in FIGS. 6 and 7, the O ₂ partial pressure is preferably from 2.5 to 40%, more preferably from 5 to 30%.

(Third Embodiment) FIGS. 8A and 8B and FIGS. 9A to 9C are cross-sectional views showing steps of manufacturing a semiconductor device according to a third embodiment of the present invention. It is.

First, up to the step shown in FIG. 8A, the same processing as the steps shown in FIGS. 2A to 2C in the second embodiment is performed.

Then, in the step shown in FIG.
A TEOS film 10 is deposited on the entire surface of the substrate by plasma CVD. In the first embodiment, annealing is performed immediately after this, but in this embodiment, annealing is not performed.

Next, in the step shown in FIG.
A resist mask 24 is formed on the EOS film 10 so as to cover the non-silicided region Rnsi and open the silicided region Rsi. Then, wet etching is performed using the resist mask 24 as an etching mask to remove a portion of the TEOS film 10 included in the silicidation region Rsi. As a result, a TEOS mask 10a covering the non-silicided region Rnsi is formed, and the surface of the source / drain region 6 and the gate electrode 8 of each MOS transistor in the silicide formation region Rsi is exposed.

Here, in the second embodiment,
The resist mask 23 is made of sulfuric acid / hydrogen peroxide (sulfuric acid + hydrogen peroxide +
(Water).

On the other hand, in the present embodiment, FIG.
In the step shown in (a), after performing ashing with O ₂ plasma, the resist mask 24 is further washed with sulfuric acid / hydrogen peroxide (sulfuric acid + hydrogen peroxide + water).
Is removed. At this time, by performing ashing with O ₂ plasma, an oxide film 32 is formed on a portion not covered by the TEOS mask 10a, that is, on the gate electrode 8 and the source / drain region 6 of the MOS transistor in the silicide formation region Rsi. It is formed. That is, the oxide film 32 is also formed on the gate electrode 8 in the pMOSFET formation region Rsp. As a result, the out diffusion of the p-type impurity (boron) in the gate electrode 8 of the pMOS transistor during the RTA process is suppressed, and the penetration of As does not occur even by the subsequent ion implantation during the pre-amorphous formation. The same effect as that of the embodiment can be obtained.

At this time, the ashing temperature is 150 to 30.
It is in the range of 0 ° C.

Next, in the step shown in FIG. 9B, in order to facilitate silicidation of the surface of the gate electrode 8 and the high concentration source / drain region 6, the gate electrode 8 and the high concentration source Perform ion implantation for pre-amorphizing the surface of the drain region 6. That is, using the TEOS mask 10a as an implantation mask, arsenic ions (As ⁺ ) are applied to the gate electrode 8 and the high-concentration source / drain regions 6 at a dose of about 5
The implantation is performed under conditions of × 10 ¹⁵ cm ^-2 and an implantation energy of about 20 keV. As a result, the regions near the surfaces of the gate electrode 8 and the high-concentration source / drain regions 6 are made amorphous, so that silicide is easily formed. Since the dose in the ion implantation at this time is extremely smaller than the dose in the ion implantation into the polysilicon film and the source / drain regions, the conductivity due to impurities implanted into the polysilicon film and the source / drain regions is reduced. Will not be compromised.

The ion species implanted at this time is
It has a function to make the area to be made amorphous
As long as it is enough,⁺ Not only for example
Ge ⁺ Ions using ions of relatively large atoms such as
An injection may be performed.

Next, in the step shown in FIG. 9C, a metal film made of titanium (or cobalt film) having a thickness of 50 nm is deposited on the entire surface of the substrate. At this time, a sputtering method using titanium (or cobalt) as a target is used.

Next, heat treatment is performed at 650 ° C. for 30 minutes to form titanium (or cobalt) and the gate electrode 8.
Of the gate electrode 8 and the high-concentration source / drain regions 6 are silicided by reacting the polysilicon constituting the silicon nitride and the single-crystal silicon forming the high-concentration source / drain regions 6 to form a titanium silicide film 11a. , 11b. Then, the unreacted metal film is removed.

The subsequent steps are the same as those described in the first embodiment. When the TEOS mask 10a is removed, in the silicidation region Rsi, the gate electrode 8 and the high-concentration source / drain whose surfaces are silicided are formed. N-channel MOS transistor having region 6 and p
A channel type MOS transistor is formed. In the non-silicided region Rnsi, a high-breakdown-voltage n-channel MOS transistor having a non-silicided gate electrode 8 and a high-concentration source / drain region 6 and a high-breakdown-voltage p
A channel type MOS transistor and a resistance element having a resistance film 13 that is not silicided are formed.

Also in this embodiment, the first RTA
By performing the treatment and the second RTA treatment in an atmosphere containing oxygen, the same effect as in the second embodiment can be exhibited. In addition, in the present embodiment, when the resist mask 24 is removed by ashing using O ₂ plasma, the oxide film 32 is formed on the gate electrode 8, so that high-temperature processing such as RTA processing is not performed. This has the advantage that adverse effects on the characteristics of the MOS transistor can be reliably avoided.

Note that, in order to activate the p-type impurities implanted in the resistor film 13 and the gate electrode 8 of the p-type MOS transistor, the oxide film 32 shown in FIG. RTA process is performed. Also in this case, in the present embodiment, there is an advantage that the oxide film 32 having an optimum thickness can be formed under conditions unrelated to the conditions of the RTA process.

The RTA for activating the source / drain impurities may be performed after forming the interlayer insulating film.

(Modification of Third Embodiment) In the third embodiment, in order to form an oxide film while removing the resist mask 24, first, ashing (plasma oxidation) using O ₂ plasma is performed. After that, washing with sulfuric acid / hydrogen peroxide (sulfuric acid + hydrogen peroxide + water) was performed, but this procedure may be reversed. That is, sulfuric acid-hydrogen peroxide (sulfuric acid +
After removing the resist mask 24 by washing with hydrogen peroxide + water), an oxide film 32 is formed on the gate electrode 8 and the high-concentration source / drain regions 6 by O ₂ plasma treatment (plasma oxidation). be able to.
Thereafter, by performing a second RTA, it is possible to suppress out diffusion of impurities and penetration of ions for pre-amorphization, and the same effects as in the third embodiment can be exhibited.

(Other Embodiments) In each of the above embodiments, the non-silicidized region Rnsi is provided with a high withstand voltage MOS.
Although a transistor is provided, the present invention is not limited to such an embodiment. That is, the present invention can be applied to a case where only the resistance element is arranged in the non-silicidation region. The present invention can also be applied to an arrangement in which an electrode (upper electrode) of a capacitor is disposed in the silicided region Rsi or the non-silicided region Rnsi.

[0090]

According to the first method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having a silicided region and a non-silicided region, a part of the polysilicon film has an n for reducing a resistance value. After implanting the type impurity ions,
After performing the first heat treatment, p-type impurity ions for reducing the resistance value are implanted into the other part of the polysilicon film, and thereafter,
After the polysilicon film is patterned, a second heat treatment is performed in a state where the non-silicided region is covered with the silicidation mask so that impurity ions for promoting silicidation are implanted and silicidation is performed. Therefore, without increasing the number of steps, it is possible to form a semiconductor device having no side etch at the upper end of a member such as a gate electrode and having a small variation in the resistance value of a polysilicon member disposed in a non-silicidation region.

In particular, by performing the first and second heat treatments in an atmosphere containing oxygen, an oxide film is formed on a polysilicon film, a gate electrode, or the like, and out diffusion of impurities during the heat treatment is suppressed. can do.

According to the second method for fabricating a semiconductor device of the present invention, after the impurity ions for reducing the resistance value are implanted into the polysilicon layer on the semiconductor substrate, the substrate is heat-treated in an atmosphere containing oxygen. As a result, an oxide film is formed on the polysilicon layer serving as a resistor film, a gate electrode, and the like, so that out-diffusion of impurities during heat treatment can be suppressed.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating a first half of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating an intermediate portion in a manufacturing process of a semiconductor device according to a second embodiment of the present invention. as well as

FIGS. 4A to 4C are cross-sectional views illustrating a latter half of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5C are diagrams in which SEM images of the upper surface of a sample subjected to RTA processing under three kinds of conditions are copied in order to confirm the effect of RTA processing in an atmosphere containing oxygen. It is.

FIG. 6 shows a change in threshold voltage of an n-channel MOS transistor with respect to a partial pressure of O ₂ during RTA processing, and a decrease in drain current due to a decrease in impurity concentration in source / drain regions of a p-channel MOS transistor FIG.

FIG. 7 is a diagram showing a variation in resistance due to the generation of holes in the polysilicon layer and a variation in resistance due to insufficient removal of an oxide film on the polysilicon layer with respect to a partial pressure of O ₂ during the RTA process. is there.

FIGS. 8A and 8B are cross-sectional views illustrating an intermediate portion in a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIGS. 9A to 9C are cross-sectional views illustrating the latter half of the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Si substrate 2 element isolation insulating film 3 well region 5 LDD region 6 high-concentration source / drain region 7 gate oxide film 8 gate electrode 9 sidewall 10 TEOS film 11 silicide layer 12 polysilicon film 13 resistor film Rsi silicidation region Rnsi Non-silicided region Rsn nMOSFET formation region Rsp pMOSFET formation region Rnn High withstand voltage nMOSFET formation region Rnp High withstand voltage pMOSFET formation region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/04 H01L 27/08 102C 21/822 29/78 301P 27/088 301K 29/78 21/336

Claims (11)

[Claims] 1. A silicidation region in which a MOS transistor in which the upper portions of a gate electrode and a high-concentration source / drain region are silicided is arranged, and an element in which an upper portion has a non-silicided polysilicon member is arranged. A method for manufacturing a semiconductor device having a non-silicided region, comprising: a step (a) of forming a gate insulating film and a polysilicon film on a semiconductor substrate; and a mask having an opening in an n-type impurity implantation region. A step (b) of implanting n-type impurity ions for reducing a resistance value into a part of the polysilicon film, a step (c) of performing a first heat treatment for activating the n-type impurity, After the step (c), a step of implanting p-type impurity ions for reducing the resistance value into the other portion of the polysilicon film using a mask having an opening in the p-type impurity implantation region (d) Patterning the polysilicon film after the step (d) to form the gate electrode of the MOS transistor in the silicidation region and the polysilicon member in the non-silicidation region (e). And (f) implanting impurity ions for forming a high-concentration source / drain region of the MOS transistor.
A step (g) of forming an insulating film on the substrate after the step (f); a step (h) of forming a mask for selective etching on the insulating film; and using the mask for selective etching. (I) forming a silicide mask covering the non-silicided region and opening the silicidized region by patterning the insulating film by using the p-type impurity. (J) performing a second heat treatment for activating the MOS, and after the step (j), the MOS in the silicidation region is formed.
A step (k) of implanting impurity ions for promoting silicidation into the gate electrode and the high-concentration source / drain regions of the transistor; and, after the step (k), a MOS of the silicidized region.
A step (l) of silicidizing the upper part of the gate electrode and the high-concentration source / drain region of the transistor. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment is performed in an atmosphere containing oxygen. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the partial pressure of oxygen in the atmosphere containing oxygen in the first heat treatment is 5 to 30%. Production method. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the second heat treatment is performed in an atmosphere containing oxygen. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the partial pressure of oxygen in the atmosphere containing oxygen in the second heat treatment is 5 to 30%. Production method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (h), the selective etching mask is formed of a resist film, and the step (i) is performed after the step (i). A method of manufacturing a semiconductor device, further comprising a step of removing the resist film by ashing with oxygen plasma before j). 7. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (h), the selective etching mask is formed of a resist film, and the step (i) is performed after the step (i). Before j), after the resist film is removed with an aqueous solution of sulfuric acid and hydrogen peroxide, a step of plasma oxidizing the gate electrode in the silicidation region and the surface portion of the high-concentration source / drain region is further provided. A method for manufacturing a semiconductor device, comprising: 8. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step (b), the resistive element of the resistive element is used as the polysilicon member of the element in the non-silicided region. A method for manufacturing a semiconductor device, comprising forming at least one of a film and a gate electrode of a high breakdown voltage transistor. 9. A step (a) of implanting an impurity for reducing a resistance value into a polysilicon layer on a semiconductor substrate, and a step (b) of heat-treating the substrate in an atmosphere containing oxygen.
And a method for manufacturing a semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the polysilicon layer is a gate electrode of a MOS transistor, and after the step (b), the polysilicon layer is formed in the polysilicon layer to promote silicidation. A method of manufacturing a semiconductor device, further comprising: a step (c) of introducing an impurity; and a step (d) of silicidizing an upper portion of the polysilicon layer after the step (c). 11. The method of manufacturing a semiconductor device according to claim 9, wherein said polysilicon layer is a resistor of a resistance element.