JP3190858B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a semiconductor device using a technique of siliciding a diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art The miniaturization and higher density of the structure of semiconductor devices are still being vigorously pursued. For miniaturization, a semiconductor element formed with a size of 0.25 μm is currently used, and semiconductor devices such as a memory device or a logic device based on this size as a design standard have been put to practical use.

[0003] Such miniaturization is the most effective method for achieving high performance or multifunctionality due to high integration, high speed, etc. of a semiconductor device, and is indispensable for the manufacture of semiconductor devices in the future. With the miniaturization of such semiconductor elements, it has become necessary to make the impurity diffusion layers for forming source and drain regions extremely shallow. However, making the diffusion layer shallow leads to an increase in resistance of the source and drain regions, significantly lowering the current driving capability of an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor), and hindering the speeding up of the semiconductor device. .
In order to solve such a problem, a MOS transistor having a so-called silicide structure in which a silicide layer is selectively formed on a diffusion layer forming a source / drain and the resistance of the source / drain is extremely reduced has been used. I have.

However, in this silicide structure MOS transistor, since a diffusion layer (source / drain) resistance is small, a large current easily flows, and the semiconductor device is ESD (E)
There is a drawback that the device is susceptible to electrostatic breakdown due to electro-static discharge or the like. Therefore,
For example, as disclosed in Japanese Patent Application Laid-Open No. 1-259560, the input / output section of the semiconductor integrated circuit must not be selectively silicided. A conventional method for manufacturing such a semiconductor device will be described with reference to FIG. 2 (hereinafter, referred to as a first conventional example).

First, as shown in FIG. 2A, a field oxide film 12 for element isolation is formed on a silicon substrate 11 by forming a groove and performing selective oxidation. Next, the gate electrode 14 and the sidewall 1 made of an insulating film are interposed via the gate oxide film 13.
5 and diffusion layer 16 of impurities constituting source / drain
To form

Next, as shown in FIG. 2B, after an oxide film is deposited on the substrate by a chemical vapor deposition (CVD) method, a MOS transistor of an input / output circuit section, that is, an input / output transistor (Tr) is formed. A) A photoresist mask patterned to leave the mask oxide film 17 only in the region is formed, and the oxide film other than the input / output transistor region is removed by plasma etching.

Next, as shown in FIG. 2C, titanium (T
i) Titanium silicidation is performed by depositing and annealing a film to selectively form a Ti silicide layer 18 on the MOS transistor in the internal circuit portion, that is, on the diffusion layer 16 in the internal transistor (Tr) region. At this time, the mask oxide film 17 becomes a protective film for preventing the diffusion layer 16 in the input / output transistor region from being silicided.

By the way, as shown in FIG. 2B, during plasma etching for forming the mask oxide film 17, the field oxide film 12 in the internal transistor region is reduced by overetching, and the field oxide film 1 is removed.
2 is lower than the silicon substrate surface. In an extreme case, a large concave portion is formed. In this region, the silicon substrate 11 and the diffusion layer 16 are short-circuited through the Ti silicide layer 18 as shown in FIG.

Therefore, the present inventor has filed Japanese Patent Application No. 8-28231.
No. 8 proposed a method for solving such a problem. Hereinafter, this method will be described with reference to FIG.
Described as a conventional example).

First, as shown in FIG. 3A, a thin oxide film and a nitride film are formed on a silicon substrate 11 in the same manner as in the first prior art, and then the silicon substrate 11 is etched.
Then, a trench having a depth of about 60 nm is formed and then selectively oxidized to form a field oxide film 12 for separating an element region. Next, after forming a gate oxide film 13, a polysilicon film and a silicide film are deposited and patterned to form a gate electrode. Next, an oxide film (or a nitride film) having a thickness of about 200 nm is formed on the entire surface by the CVD method, and then anisotropically etched to form sidewalls 15 on the side surfaces of the gate electrode 14. Next, an impurity is introduced using the field oxide film 12, the gate electrode 14, and the sidewalls 15 as a mask to form a diffusion layer 16 constituting source / drain.

Next, as shown in FIG. 3B, a silicon oxide film having a thickness of 50 to 150 nm is formed on the entire surface by the CVD method, and then a photoresist film is formed on the entire surface. Next, the photoresist film is left so as to completely cover the field oxide film 12 in the input / output transistor region and the internal transistor region, and the silicon oxide film is dry-etched and removed using the photoresist film as a mask to remove the mask oxide film 19. To form Next, the photoresist film used as the mask is removed. In this step, the mask oxide film 19 is left on the input / output transistor as a measure against electrostatic breakdown, and the field oxide film 12 is formed in the internal transistor region.
This is to prevent the field oxide film 12 from being thinned due to over-etching when the mask oxide film 19 is etched.

In the step of patterning the mask oxide film 19, the photoresist film formed on the silicon substrate is exposed using a reduction projection exposure machine (stepper).
"Displacement" inevitably occurs. However, even if misalignment occurs for the purpose of the present invention, the field oxide film 12
Since the mask oxide film 19 must be patterned so that the end of the mask oxide film 19 is not exposed, the etching end of the mask oxide film 19 extends over the diffusion layer 16 in the internal transistor region as shown in FIG. Extension 20 to be positioned
Is provided. The width of the extending portion 20 does not exceed the allowable misalignment range of the product.

Next, as shown in FIG. 3C, a Ti film having a thickness of about 35 nm is formed on the entire surface by a sputtering method.
Heating is performed in an inert gas atmosphere to form a Ti silicide layer 21 on the diffusion layer 16 in the internal transistor region. The unreacted Ti film is removed by wet etching using aqueous ammonia and aqueous hydrogen peroxide. After that, interlayer insulating film,
A semiconductor device is completed by a normal manufacturing process of a MOS transistor such as a contact hole and a wiring.

As described above, according to the second conventional example, since the field oxide film 12 in the internal transistor region as well as the input / output transistor region is covered with the mask oxide film 19, the Ti formed on the diffusion layer 16 is formed. Silicide layer 21
Are formed at a distance from the end of the field oxide film 12. Therefore, the Ti silicide layer 21 does not come into contact with the silicon substrate 11.

[0015]

In the above-mentioned first conventional example, the field oxide film 12 in the MOS transistor region of the internal circuit portion is reduced by overetching so as to be larger than the depth of the diffusion layer 16 constituting the source / drain. In this case, the surface of the silicon substrate 11 exposed due to the decrease in film thickness also has T
Since the i-silicide layer 18 is formed, a short circuit occurs between the Ti silicide layer and the silicon substrate, and there is a problem that desired integrated circuit characteristics cannot be obtained due to an increase in leak current.

In the second conventional example, it is essential to form the extension 20 covering a part of the diffusion layer 16. However, when the semiconductor element is further miniaturized, the region of the diffusion layer 16 is narrowed, and it is difficult to form the extending portion 20. Therefore, this method makes it difficult to cope with miniaturization of semiconductor elements.

An object of the present invention is to provide a semiconductor device which solves all of the above problems, has a source and a drain which are silicidized, has excellent electrostatic breakdown resistance, and which can cope with miniaturization by a simple method, and a method of manufacturing the same. Is to do.

[0018]

For this purpose, in the semiconductor device of the present invention, in a semiconductor integrated circuit composed of MOS transistors, a first film of a predetermined thickness is formed on a diffusion layer of a MOS transistor constituting an internal circuit. A second silicide layer having a smaller thickness than the first silicide layer is formed on the diffusion layer of the MOS transistor constituting the input / output circuit.
Is formed.

Alternatively, in a semiconductor integrated circuit composed of MOS transistors, a MOS
A titanium silicide layer having a C54 crystal structure having a low resistance phase is formed on a diffusion layer of the transistor, and a titanium silicide layer having a C49 crystal structure having a high resistance phase is formed on a diffusion layer of a MOS transistor constituting an input / output circuit. Is formed. Here, the thickness of the titanium silicide layer having the C54 crystal structure is formed to be larger than the thickness of the titanium silicide layer having the C49 crystal structure.

[0020]

Further, the method of manufacturing a semiconductor device according to the present invention
A method of silicidizing a diffusion layer serving as a source / drain of a MOS transistor on a semiconductor substrate with a high melting point metal, comprising the steps of: amorphizing a surface of a diffusion layer in a predetermined region on a semiconductor substrate; Depositing a refractory metal film and performing a heat treatment, forming a thick, low-resistance silicide layer on the diffusion layer in the predetermined region and simultaneously forming a thin, high-resistance silicide layer on the diffusion layer outside the predetermined region. A resistor silicide layer is formed. Here, the amorphization is performed by arsenic or silicon ion implantation.

If the surface of the diffusion layer which becomes the source / drain of the MOS transistor constituting the semiconductor device is made amorphous, silicidation is greatly promoted from the surface of the non-amorphized diffusion layer. In particular, in the formation of the titanium silicide layer, the silicide layer on the surface of the diffusion layer, that is, the first silicide layer, that is, the first silicide layer has a C54 crystal structure and has a low resistance through heat treatment for appropriate silicidation. . The simultaneously formed silicide layer on the surface of the diffusion layer that has not been made amorphous, that is, the second silicide layer has a C49 crystal structure and has a high resistance. Since the resistance of the second silicide layer is easily increased, the electrostatic breakdown resistance of the semiconductor device is easily improved.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1C are cross-sectional views of a semiconductor chip for describing an embodiment of the present invention.

First, as shown in FIG. 1A, a thin oxide film and a nitride film are formed on a silicon substrate 1 and etched in the same manner as in the prior art, and the silicon substrate 1 is etched to a depth of about 60 nm. After the grooves are formed, selective oxidation is performed to form a field oxide film 2 for isolating the element region. Next, after forming a gate oxide film 3, a polysilicon film and a silicide film are deposited and patterned to form a gate electrode 4. Next, an oxide film (or nitride film) having a thickness of about 200 nm is formed on the entire surface by the CVD method, and then anisotropically etched to form sidewalls 5 on the side surfaces of the gate electrode 4. Next, impurities are introduced by using the field oxide film 2, the gate electrode 4 and the side walls 5 as a mask to form a diffusion layer 6 constituting a source / drain.

Next, as shown in FIG. 1 (b), a photoresist film is formed on the entire surface, and the photoresist film is formed so as to completely cover the MOS transistor region of the input / output circuit section, that is, the input / output transistor region. Mask 7
To form

Next, the resist mask 7 and the M
Arsenic is ion-implanted using the gate electrode 4 and the side wall 5 in the OS transistor region, that is, the internal transistor region as a mask. Here, the arsenic implantation energy is 30 keV and the dose is 1 × 10 ¹⁴ ions /
cm ² . By this ion implantation, an amorphous layer 8 is selectively formed on the surface of the diffusion layer 6 in the internal transistor region. Note that the depth of the amorphous layer 8 is about 15 nm. Here, the arsenic ions are implanted into the diffusion layers of the n-channel MOS transistor and the p-channel MOS transistor in the internal transistor region. The conductivity type does not change in the diffusion layer of the P-channel MOS transistor. This is because the arsenic concentration in this diffusion region becomes lower than the boron concentration.

After the resist mask 7 used as the arsenic ion implantation mask is removed by a known method, a Ti film having a thickness of about 35 nm is formed on the entire surface by a sputtering method, and then heat treatment is performed. Here, this heat treatment is a heat treatment at a temperature of 700 to 750 ° C. in a nitrogen gas atmosphere. FIG.
As shown in (c), the heat treatment forms a first silicide layer 9 on the diffusion layer 6 in the internal transistor region, and at the same time, forms a second silicide layer 10 on the diffusion layer 6 in the input / output transistor region. It is formed.

In the above heat treatment step, the amorphous layer 8 in the internal transistor region promotes the silicidation of the Ti film. Therefore, the thickness of the first silicide layer 9 is 2
While the thickness is about 0 nm, the thickness of the second silicide layer 10 is a half thereof, that is, about 10 nm. Moreover,
The amorphous layer 8 lowers the resistance of the silicided titanium silicide layer. That is, in the amorphous layer 8,
The formed first silicide layer 9 has a low resistance phase of C
It tends to have a crystal structure called 54. On the other hand, at the above heat treatment temperature, the second silicide layer 10 has a crystal structure called C49 which is a high resistance phase.

As described above, the layer resistance of the diffusion layer after silicidation of the internal transistor region is reduced to 5Ω / □ or less. The layer resistance of the input / output transistor region after silicidation is increased to 100Ω / □ or more. The unreacted Ti film in the above heat treatment is removed by wet etching using aqueous ammonia and aqueous hydrogen peroxide. Thereafter, a semiconductor device is completed by a normal process of manufacturing a MOS transistor such as an interlayer insulating film, a contact hole, and a wiring.

As described above, in the MOS transistor having the gate oxide film 3 and the gate electrode 4 and constituting an internal circuit portion, the first silicide layer 9 having a relatively large thickness and a C54 structure reduces the resistance. The diffused layer 6 becomes the source / drain of this MOS transistor.

Then, similarly, M
In the case of the OS transistor, the diffusion layer 6 having a small film thickness and a high / low resistance made by the second silicide layer 10 having the C49 structure serves as a source and a drain of the MOS transistor.

According to the above-described method, a very simple method of manufacturing a semiconductor device can be used.
A high-resistance silicide layer can be formed in a diffusion layer of a transistor. For this reason, the electrostatic breakdown resistance of the semiconductor device is greatly improved. At the same time, a low-resistance silicide layer can be formed in the diffusion layer of the MOS transistor in the internal circuit portion. For this reason, the performance of the semiconductor device having a fine structure is easily improved.

In the above embodiment, the amorphous layer 8
Was formed, arsenic ions were selectively implanted into the internal transistor region. Here, silicon ions may be selectively implanted instead of arsenic ions.

When the amorphous layer 8 is formed by ion implantation of silicon ions, the implantation energy is 15 k
It is set to about eV. And the dose amount is 1 × 10 ¹⁵
Set to ions / cm ² . In this case, Ti
The temperature of the heat treatment for silicidation of the film is 650 to 70
0 ° C., lower than in the case of arsenic ion implantation. This is because the presence of excessive silicon atoms in the amorphous layer 8 further promotes silicidation of the Ti film. Also, when the temperature of the heat treatment is lowered,
The reaction rate between the atmosphere gas nitrogen and the Ti film is higher than the reaction rate for silicidation. That is, titanium nitride formation is superior to silicide formation. this is,
This is noticeable in a region where silicon ions are not implanted, that is, on a diffusion layer of a MOS transistor in an input / output circuit portion.

After silicidation of the Ti film, a 20 nm thick film is formed on the diffusion layer 6 of the MOS transistor in the internal circuit portion.
Is formed, the MOS of the input / output circuit section is formed.
On the diffusion layer 6 of the transistor, a silicide layer of 5 nm or less is formed. For this reason, the resistance of the source / drain of the MOS transistor in the input / output circuit section increases, and furthermore, the electrostatic breakdown resistance of the semiconductor device improves.

When the amorphous layer 8 is formed by ion implantation of silicon ions, if the conditions for implanting silicon ions or the heat treatment conditions are further optimized, the silicide layer is selectively formed only on the diffusion layer of the MOS transistor in the internal circuit portion. Can be formed.

In the above silicidation, the formation of the titanium silicide layer has been described. The present invention is not limited to forming a titanium silicide layer. It should be noted that the method of the present invention is equally applicable to silicidation of refractory metals such as cobalt or tungsten.

[0038]

As described above, according to the present invention, the MOS
In a semiconductor integrated circuit composed of transistors, a first silicide layer having a predetermined thickness is formed on a diffusion layer of a MOS transistor forming an internal circuit, and is formed on a diffusion layer of a MOS transistor forming an input / output circuit. A second silicide layer having a thickness smaller than that of the first silicide layer is formed. Here, the first silicide layer has a low resistance phase of C
A titanium silicide layer having a 54 crystal structure is formed, and a titanium silicide layer having a C49 crystal structure, which is a high resistance phase, is formed as a second silicide layer.

The method of forming these two types of silicide layers includes a step of amorphizing the surface of the diffusion layer in a predetermined region on the semiconductor substrate, and a step of depositing a high melting point metal film over the entire surface after the amorphization and performing a heat treatment. Having. Then, simultaneously with forming the first silicide layer on the diffusion layer in the predetermined region, a second silicide layer is formed on the diffusion layer outside the predetermined region.

In this manner, a highly-resistive silicide layer can be formed in a diffusion layer of a MOS transistor in an input / output circuit portion of a semiconductor device by a very simple method of manufacturing a semiconductor device. For this reason, the electrostatic breakdown resistance of the semiconductor device is greatly improved.

At the same time, M
A low-resistance silicide layer can be formed in a diffusion layer of the OS transistor. Therefore, the performance of the semiconductor device can be easily improved.

As described above, the fine and source
The electrostatic breakdown resistance of a semiconductor device including a MOS transistor whose drain is silicided can be easily improved by a highly reliable and simple method.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in the order of manufacturing steps for describing an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a first conventional example in the order of manufacturing steps.

FIG. 3 is a cross-sectional view in the order of manufacturing steps for explaining a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,11 Silicon substrate 2,12 Field oxide film 3,13 Gate oxide film 4,14 Gate electrode 5,15 Side wall 6,16 Diffusion layer 7 Resist mask 8 Amorphous layer 9 First silicide layer 10 Second silicide layer 17, 19 Mask oxide film 18, 21 Ti silicide layer 20 Extension

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/088 H01L 21/8234 H01L 21/28 H01L 29/78 H01L 21/336

Claims (5)

(57) [Claims] In a semiconductor integrated circuit including an insulated gate field effect transistor, a first silicide layer having a predetermined thickness is formed on a diffusion layer of an insulated gate field effect transistor forming an internal circuit. A semiconductor device, wherein a second silicide layer having a smaller thickness than the first silicide layer is formed on a diffusion layer of an insulated gate field effect transistor constituting an output circuit. 2. A semiconductor integrated circuit comprising an insulated gate field effect transistor, wherein a titanium silicide layer of a C54 crystal structure having a low resistance phase is formed on a diffusion layer of the insulated gate field effect transistor forming an internal circuit;
A semiconductor device, wherein a titanium silicide layer having a C49 crystal structure having a high resistance phase is formed on a diffusion layer of an insulated gate field effect transistor forming an input / output circuit. 3. The titanium silicide layer having a C54 crystal structure is formed to be thicker than the titanium silicide layer having a C49 crystal structure.
13. The semiconductor device according to claim 1. 4. A method of siliciding a diffusion layer serving as a source / drain of an insulated gate field effect transistor on a semiconductor substrate with a refractory metal, wherein the surface of the diffusion layer in a predetermined region on the semiconductor substrate is made amorphous. And depositing a refractory metal film over the entire surface after the amorphization and heat-treating, forming a thick low-resistance silicide layer on the diffusion layer in the predetermined region and simultaneously diffusing the silicide layer outside the predetermined region. A method for manufacturing a semiconductor device, comprising: forming a thin, high-resistance silicide layer on a layer. 5. The method according to claim 4, wherein said amorphization is performed by ion implantation of arsenic or silicon.
The manufacturing method of the semiconductor device described in the above.