JP3394204B2 - Method of manufacturing semiconductor device and semiconductor device formed by the method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device capable of realizing a high speed operation while suppressing a short channel effect, and simultaneously responding to miniaturization and high speed operation. The present invention relates to a device manufacturing method and a semiconductor device formed by this method.

[0002]

2. Description of the Related Art With the miniaturization of transistors, the short channel effect becomes remarkable.
In order to suppress this, conventionally, as a method of reducing the electric field at the source / drain region end, a method of forming both the source / drain region end at the LDD structure has been used.
However, at both ends of the source / drain region, the low concentration L
The DD structure is effective in suppressing the short channel effect, but on the other hand, since the low concentration layer has a high resistance, there is a concern that the drive current may decrease. When the drive current decreases, the current driving force decreases, which makes it difficult to realize high-speed transistors. Therefore, an asymmetric LDD structure has been proposed in which only the end of the drain region has a low concentration layer (Japanese Patent Laid-Open No. Sho 6-96).
2-132363, Japanese Patent Application Laid-Open No. 4-171942, Japanese Patent Application Laid-Open No. 5-2756932, and Japanese Patent Application No. 7-3.
No. 8099). For example, Japanese Patent Laid-Open No. 4-171942
2A, the p-type semiconductor substrate 2
After forming the gate electrode 22 and the insulating film 24 on the
After ion implantation from vertically above to form the n-type low-concentration diffusion layer 23, as shown in FIG. 2B, by ion implantation from the direction inclined by 30 to 60 ° on the source region side, A method for forming an n-type high concentration diffusion layer in the region 25 and a relatively long n-type low concentration diffusion layer in the drain region 27 is described.

According to this method, a semiconductor device having an asymmetric LDD structure can be formed without forming a sidewall. However, since the ion implantation is performed at an angle of 30 to 60 ° from the source region 25 side,
Under the gate electrode on the source region 25 side, n-type high-concentration ions are deeply implanted. Therefore, due to this, it becomes difficult to prevent the short channel effect and the transistor characteristics become unstable. Also,
Japanese Laid-Open Patent Publication No. 62-132363 discloses a semiconductor substrate 31.
After forming the gate electrode 32 using the resist layer 34 on it, as shown in FIG. 3A, using the gate electrode 32 and the resist layer 34 as a mask, ion implantation is performed from above to achieve high concentration. An impurity region 33 is formed, and then, as shown in FIG. 3B, the gate electrode 32 is anisotropically etched at an angle from diagonally above the drain region side, and the end of the gate electrode 32 on the drain region side is etched. Has a shape inclined to the inside of the length A, and further, as shown in FIG. 3C, using this gate electrode 32 as a mask, ions are implanted from diagonally above the drain region side, and only at the drain region end. A method of forming the low concentration impurity region 35 is described.

According to this method, it is possible to form a semiconductor device having an asymmetric LDD structure having a low concentration diffusion layer only at the drain region end without forming a sidewall. However, it is necessary to protect the source region side with a resist or the like at the time of anisotropic etching for forming an inclination in the gate electrode 32, which increases the number of times of photo. Further, it is difficult to control the etching shape (inclined shape) of the gate electrode 32, and a transistor using this has a problem that its characteristics become unstable.

Further, in Japanese Patent Application Laid-Open No. 5-27593, after forming a gate electrode 42 on a semiconductor substrate 41,
As shown in FIG. 4A, B ⁺ is implanted from the drain region side by the oblique ion implantation method. At this time, since B ⁺ is blocked by the gate electrode 42, it is not injected into the source region side, and the P-type region 43 is formed only in the drain region side.
After that, as shown in FIG. 4B, P ⁺ ions are ion-implanted into the entire semiconductor substrate 41 from the vertical direction. This allows
As shown in FIG. 4C, P is formed below the gate electrode 42.
^{Since +} is not injected, the drain region 45 has a P-type region 43 below the gate electrode 42, and the drain region 45 itself cancels out B ⁺ and P ^+. The MOS transistor can be formed. According to this MOS transistor, the P-type region 4 is provided only under the gate electrode 42 on the drain region 45 side.
3 exists, the punch-through phenomenon of the depletion layer is suppressed, and the breakdown voltage is increased. Therefore, it becomes possible to cope with the miniaturization of the element itself. However, since the N-type impurity concentration on the drain region 45 side becomes low, the resistance value of the diffusion layer becomes high, and as a result, the drive current becomes low,
There is a problem that it is not possible to cope with the speedup.

[0006]

According to the present invention, (a)
At least one pair of gate electrodes is formed on the semiconductor substrate using the resist film, and the other of the pair of gate electrodes is formed so that the first conductivity type low concentration region can be formed only in the vicinity of one of the gate electrodes. Diagonal ion implantation is performed using the gate electrode as a mask. At that time, the total thickness t of the gate electrode and the resist film, the distance s between the gate electrodes, the width d of the first conductivity type low concentration region from the end of the gate electrode, and An inclination angle θ from the surface of the semiconductor substrate is set so as to satisfy the following equation tan θ = t / (s−d), and an injection protection oxide film is formed on the entire surface of the obtained semiconductor substrate by an oxidation treatment. ) A second conductivity type impurity is ion-implanted from a direction perpendicular to the semiconductor substrate through the implantation protection oxide film to convert the first conductivity type low concentration region into a second conductivity type low concentration region. , The second conductivity By forming a high-concentration source / drain regions, the method of manufacturing a semiconductor device comprises forming a semiconductor device of the asymmetrical LDD structure having a second conductivity type low concentration region only the drain region end is provided.

Further, according to the present invention, there is provided a semiconductor device having an asymmetric LDD structure formed by the above method.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION In the method for manufacturing a semiconductor device of the present invention, first, in step (a), at least one pair of gate electrodes is formed on a semiconductor substrate using a resist film.
Here, the semiconductor substrate that can be used in this manufacturing method is not particularly limited as long as it is a semiconductor substrate on which a semiconductor device is usually manufactured. For example, a semiconductor substrate of silicon, germanium, or the like, GaAs, InGaAs, or the like. And various other compounds such as compound semiconductors. Of these, a silicon substrate is preferable. The semiconductor substrate is
It is preferably doped with one conductivity type impurities. In this case, examples of the first conductivity type impurities include phosphorus and arsenic in the case of P type, and boron and the like in the case of N type. The impurity concentration is not particularly limited as long as it is a concentration contained in a semiconductor substrate that normally forms a transistor,
For example, it may be about 5 × 10 ^{16 to} 3 × 10 ¹⁷ cm ⁻³ . Moreover, an element isolation film such as a LOCOS film may be formed on the semiconductor substrate.

At least one pair of gate electrodes is usually formed on the semiconductor substrate with a gate insulating film interposed therebetween. At this time, the gate electrode can be formed by a known method, for example, a photolithography and etching process using a resist film. Here, the gate electrodes are formed with a distance s between the pair of gate electrodes. Also, the gate electrode is
It is formed so that the total film thickness with the resist film is t.
That is, the gate electrode formed here is used together with the resist film to form the first gate electrode for the other gate electrode in a later step.
Inclination angle θ of the conductivity type low concentration region with respect to the semiconductor substrate surface
In order to function as a mask when forming by oblique ion implantation, a pair of diagonal electrodes is formed in consideration of the relationship between the tilt angle θ of oblique ion implantation and the width d from the end of the gate electrode of the first conductivity type low concentration region described later. It is necessary to adjust the distance s between the gate electrodes and the total film thickness t of the gate electrode and the resist film, and for example, it is preferable that the relationship of tan θ = t / (s−d) is substantially satisfied (FIG. 1C). reference). Specifically, the pair of gate electrodes are preferably formed in parallel with each other, and the distance s between the gate electrodes is
Is about 0.5 to 0.75 μm. The thickness of the gate electrode is about 150 to 200 nm. The film thickness of the resist film when forming the gate electrode is, for example, about 300 to 800 nm, and further 500 n.
It can be around m. The width of the gate electrode is not particularly limited as long as it has a width that is normally used as a word line, and is, for example, 0.35 to
The thickness is about 0.50 μm. The gate electrode is a material that normally functions as a word line of a semiconductor device, for example,
It can be formed of metal such as aluminum, copper, silver, platinum, refractory metal (tungsten, tantalum, titanium, molybdenum, etc.), polysilicon, silicide with refractory metal, polycide, or the like.

Further, oblique ion implantation is performed by using the other gate electrode as a mask so that the first conductivity type low concentration region can be formed only in the vicinity of one of the pair of gate electrodes. The oblique ion implantation at this time is performed from the other gate electrode side, that is, from one of the regions to be the source / drain regions with respect to the one gate electrode, preferably from the drain region side, one gate electrode on the drain region side. The width of the first conductivity type impurity region from the end of the gate electrode is d by providing a tilt angle (tilt angle with respect to the semiconductor substrate surface) such that the first conductivity type impurities are implanted only in the vicinity.
To do so. Here, the inclination angle θ is set so that the total thickness t of the gate electrode and the resist film, the distance s between the pair of gate electrodes, and the end of the gate electrode of the first conductivity type low concentration region are satisfied so as to satisfy the above relational expression. It can be determined in consideration of the distance d, and is, for example, about 50 to 60 °.

That is, when an attempt is made to implant ions obliquely from the drain region side at the above-described inclination angle, the other gate electrode causes a shadowed region on the semiconductor substrate, and this region is not ion-implanted. Therefore, the first-conductivity-type low-concentration region can be formed within the range of the width d from the gate electrode end only on the other gate electrode side, that is, on the drain region side in the vicinity of one gate electrode of the semiconductor substrate. Here, the vicinity of the gate electrode of the semiconductor substrate on the side of the drain region usually means a region having a width about the region where the sidewall spacer formed on the gate electrode is formed. For example, usually, the sidewall spacer formed on the side wall of the gate electrode can be formed by etching back the entire insulating film having a film thickness of about 200 to 240 nm, and the width of the sidewall spacer immediately above the semiconductor substrate region is 0. ．
It is about 1 to 0.15 μm. Therefore, in the vicinity of the gate electrode of the semiconductor substrate on the drain region side, in a region having a width d of about 0.1 to 0.15 μm from the end of the gate electrode (see FIG.
(D) in (d)).

Further, it is necessary to prevent the impurities of the first conductivity type from entering too much under the gate electrode by this oblique ion implantation. Therefore, the ion implantation conditions can be appropriately adjusted depending on, for example, the implantation angle θ and the ion species. For example, the ion species is arsenic ion or BF ^2+.
In the case of, the acceleration energy is about 10 to 20 KeV,
The injection amount may be about 1 to 10 × 10 ¹⁴ cm ⁻² . As a result, the impurity concentration of the first conductivity type low concentration region is 1 ×.
It can be formed at about 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

In step (b), with respect to the semiconductor substrate
The second conductivity type impurities are ion-implanted from the vertical direction. This
The condition of ion implantation at the time of
It can be adjusted appropriately, but the ion species is BF²⁺in the case of
The acceleration energy is about 30 to 50 KeV, and the implantation amount is
Is 1-2 × 10¹⁵cm^-2The degree can be mentioned. By this
The impurity concentration of 1 × 10¹⁷
~ 1 x 10¹⁸cm^-3Converted to the second conductivity type low concentration region
And the impurity concentration is 1 × 10¹⁹
~ 1 x 10²⁰cm^-3Second conductivity type high concentration source /
A drain region can be formed. Also, ionic species
When is arsenic ion, the acceleration energy is 40-60.
KeV, injection amount is 1 to 5 × 10¹⁵cm^-2Degree
To be As a result, the first-conductivity-type low-concentration region is treated as an impurity.
Concentration is 1 × 10¹⁷~ 1 x 10¹⁸cm ^-3Second conductivity type
It is possible to convert to a low concentration area and
Degree is 1 × 10²⁰~ 1 x 10^{twenty one}cm^-3Second conductivity type
High concentration source / drain regions can be formed
It As a result, the second conductivity type low concentration is formed only at the end of the drain region.
Forming a semiconductor device having an asymmetrical LDD structure having a degree region
You can

In the method of manufacturing a semiconductor device of the present invention, cleaning, insulating film formation, protective film formation, channel injection, heat treatment, interlayer insulating film formation, and contact hole formation are performed before, during, and after the above steps. Alternatively, one or more processes that are usually performed when forming a semiconductor device, such as formation of wiring, may be performed. Particularly, it is preferable to form an implantation protection oxide film between the oblique ion implantation and the ion implantation from the vertical direction in order to reduce damage to the substrate during the ion implantation. At this time, the injection protection film is preferably formed by oxidation treatment. By this oxidation treatment, a silicon oxide film having a film thickness of about 50 to 200 Å can be formed on the entire surface of the semiconductor substrate, and a film thickness of 300 is formed by accelerated oxidation particularly on the region ion-implanted in the step (a).
It is possible to form a thick silicon oxide film having a thickness of about 400 Å. Such an implant protection oxide film partially formed as a thick film is implanted with impurities so as to have a peak in the vicinity of the semiconductor substrate surface in the thick film region during ion implantation in the step (b). , The first conductivity type low concentration region can be converted into the second conductivity type low concentration region shallower than the source / drain regions, which is advantageous.

An embodiment of a semiconductor device of the present invention will be described below with reference to the drawings. First, an oxide film (not shown) having a film thickness of about 200 Å is formed in order to reduce damage to the substrate during channel implantation, and then channel implantation ( ¹¹ B ⁺ , implantation energy: 20 KeV, implantation amount: 1.
0-10 × 10 ¹² cm ⁻² ) is performed. Then, pre-cleaning such as RCA cleaning is sufficiently performed to form a gate insulating film 2a (90Å) on the silicon substrate 1 by gate oxidation (900 ° C.), as shown in FIG. A polysilicon film 3a is deposited on the gate insulating film 2a (SiH ⁴ gas,
620 ℃, film thickness 1000 Å), followed by WSi film 4
A is deposited (360 ° C., film thickness 1000 Å).

Next, as shown in FIG. 1B, a resist is applied on the obtained silicon substrate 1, and the resist is patterned by a photolithography and etching process to form a resist mask 5. Using this resist mask 5, the WSi film 4a, the polysilicon film 3a, and the gate insulating film 2a are dry-etched, and the distance s between the gate electrodes is about 0.5 to 0.75 μm. Thickness: 2000 Å, total film thickness of gate electrode and resist film: 7000 Å) and a part of wiring are formed.

Subsequently, as shown in FIG. 1C, the gate electrode 6 and the resist mask 5 are used as a mask,
⁷⁵ As ⁺ implantation is performed from a certain direction at a tilt angle θ of 50 to 60 ° with respect to the surface of the silicon substrate 1, and a low concentration with a width d of about 0.1 to 0.15 μm from the end of the gate electrode 6. Region 7 is formed. The implantation conditions at this time are as follows: implantation energy: 10 to 20 KeV, implantation amount: 1.0 to 10.0 × 1.
A suitable value is about 0 ¹⁴ cm ^-2 . Thereafter, as shown in FIG. 1D, the resist mask 5 is peeled off, and the entire surface of the obtained silicon substrate 1 is oxidized to form an oxide film 8 having a film thickness of about 100Å. The oxide film 8 is for reducing damage to the substrate due to ion implantation in the next step.

Then, as shown in FIG.
From the direction perpendicular to the control board 1 ⁴⁹BF²⁺Make an injection
To form the high-concentration source / drain regions 9.
Then, the low-concentration region 7 is converted into the p-type low-concentration region 9a.
The implantation conditions at this time are implantation energy: 40 KeV,
Quantity: 1.0-2.0 × 10¹⁵cm^-2The degree is appropriate
It Then, as shown in FIG. 1F, the oxide film 8 is removed.
Then, the interlayer insulating film is formed on the entire surface of the obtained silicon substrate 1.
Form 10 and smooth the entire surface by etch back
It After that, a contact hole is formed in the interlayer insulating film 10.
A is formed on the interlayer insulating film 10 including the contact hole.
Form a Cu film and pattern it to form metal wiring 11.
To achieve. With this method, only at the drain region edge
It is possible to form an asymmetric semiconductor device in which low-concentration regions are arranged.
You can

[0019]

According to the present invention, first, by using the adjacent gate electrode as a mask, the first conductivity type low concentration region is formed only at the drain end, and then the first conductivity type low concentration region is formed.
Since the source / drain regions, which are the second conductivity type high concentration regions, are formed at the same time when the conductivity type low concentration region is converted into the second conductivity type low concentration region, the sidewall spacers are not formed and only the drain end is formed. The LDD region can be reliably formed. Therefore, it is possible to simplify the manufacturing process of the semiconductor device, and eventually reduce the manufacturing cost.

Moreover, unlike the prior art, the LDD region can be reliably formed only at the drain end without performing any special processing on the gate electrode itself, so that the semiconductor device has stable characteristics and high reliability. Can be manufactured at low cost. Further, since the second-conductivity-type high-concentration region can be formed by vertical ion implantation, it is possible to prevent impurities from sneaking under the gate electrode, and further, the semiconductor device has stable characteristics and high reliability. Can be manufactured. In addition, while realizing the simplification of the manufacturing process as described above, the short channel effect can be suppressed, and the resistance value of the source / drain regions can be kept low by forming the source / drain regions of the same impurity concentration. As a result, a high drive current can be obtained, and the speed can be increased even when the semiconductor device is miniaturized.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional manufacturing process diagram of an essential part for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional manufacturing process diagram of a main part for explaining a conventional method for manufacturing a semiconductor device.

FIG. 3 is a schematic cross-sectional manufacturing process diagram of a main part for explaining another conventional method for manufacturing a semiconductor device.

FIG. 4 is a schematic cross-sectional manufacturing process diagram of a main part for explaining still another conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Silicon Substrate (Semiconductor Substrate) 2a, 2 Gate Insulating Film 3a Polysilicon Film 4a WSi Film 5 Resist Mask 6 Gate Electrode 7 Low Concentration Region (First Conduction Type Low Concentration Region) 8 Oxide Film (Injection Protective Oxide Film) 9 Source / Drain region (second conductivity type high concentration source /
Drain region) 9a P type low concentration region (second conductivity type low concentration region) 10 Interlayer insulating film 11 Metal wiring

Claims (2)

(57) [Claims] 1. (a) A resist film is used to form at least one pair of gate electrodes on a semiconductor substrate, and the first conductivity type low concentration region is provided only in the vicinity of one of the pair of gate electrodes. So that the other gate electrode is used as a mask, oblique ion implantation is performed. At that time, the total film thickness t of the gate electrode and the resist film, the distance s between the gate electrodes, and the first conductivity type low concentration region The width d from the end of the gate electrode and the inclination angle θ from the surface of the semiconductor substrate are set so as to satisfy the following expression tan θ = t / (s−d), and the entire surface of the obtained semiconductor substrate is protected by injection treatment by oxidation. An oxide film is formed, and (b) second conductivity type impurities are ion-implanted through the implantation protection oxide film from a direction perpendicular to the semiconductor substrate, and the first conductivity type low concentration region is formed into the second conductivity type. Convert to mold low concentration area Together, by forming a second conductivity type high concentration source / drain regions, the method of manufacturing a semiconductor device comprises forming a semiconductor device of the asymmetrical LDD structure having a second conductivity type low concentration region only the drain region end. 2. A semiconductor device having an asymmetrical LDD structure formed by the method according to claim 1.