JP2001006287A - Digital signal reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal reproducing device which converges fast and surely reproduce recorded information of a recording medium. SOLUTION: An error computing element 15 selects an effective component of re-sampling data, and makes an internal digital low-pass filter integrate the component and outputs is as a DC drift component only when 0-point information from re-sampling DPLL(digital phase synchronous loop) 14 is '1' (at this time, a timing is shown when a sampling point formed by re-sampling exists). The output of an error computing element 15, a DC offset output component, are inputted to a subtracter circuit 13, and subtracted from the output signal of an AGC(automatic gain control)-ATC(automatic threshold control) circuit 12. Thus, the DC component can be eliminated from the output of the AGC-ATC circuit 12 through the subtracter circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus, and more particularly to a digital signal reproducing apparatus which resamples a run length limited code reproduced from a recording medium such as an optical disk at a desired bit rate to generate resampled data. The present invention relates to a digital signal reproducing apparatus including a resampling operation phase locked loop circuit for outputting to an equalizer.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram showing an example of a conventional digital signal reproducing apparatus. In the figure, a digital signal obtained by digitally modulating an information signal recorded on a recording medium 51 such as an optical disk is reproduced by reproducing means (not shown), pre-amplified by a pre-amplifier 52,
After the direct current component (DC component) is blocked by the ATC circuit 53 and sampled by an A / D converter (not shown),
Automatic gain control (AG
C). The PLL circuit 55 generates digital data obtained by resampling the input signal input from the AGC circuit 54 at a desired bit rate, and supplies the digital data to an adaptive equalizer (crosstalk canceller (CTC)) 56.

An adaptive equalizer 56 gives a partial response (PR) characteristic to an input signal, for example,
Perform waveform equalization. The output signal of the adaptive equalizer 56 is supplied to a decoding circuit 57, where the output signal is subjected to, for example, a known Viterbi decoding, and then supplied to an ECC circuit 58, where the error correction code of the decoded data sequence is used. A code error of the generation element is corrected, and decoded data with reduced errors is output.

[0004]

SUMMARY OF THE INVENTION However, FIG.
In the conventional digital signal reproducing device shown in FIG. 2, when the recording medium 51 is an optical disk, the reproduced signal does not match the central level 62 of the maximum amplitude and the central level 63 of the minimum inversion interval as indicated by 61 in FIG. In such a case of a reproduced signal waveform, the ATC circuit 53 simply performs control such that the central level of the maximum amplitude is set to 0 level. ,
The zero level cannot be set at the center of the signal level of the minimum inversion interval that should be the original zero level. In this case, the error rate becomes worse, and it becomes an obstacle to high-density recording.

[0005] The present invention has been made in view of the above points,
It is an object of the present invention to provide a digital signal reproducing apparatus that can quickly and reliably reproduce recorded information on a recording medium.

It is another object of the present invention to provide a digital signal reproducing apparatus capable of accurately reproducing information recorded on a recording medium on which high-density recording has been performed by using partial response equalization.

[0007]

According to a first aspect of the present invention, a run-length limited code is reproduced from a reproduced signal, and a reproduced signal obtained by reproducing the run-length restricted code is subjected to partial response equalization. In a digital signal reproducing apparatus for post-decoding, an A / D converter for converting a run-length limited code into a digital reproduced signal, and a re-sampling operation of the digital reproduced signal output from the A / D converter at a desired bit rate. A resampling operation phase locked loop circuit for generating resampling data and outputting it to the equalizer, generating a bit clock, detecting zero crossings of the resampling data and outputting zero point information, and a resampling operation phase locked loop The signal resampled by the circuit is input to the first input terminal, Zero point information indicating the timing at which a sample point formed by resampling, which corresponds to a zero crossing point to be locked by the pulling operation phase locked loop circuit, is input to the second input terminal, and input to the second input terminal An error calculator that integrates only the effective component of the input signal of the first input terminal according to the signal timing and outputs the integrated value as DC offset information; and a digital reproduction signal output from the A / D converter. And a subtraction circuit that generates a difference signal from the DC offset information output from the error calculator and inputs the signal to the resampling calculation phase locked loop circuit.

In the first aspect of the invention, the zero point information indicating the timing at which the sample point formed by the resampling, which corresponds to the zero crossing point to be locked by the resampling calculation phase locked loop circuit, exists by the error calculator. Only the effective component of the resampling data output from the resampling operation phase locked loop circuit according to the timing is integrated, and the integrated value is subtracted from the digital reproduction signal output from the A / D converter as DC offset information. As a result of this subtraction, A
DC in the digital reproduction signal output from the / D converter
The offset component can be removed and input to the resampling operation phase locked loop circuit.

According to a second aspect of the present invention, in order to achieve the above object, the subtraction circuit is replaced with a resampling operation and a resampling data output from a phase locked loop circuit in place of the subtraction circuit in the first invention. A difference signal from the DC offset information output from the mixer is generated and input to the equalizer.

[0010] In the second aspect, the error calculator calculates the zero point information indicating the timing at which the sample point formed by the resampling, which corresponds to the zero cross point to be locked by the resampling calculation phase locked loop circuit, exists. Resampling operation according to timing Only the effective component of the output resampling data of the phase locked loop circuit is integrated, and the integrated value is subtracted from the resampling data as DC offset information. D in the resampling data output from the phase locked loop circuit
The C offset component can be removed and input to the equalizer.

[0011] In order to achieve the above object, a third aspect of the present invention provides a method according to the third aspect, wherein the 0 point information input to the error calculator is:
The resampling operation is a signal indicating not only a sample point formed by resampling but also a sample point before and after the sample point corresponding to a zero cross point to be locked by the phase locked loop circuit. Is based on the timing of the sample point and the sample points before and after it.
It is characterized in that only the effective component of the resampling data output from the resampling operation phase locked loop circuit is integrated, and the integrated value is output as DC offset information.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a digital signal reproducing apparatus according to a first embodiment of the present invention.
In FIG. 1, a signal reproduced from an optical disk by a known optical head is supplied to an A / D converter 11, where it is sampled by a master clock and converted into a digital signal. , Where the amplitude is controlled to be constant.
C) and the threshold value of the binary comparator is appropriately set to direct current (DC)
Automatic threshold control (ATC) is performed.

The output signal of the AGC / ATC circuit 12 is supplied to a resampling DPLL 1
4 is supplied. The resampling DPLL 14 is a digital PLL (phase locked loop) circuit in which a loop is completed in its own block. The resampling data is generated by resampling (decimating interpolation) an input signal at a desired bit rate. (That is, 180 ° resampling data out of 0 ° and 180 ° phases of the resampling data) is supplied to the transversal filter and the error calculator 15 in the equalizer 16, respectively.

The resampling DPLL 14 detects a zero crossing of the resampling data having a phase of 0 °, and supplies the obtained zero point information to the tap delay circuit in the equalizer 16 and the error calculator 15, respectively. The zero point information indicates the point at which the bit sampling data crosses the zero level in bit clock units. Further, the resampling DPLL 14 locks the resampling timing, that is, the frequency, based on the value of the resampling data with a phase of 180 ° corresponding to the zero cross point indicated by the zero point information, so that it becomes zero.

The resampling DPLL 14 is configured, for example, as shown in the block diagram of FIG. In the figure, an interpolator 141 receives an input digital signal from the subtraction circuit 13 of FIG. 1 and a signal from a timing generator 144, which will be described later, as input signals, and outputs data point phase information and bit information input from the timing generator 144. The data value of the phase point data is estimated from the clock by interpolation and output.
The output data value of the interpolator 141 is supplied to the phase detector 142.

The phase detector 142 converts the input data value, that is, the resampling data having a phase of 0 ° into a phase of 180 °.
Generates and outputs the resampling data. For example,
By operation on 1-bit data before D _t-1 and the data D _t at the current time to _{(D t-1 + D t} ) / 2, the phase 18
0 ° resampling data is obtained.

Further, the phase detector 142 receives an input data value,
In other words, the zero-cross point is detected from the sampling data of the phase 0 °, and is output as a phase error using the data value at the zero-cross point. For example, data D _t−1 one bit before
To detect the zero-crossing point from the data D _t at the moment and,
By multiplying the polarity of D _t-1 the _{(D t-1 + D t} ) / 2, the phase error is obtained. Conventionally, only the phase error is output from the phase detector, but in this embodiment, zero point information indicating a zero crossing point is also output from the phase detector. This 0 point information
This shows the timing at which the above-mentioned 180 ° phase sample point, which corresponds to the zero-cross point to be locked by the resampling DPLL 14, is shown.

The output phase error signal of the phase detector 142 is
After being integrated by the loop filter 143, it is supplied to the timing generator 144, where the next data point phase of the output of the loop filter 143 is estimated, and the data point phase information and the similarly generated bit clock are output. Interpolator 1
41.

Referring back to FIG. 1, the error calculator 15 extracts only DC offset information from the output signal of the resampling DPLL 14 based on the 0-point information, and integrates the extracted data as a DC shift component. It is supplied to the subtraction circuit 13. The subtraction circuit 13 removes the DC component from the output signal of the AGC / ATC circuit 12 and supplies the signal to the resampling DPLL 14. Resampling DPLL1
4 supplies to the equalizer 16 resampling data generated by performing resampling (decimation interpolation) on the input signal from the subtraction circuit 13 at a desired bit rate.

FIG. 3 is a block diagram showing a first embodiment of the error calculator 15. In FIG.
0 is the resampling DPLL1 input to the terminal 30a.
4 and the 0 generator 31 input to the terminal 30b
And the fixed 0 point information from the resampling DPLL 14 is "1".
(In this case, a zero cross point is indicated, indicating a timing at which a sample point formed by resampling exists), and an effective component of the output signal of the resampling DPLL 14 input to the terminal 30a is selected. Is supplied to a digital low-pass filter (LPF) 32 comprising an adder 33 and a latch circuit 34, where it is integrated and output as a DC shift component (DC offset component).

When the 0 point information is "0", the switch circuit 30 outputs the 0 generator 3 input to the terminal 30b.
A fixed value 0 from 1 is selected and input to the LPF 32. At this time, the output of the LPF 32 is held at the previous value.

As described above, in this embodiment, as shown in FIG. 4, among the output signals of the resampling DPLL 14, the information corresponding to the zero cross samples indicated by the open circles of the reproduced digital signal I input to the resampling DPLL 14. Is integrated by the LPF 32 and can be regarded as a DC shift component.
The output signal of the C / ATC circuit 12 is subtracted. Thus, the DC component can be removed from the output signal of the AGC / ATC circuit 12 from the subtraction circuit 13.

Returning to FIG. 1, the output signal of the resampling DPLL 14 is supplied to an equalizer 16 where a partial response (PR) characteristic is added and the waveform is equalized. (Not shown) for Viterbi decoding. The circuit configuration of this Viterbi decoding is known. For example, a branch metric operation circuit that calculates a branch metric from a sample value of a reproduced waveform after equalization, and a path metric is calculated by cumulatively adding the branch metric every clock. It comprises a path metric calculation circuit and a path memory for storing a signal for selecting the most probable data sequence with the smallest path metric. The path memory stores a plurality of candidate sequences, and outputs a candidate sequence selected according to a selection signal from the path metric operation circuit as a decoded data sequence.

FIG. 5 is a block diagram of the error calculator 15 according to a second embodiment. 3, the same components as those of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. The error calculator 15 sets the switch circuit 30 to a resampling DPL.
It is characterized in that switching is performed based on the result of the logical OR operation of the three pieces of adjacent 0-point information from L14. That is, when at least one of the three 0-point information of three consecutive clock cycles is "1", they are, as shown in FIG. 6, the zero-cross of the reproduced digital signal II input to the resampling DPLL 14 and the zero cross. When the LPF 32 integrates only the three sample values in the vicinity and corresponding to the zero-cross sample indicated by the white circle and the samples indicated by the white triangle before and after the zero-cross sample, these are regarded as DC shift components, and are output.

In FIG. 5, the resampling DPLL 1
The zero point information from 4 is supplied to the OR circuit 40 after being delayed by one sample clock by the two cascaded latch circuits 38 and 39, and is also directly supplied to the OR circuit 40. Therefore, the OR circuit 40 outputs "1" only when at least one of the three consecutive zero point information is "1", and the switch circuit 30 outputs the effective component of the error information input to the terminal 30a. Is supplied to the LPF 32, where it is integrated and output as a DC shift component (DC offset component) to the subtraction circuit 13 in FIG.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram showing a second embodiment of the digital signal reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In the embodiment shown in FIG.
In the embodiment in which the offset information is fed back to the input side of the resampling DPLL 14, the embodiment in FIG. 7 subtracts the output DC offset component of the error calculator 18 from the signal on the output side of the resampling DPLL 14. The circuit 19 performs feedforward control for obtaining a difference.

That is, the output signal of the resampling DPLL 14 and the zero point information are supplied to the error calculator 18. The error calculator 18 has the configuration shown in FIG. 3 or FIG.
Only the necessary DC offset information is extracted from the output signal of the LL 14 based on the 0 point information, and the result of integration is supplied to the subtraction circuit 19 as a DC shift component. The subtraction circuit 19 subtracts the output DC offset information of the error calculator 18 from the output signal of the resampling DPLL 14. As a result, a DC shift or a DC
It is possible to obtain a signal in which a DC error component such as fluctuation is greatly reduced.

Next, the data waveform of the first embodiment will be described. FIG. 8 and FIG. 9 show that a signal having a DC offset and a swing is resampled by the DPLL1.
4 and the eye pattern of the data when the DC error component is not reduced by the error calculator 15,
The vertical axis is the level, the horizontal axis is the time axis, and the arrow attached to the vertical axis indicates the original 0 level.

FIG. 8 shows that the output signal of the resampling DPLL 14 is sliced at the absolute zero level of the circuit.
An eye pattern of resampling data having a phase of 0 ° for discriminating between 1 ”and“ 0 ”, FIG.
3 shows eye patterns of an output signal of the resampling DPLL 14, which is resampling data having a phase of 180 ° for waveform equalization.

As can be seen from FIGS. 8 and 9, these data are clearly offset in level, and the DC fluctuations present in the input signal are also left out. As a result, in the case of the data in FIG. However, if the slice discrimination is simply performed at the 0 level (+ polarity is 1, and-polarity is 0), many data will cause a discrimination error. In such a state, no matter how much the Viterbi decoder is used in the subsequent stage, the error cannot be eliminated (particularly, Viterbi decoding is vulnerable to DC deviation).

On the other hand, the eye pattern of data when a signal having a DC offset and fluctuation is actually input to the resampling DPLL 14 and the DC component is reduced by the error calculator 15 is shown in FIGS. 11. FIG. 10 shows the output signal of the resampling DPLL 14 sliced at the absolute 0 level of the circuit.
FIG. 11 shows an output signal of the resampling DPLL 14 which is 180 ° phase resampling data for waveform equalization by the equalizer 16 for the phase 0 ° resampling data for discriminating between 1 ”and“ 0 ”. The eye patterns are shown.

As can be seen from FIGS. 10 and 11, these data are compared with FIGS.
Both the shifts are greatly reduced, and as can be seen from FIG. 10, it can be seen that correct values can be determined even with a simple 0-level slice. Also, it can be seen that the sample corresponding to the zero crossing point from FIG. 11 is correctly controlled to the 0 level. In this state, the Viterbi decoding circuit at the subsequent stage can exhibit a higher error rate reduction effect closer to the theoretical value.

The present invention is not limited to the above-described embodiment. For example, the present invention is applicable not only to recording media such as optical discs, but also to transmission of non-DC-free signals that cause band limitation. .

[0034]

As described above, according to the present invention,
The resampling operation phase synchronization according to the timing of 0 point information indicating the timing at which the sample point formed by the resampling exists, which corresponds to the zero cross point to be locked by the resampling operation phase locked loop circuit by the error operation unit. Only the effective component of the output resampling data of the loop circuit is integrated, and the integrated value is used as DC offset information as a digital reproduction signal output from an A / D converter or output resampling data of a resampling operation phase locked loop circuit. The DC offset component is removed by subtracting from the above, so even if the input signal waveform is vertically asymmetric, there is no function to control the DC component in the resampling operation phase locked loop circuit or the equalizer in the subsequent stage. ,
In addition, automatic threshold control (AT
C) The DC component of the input signal, the output signal of the resampling operation phase locked loop circuit or the output signal of the equalizer, which remains due to slow response and lack of accuracy in the device, can be largely removed. In the subsequent Viterbi decoding circuit, a high error rate reduction effect close to the theoretical value can be exhibited.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the device of the present invention.

FIG. 2 is a block diagram illustrating an example of a resampling DPLL.

FIG. 3 is a block diagram of an error calculator according to a first embodiment;

FIG. 4 is an operation explanatory diagram of FIG. 3;

FIG. 5 is a block diagram of an error calculator according to a second embodiment;

FIG. 6 is an operation explanatory diagram of FIG. 5;

FIG. 7 is a block diagram of a second embodiment of the device of the present invention.

8 is a diagram illustrating an example of an eye pattern of an output signal of the resampling DPLL circuit in FIG. 1 when DC cancellation is not performed.

9 is a diagram illustrating another example of the eye pattern of the output signal of the resampling DPLL circuit in FIG. 1 when DC cancellation is not performed.

FIG. 10 is a diagram illustrating an example of an eye pattern of an output signal of the resampling DPLL circuit in FIG. 1 when an error calculator is used.

11 is a diagram showing another example of the eye pattern of the output signal of the resampling DPLL circuit in FIG. 1 when an error calculator is used.

FIG. 12 is a block diagram of an example of a general digital signal reproducing device.

FIG. 13 is a diagram showing an example of a vertically asymmetric reproduced signal waveform.

[Explanation of symbols]

 Reference Signs List 11 A / D converter 12 AGC / ATC circuit 13, 19 Subtraction circuit 14 Resampling DPLL circuit 15, 18 Error calculator 16 Equalizer 30 Switch circuit 32 Digital low-pass filter (LPF) 34, 38, 39 Latch circuit 40 OR circuit 141 Interpolator 142 Phase detector 143 Loop filter 144 Timing generator

Claims (3)

[Claims] 1. A digital signal reproducing apparatus for reproducing a run-length limited code from a reproduced signal, performing partial response equalization on a reproduced signal obtained by reproducing the run-length restricted code, and then decoding the reproduced signal. An A / D converter for converting the digital reproduced signal output from the A / D converter into a signal, generating resampling data by performing a resampling operation at a desired bit rate, and outputting the resampled data to an equalizer; A resampling operation phase locked loop circuit for generating a clock and detecting zero crossings of the resampling data and outputting zero point information; and a signal resampled by the resampling operation phase locked loop circuit is supplied to a first input terminal. Is input to the The zero point information indicating the timing at which a sample point formed by resampling corresponding to the zero crossing point to be locked by the loop circuit is input to a second input terminal, and the input signal of the second input terminal is input. An error calculator that integrates only the effective component of the input signal of the first input terminal according to the timing and outputs the integrated value as DC offset information; and the digital reproduction output from the A / D converter. A digital signal reproducing apparatus, comprising: a subtraction circuit that generates a difference signal between a signal and the DC offset information output from the error calculator and inputs the signal to the resampling calculation phase locked loop circuit. 2. A digital signal reproducing apparatus for reproducing a run-length limited code from a reproduced signal, performing partial response equalization on a reproduced signal obtained by reproducing the run-length restricted code, and then decoding the reproduced signal. An A / D converter for converting the digital reproduced signal output from the A / D converter into a signal, generating resampling data by performing a resampling operation at a desired bit rate, and outputting the resampled data; A resampling operation phase locked loop circuit for generating and further detecting zero crossings of the resampling data and outputting zero point information; and a signal resampled by the resampling operation phase locked loop circuit is supplied to a first input terminal. And the resampling operation phase locked loop circuit is locked. The zero point information indicating the timing at which a sample point formed by resampling corresponding to a zero crossing point to be clicked is input to a second input terminal, and the zero point information is input in accordance with the timing of an input signal of the second input terminal. An error calculator that integrates only the effective component of the input signal of the first input terminal and outputs the integrated value as DC offset information; and the resampling data output from the resampling calculation phase locked loop circuit. And a subtraction circuit for generating a difference signal between the DC offset information output from the error calculator and inputting the signal to the equalizer. 3. The zero point information input to the error calculator includes not only a sample point formed by resampling corresponding to a zero crossing point to be locked by the resampling calculation phase locked loop circuit, but also the zero point information. A signal indicating the timing at which sample points before and after the sample point are present, wherein the error calculator calculates the output resampling of the resampling calculation phase locked loop circuit according to the timing of the sample point and the sample points before and after the sample point. 3. The digital signal reproducing apparatus according to claim 1, wherein only the effective component of the data is integrated, and the integrated value is output as DC offset information.