JP3818031B2 - Recorded information playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a recorded information reproducing apparatus, and more particularly to a recorded information reproducing apparatus that reproduces a recorded information signal of an optical disc.
[0002]
[Prior art]
Conventionally, on the basis of signals reproduced by separate beams from three adjacent recording tracks of an optical disc on which high density recording has been performed, crosstalk removal is performed and a reproduction signal having a good S / N ratio is obtained from the central track. Various recording information reproducing apparatuses using the three-beam method have been proposed, but the recording capacity is reduced by removing the crosstalk of the reproduced signal without recording the preamble signal for removing the crosstalk in advance. An improved recorded information reproducing apparatus using a three-beam method is known (Japanese Patent Laid-Open No. 9-320200).
[0003]
In the conventional recorded information reproducing apparatus, the first read signal reproduced from one arbitrary recording track of the optical disk by one beam and the two adjacent tracks on both sides of the one track are reproduced by separate beams. The two second read signals are sampled and converted into first and second sample value series, and a crosstalk component is obtained from the second sample value series by a variable coefficient filter, and the above-described first The crosstalk component is subtracted from the sample value series by a subtractor, and further, the zero cross sample value is extracted from the output sample value series of the subtractor by the zero cross sample extracting means so that the zero cross sample value converges to zero. The filter coefficient of the variable coefficient filter is updated by the filter coefficient calculation means, and subtracted by the determination means. Is the output sample value series configuration for judging the reproduced signal.
[0004]
[Problems to be solved by the invention]
However, in the above-described conventional recorded information reproducing apparatus, the error signal is set to 0 using the LMS adaptive algorithm for updating the filter coefficient of the variable coefficient filter. However, the error signal is output from the subtractor. Only the zero-cross sample values extracted from the sample value series have a problem that convergence is slow and misjudgment is often caused. In addition, since partial response equalization is not performed, there is a problem that the Viterbi decoding cannot be performed, and there is a high possibility of erroneous data restoration of a reproduction signal with a low S / N read from an optical disc that tends to be recorded at higher density. is there.
[0005]
In addition, when the reproduction signal is a signal read from the optical disk by TPP (tangential push-pull method) or has a differential characteristic such as a hard disk and a magnetic tape, the signal is close to 0 as shown in FIG. Since it takes continuous values, the data change point cannot be detected by the zero cross detection. That is, it is impossible to extract crosstalk components, and crosstalk removal has not been realized.
[0006]
The present invention has been made in view of the above points, and an object of the present invention is to provide a recorded information reproducing apparatus that can realize crosstalk removal for differential signals. Another object of the present invention is to provide a recorded information reproducing apparatus that can quickly and reliably reproduce recorded information on a recording medium.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a recorded information reproducing apparatus for decoding a first reproduced signal read from an arbitrary recording track to be reproduced recorded on a recording medium, wherein the first information A signal obtained by subtracting, from a reproduction signal, a signal obtained by subtracting a signal obtained by processing a second reproduction signal read from at least one recording track adjacent to any one recording track to be reproduced by a filter having a predetermined filtering characteristic is output. 1 subtracting means, detecting means for detecting whether or not the first reproduction signal is a peak and outputting peak point information; receiving the peak point information and an output signal of the first subtracting means; A second subtraction that outputs a difference value between the output signal from the first subtraction means and a predetermined value at a timing when the peak point information indicates a peak as an error signal. And means, based on said error signal, to provide a recording information reproducing apparatus filtering characteristic the error signal of said filter and having a coefficient generating means for variably controlled to be minimized.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a recorded information reproducing apparatus according to the present invention. In this embodiment, a known three-beam method is used in which three beam spots are separately formed for three adjacent recording tracks (hereinafter sometimes simply referred to as tracks) of an optical disc as an example of a recording medium. . That is, as shown in FIG. 3, when a recorded information signal is reproduced from an arbitrary track Ti of an optical disk on which one track is formed per rotation, a reproduction-specific light beam spot B0 is formed on the track Ti. Of the tracks Ti-1 and Ti + 1 adjacent to both sides of the track Ti, a beam spot B1 is formed on the inner track Ti-1 and a beam spot B2 is formed on the outer track Ti + 1.
[0009]
These three beam spots B0, B1, and B2 are centered on the center beam spot B0, the beam spot B1 is at the rear position (or front position), and the beam spot B2 is at the front position (or rear position) in the rotation direction of the optical disc. As is well known, tracking is performed while maintaining the state of the Reflected light from these three beam spots B0, B1, and B2 is converted into a read signal through a known optical system separately.
[0010]
Of the above read signals, the read signal of the track Ti to be reproduced at the center is supplied to the A / D converter 11 of FIG. 1, and the read signal of the adjacent track Ti-1 on the inner peripheral side is A in FIG. The read signal of the adjacent track Ti + 1 on the outer peripheral side is supplied to the A / D converter 13 of FIG. The A / D converters 11, 12, and 13 sample the input read signal with a master clock, convert it into a digital signal, and supply it to the AGC / ATC circuits 14, 15, and 16 of the next stage, where the amplitude is Automatic amplitude control (AGC) in which is controlled to be constant, and automatic threshold control (ATC) in which direct current (DC) control is appropriately performed for the threshold of binary comparison.
[0011]
The output signal of the AGC / ATC circuit 14 is supplied to the resampling DPLL 17. The resampling DPLL 17 is a digital PLL (phase locked loop) circuit in which a loop is completed in its own block, and performs resampling (decimation interpolation) on digital data sampled at a desired bit rate with respect to an input signal. And is supplied to the transversal filter 21 through the delay adjuster 20. The resampling DPLL 17 detects the peak of the resampling data, and supplies the peak point information obtained thereby to the tap delay circuit 32 described later through the delay adjuster 22.
[0012]
Further, the resampling DPLL 17 generates a bit clock BCLK for bit sampling, generates a parameter T_ratio indicating an internal division ratio for the resampling operation, and supplies them to the resampling circuits 18 and 19, respectively. Here, the digital signals from the AGC / ATC circuits 15 and 16 are resampled by the bit clock BCLK at the ratio indicated by the parameter T_ratio. The bit clock BCLK is a missing clock (Punctured Clock). The peak point information indicates a positive or negative peak level in bit sampling data in bit clock units.
[0013]
The signals extracted from the resampling circuits 18 and 19 are supplied to transversal filters 25 and 26 through delay adjusters 23 and 24, respectively. The transversal filter 21 and the transversal filters 25 and 26 receive filter coefficients (tap coefficients) from multiplier / low-pass filters (LPF) 27, 28, and 29, respectively, and perform filtering processing with characteristics corresponding thereto. Perform for input signal.
[0014]
The transversal filter 21 performs waveform equalization processing based on the tap coefficient (filter coefficient) from the multiplier / LPF 27, and affects the influence of intersymbol interference with signals before and after the read signal from the desired track to be reproduced. To reduce. The output signal after equalization of the output waveform of the transversal filter 21 is supplied to a provisional discrimination circuit 33 through subtractors 30 and 31, which will be described later. Here, the delay signal from the tap delay circuit 32 and the type of partial response (PR) And a RLL mode signal indicating a run-length limited code length (minimum inversion interval or maximum inversion interval) of a signal recorded on the optical disc, and a temporary determination result is output based on these.
[0015]
The provisional discrimination result and the input signal of the provisional discrimination circuit 33 (the output signal of the subtractor 31) are subtracted by the subtracter 34, and the difference value is inverted as an error signal by the inverter 35. Then, the multiplier / LPF 27 Where the correlation is detected by multiplication with the tap output of the transversal filter 21 and integrated by the LPF. The output integrated value of the multiplier / LPF 27 is input to the transversal filter 21 as a filter coefficient (tap coefficient) of the transversal filter 21 that makes the value of the error signal 0.
[0016]
The feedback loop including the transversal filter 21, multiplier / LPF 27, provisional discrimination circuit 33, tap delay circuit 32, subtractor 34, and inverter 35 is based on the well-known LMS algorithm. The circuit proposed by the present inventor performs provisional discrimination (convergence target setting) on the premise of partial response equalization.
[0017]
Here, the partial response (PR) characteristics will be described. For example, if the characteristics of PR (a, b, -b, -a) are applied to the solitary wave shown in FIG. As is well known, the waveform is as shown in FIG. Further, in the continuous wave, this equalized waveform takes five values of-(a + b), -a, 0, a, and a + b. When these five values are input to the Viterbi decoder, the original data (input value) and the reproduction signal (output value) after PR equalization are subject to past signal constraints and input by this and (1, X) RLL. It is known that if the signal “1” does not last more than twice, it can be represented by a state transition diagram as shown in FIG.
[0018]
In FIG. 4C, S0 to S5 indicate states determined by the immediately preceding output value. From this state transition diagram, for example, when in state S2, when the input value is a + 2b, the output value becomes 1 and transitions to state S3, and when the input value is 2b, the output value becomes 1 and transitions to state S4. However, it is understood that no other input value is input, and if it is input, it is understood that it is an error.
[0019]
FIG. 4D shows a state transition diagram when the signal run length limit is (2, X), and it can be seen that there are no transitions from S5 to S1 and from S2 to S4.
[0020]
FIG. 5 is a diagram showing the relationship between the characteristics of PR (a, b, −b, −a) and the temporary determination value output from the temporary determination circuit 33. In the figure, the PR mode in the top row indicates the value of the signal input to the temporary determination circuit 33, and the RLL mode in the leftmost column indicates the signal input to the temporary determination circuit 33. Show.
[0021]
The value of the PR mode has partial response characteristics of PR (1, -1), PR (1, 1, -1, -1), PR (1, 2, -2, -1), PR (1, 3,- 3, -1), PR (2, 3, -3, -2) and PR (3,4, -4, -3). In particular, PR (1, -1) is the well-known PR4 (Partial Response Class IV), and PR (1, 1, -1, -1) is the well-known EPR4 (Extended Partial Response Class IV). .
[0022]
In FIG. 5, PR (1, −1) is a case where a = 0 and b = 1 of PR (a, b, −b, −a). Furthermore, in FIG. 5, the gain G is a multiplication coefficient for normalizing the maximum absolute value (a + b), and is represented by A / (a + b) (where A is an arbitrary level).
[0023]
The waveform equalization reproduction signal from the subtractor 31 is handled as the signal D3 at the current time. On the other hand, the peak point information from the resampling / DPLL 17 is supplied to the tap delay circuit 32 via the delay adjustment 22, and the tap delay output is input to the provisional determination circuit 33. The provisional discrimination circuit 33 performs provisional discrimination (convergence target setting) based on partial response equalization according to an algorithm described later.
[0024]
Next, the operation of the provisional determination circuit 33 will be described in more detail with reference to the flowchart of FIG. Here, for the sake of simplicity, the case where the signal run length limit is (2, X) will be described. Here, when the value PK of the peak point information is “1”, it indicates a peak, which is the state of PR (a, b, −b, −a) shown in FIG. In the transition diagram, it is represented by the value “a + b” or “− (a + b)”, and occurs in the process of transition from state S1 to S2 or state S4 to S5.
[0025]
In this case, in FIG. 4C, the polarity of the peak can be determined by the polarity of the sample point. In addition, if the interval from one peak to the next peak is known, that is, the number of transitions from state S2 to state S5, or from state S5 to state S2, the path is determined and a value that can be taken. Becomes clear for each sample point.
[0026]
In the state transition diagram, when the value is not “a + b” or “− (a + b)”, that is, when it is not a peak, the value PK of the peak point information is “0”. From this state transition diagram, two peaks (PK = 1) are not extracted continuously. In the case of (2, X), there are at least two “0” s between adjacent PK = 1. To do.
[0027]
In the actual signal, it is fully expected that the detection of the peak itself will be erroneous due to the influence of noise, etc., but in the case of feedback control, if the probability of correct determination exceeds the probability of error, it will converge in the correct direction. In addition, it is considered that there is no practical problem with single noise because of sufficient integration processing.
[0028]
Paying attention to the above points, the temporary discrimination circuit 33 first identifies the value PK of the peak point information inputted for each cycle of the bit clock via the tap delay circuit 32, and has five values of five consecutive clock cycles. Is all “0” (step 61 in FIG. 6), only the last value among the above five values is “1” (step 62 in FIG. 6), out of the above five values Whether only the first value is “1” (step 63 in FIG. 6), the first and last values of the above five values are “1”, and the remaining three values are “0”. (Step 64 in FIG. 6).
[0029]
In these patterns, when the central value of the peak point information value PK of interest is “0”, the peak point information values PK on both the front and rear sides are both “0”. Since it is a case of sticking to the waveform 0, when satisfying any of these patterns,
Q = 0 (1)
The provisional discrimination value Q is calculated by the following formula (step 65 in FIG. 6).
[0030]
If none of the above patterns, the value PK of the five peak point information of five consecutive clock cycles is one of “01010”, “01001”, “10010”, “00010”, and “01000”. Whether it is a pattern or not is discriminated (steps 66 and 69 to 72 in FIG. 6). In these four patterns, the median value of the continuous five peak point information does not indicate the peak point, and any one of the two adjacent peak point information before and after the median value indicates the peak point. Is the time.
[0031]
If any of the above five patterns
P = a × G (2)
The value P is calculated by the following equation (step 73 in FIG. 6). In the equation (2) and the later-described equation (3), G represents the gain shown in FIG. 5, and a and b represent the values of a and b in PR (a, b, b, a). The values of a, b and G are known values obtained from the PR mode signal input via the terminal 43 and the RLL mode signal input via the terminal 44.
[0032]
When it is determined in step 72 that the peak point information value PK is other than the above,
P = (a + b) × G (2)
The value P is calculated by the following formula (step 77 in FIG. 6). For example, the case where the median value of five consecutive peaks PK is “1” corresponds to this case.
[0033]
When the value P is calculated in any of the above steps 73 and 77, it is determined whether or not the waveform equalization signal D3 at the current time taken out from the D-type flip-flop 47 is 0 or more (step 74 in FIG. 6). . When the waveform equalization signal D3 at the current time is 0 or more, the final provisional determination level Q is a value of P (step 75 in FIG. 6), and when it is negative, the final provisional determination level Q is a value of −P. (Step 76 in FIG. 6)
[0034]
The provisional judgment level Q obtained by the above provisional judgment processing is supplied to the subtracter 34 in FIG. 1 to obtain a difference from the waveform equalization signal D3 at the current time to be an error signal, which is multiplied through the INV 35. Output to the filter / LPF 27, the high frequency component is removed after multiplication, and output to the transversal filter 21 as a tap coefficient. In this way, the tap coefficient of the transversal filter 21 is variably controlled so that the error signal extracted from the subtractor 52 in FIG. It can be suitably performed by enlarging.
[0035]
As described above, the provisional determination circuit 33 includes the PR mode signal indicating the type of partial response equalization, the RLL mode signal indicating the type of run-length limit code of the reproduction signal, and the plurality of peak point information from the tap delay circuit 32. And the output signal after equalization output from the subtracter 31 are received as inputs, and the waveform equalization signal is temporarily determined based on the state transition determined by the PR mode signal and the RLL mode signal and a plurality of peak point information patterns. Level Q is calculated. The provisional determination level Q is supplied as a target value to the subtractor 34 in FIG. 1, and is taken as an error signal by taking the difference from the waveform equalized reproduction signal which is an actual signal.
[0036]
On the other hand, the signals extracted from the resampling circuits 18 and 19 shown in FIG. 1 are given fixed delays by the delay adjusters 23 and 24, and are roughly time-matched with a pseudo crosstalk to be described later. 25 and 26. The multipliers and LPFs 28 and 29 for supplying tap coefficients (filter coefficients) to the transversal filters 25 and 26 receive the error signal output from the subtractor 34. Here, the tap outputs of the transversal filters 25 and 26 are input. And the correlation value of the adjacent track signal is extracted, and the correlation value is integrated by the LPF and input to the transversal filters 25 and 26.
[0037]
In this way, the tap coefficients (filter coefficients) of the transversal filters 25 and 26 are updated in accordance with the correlation value of the adjacent track signal, and from the transversal filters 25 and 26, from the inner and outer tracks. A pseudo crosstalk signal corresponding to the read signal is extracted. The pseudo crosstalk signals output from the transversal filters 25 and 26 are subtracted by subtracters 30 and 31 from the reproduced signals from the track to be reproduced after waveform equalization from the transversal filter 21, respectively. As a result, the subtracter 31 cancels out the crosstalk in the reproduction signal of the track to be reproduced after the waveform equalization from the transversal filter 21 and outputs it as a reproduction signal having a good S / N. Since this embodiment is a feedback process, a stable operation can be realized.
[0038]
In this embodiment, the intersymbol interference removal block of the reproduction signal of the track to be reproduced including the transversal filter 21 and the pseudo crosstalk generation block based on the reproduction signal from the adjacent track including the transversal filters 25 and 26 are included. In any case, since each tap coefficient (filter coefficient) is controlled so that the same error signal is set to 0, a control conflict does not occur.
[0039]
In addition, the crosstalk component can be clearly identified when the playback signal of the desired track is flat (a state where the inversion interval is large), that is, when it is continuous near zero. In contrast, in this embodiment, the value converges toward a clear value such as 0 or a + b, and at the same time, an error from these values is used as an error signal to correlate with the adjacent track signal, and the cross Since the talk component is extracted, accurate and quick convergence is possible. That is, the feature is that an error signal can be extracted not only from zero crossing and peak point but also from information of all sampling points corresponding to partial response equalization.
[0040]
When the resampling DPLL 17 is used, the sampling clock used for the A / D converter 11 is not synchronized with the bit clock, and the same applies to the sampling clock of the reproduction signal of the adjacent track. A constant phase shift can be absorbed by a pseudo crosstalk generator (transversal filters 25 and 26 themselves can be regarded as a resampling calculator). However, when the frequency is shifted, the sampling time interval is constant. Therefore, the conventional pseudo crosstalk generator cannot cope with it.
[0041]
On the other hand, in this embodiment, using the internal ratio T_ratio at the time of the resampling calculation and the bit clock BCLK generated by the resampling DPLL 17, the resampling units 18 and 19 perform the resampling calculation of the reproduction signal from the adjacent track. Since this is done, it is possible to cope with a frequency shift. The phase is roughly adjusted by the delay adjusters 23 and 24 in the subsequent stage, and the rest is left to a pseudo crosstalk generator using the transversal filters 25 and 26. Thereby, the resampling DPLL 17 can be used. The reason why the delay adjusters 23 and 24 are arranged at the subsequent stage of the resampling units 18 and 19 is that this can reduce the number of stages of the delay flip-flops. You may arrange.
[0042]
The resampling DPLL 17 is sandwiched independently between the AGC / ATC circuit 14 and the intersymbol interference cancellation block of the reproduction signal of the track to be reproduced, including the transversal filter 21, and the loop is completed in its own block. Therefore, reliable convergence can be expected. On the other hand, when the resampling DPLL 17 is not used, an external voltage-controlled oscillator (VCO) is required, and bit sampling is performed by the A / D converter. Therefore, a PLL loop including the A / D converter The cost is increased because a high-speed A / D converter is required.
[0043]
Further, when the resampling DPLL 17 is not used, a PLL loop including an AGC / ATC circuit is formed. Therefore, there is a case where each of them interferes and cannot converge in an appropriate direction. Further, the AGC loop, ATC loop, PLL Although it is conceivable that all the loops go out and are constituted by an analog circuit, it is necessary to add a voltage control amplifier (VCA), and it is adversely affected by the time-dependent change and component variations peculiar to the analog circuit. From the above, it is clear that the configuration using the resampling DPLL is desirable as in this embodiment. Particularly, in the optical disc, since the recording / reproducing system has a high frequency attenuation characteristic in the frequency characteristic, it is suitable for oversampling.
[0044]
Next, another embodiment of the present invention will be described. FIG. 10 shows a block diagram of a second embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as in FIG. The second embodiment of FIG. 10 is characterized in that digital pre-equalizers (PreEQ) 37 to 39 are used between the A / D converters 11 to 13 and the AGC / ATC circuits 14 to 16.
[0045]
FIG. 11 shows a block diagram of a third embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as in FIG. The third embodiment of FIG. 13 is characterized in that analog pre-equalizers (PreEQ) 41 to 43 are used on the input side of the A / D converters 11 to 13.
[0046]
FIG. 12 shows a block diagram of a fourth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as in FIG. The fourth embodiment shown in FIG. 12 is characterized in that a provisional discrimination circuit 45 that uses a fixed threshold instead of peak point information for provisional discrimination is provided. That is, the reproduction signal after waveform equalization extracted from the subtracter 31 is output to the subsequent Viterbi decoding circuit and supplied to the provisional discrimination circuit 45 where it is compared with a predetermined threshold value to detect a peak point. Then, provisional discrimination is performed from the continuous pattern series of peaks using the algorithm described above.
[0047]
After the result of provisional discrimination by the provisional discrimination circuit 45 and the input signal (output signal of the subtractor 31) of the provisional discrimination circuit 45 are subtracted by the subtractor 34, the difference value is inverted by the inverter 35 as an error signal. The filter coefficient (tap coefficient) of the transversal filter 21 that is supplied to the multiplier / LPF 27 and sets the value of the error signal to 0 is input to the transversal filter 21. In this embodiment, since the peak point information from the resampling DPLL 17 is not used, the delay adjuster 22 and the tap delay circuit 32 become unnecessary.
[0048]
FIG. 13 shows a block diagram of a fifth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as in FIG. In FIG. 13, among the three adjacent tracks in the track group formed on the optical disc, the read signal of the track Ti to be reproduced at the center is input to the voltage control amplifier (VCA) 47 and the adjacent track on the inner circumference side. The read signal of Ti-1 is input to the VCA 48, and the read signal of the adjacent track Ti + 1 on the outer peripheral side is input to the VCA 49 to control the level and DC.
[0049]
The output read signals of the VCAs 47, 48, and 49 are supplied to the A / D converters 50, 51, and 52 of the next stage, sampled by the master clock, converted into digital signals, and the fixed equalizer (EQ) 53 of the next stage. , 54 and 55, the equalizer characteristics are given, and then supplied to the AGC / ATC detection circuits 56, 57 and 58, where the amplitude is controlled to be constant and the threshold value is appropriately set to DC (DC ) A gain control signal and a DC control signal for automatic threshold control (ATC) to be controlled are generated. This gain control signal is supplied to the VCAs 47, 48, and 49 to variably control the gain. Thereby, in this embodiment, AGC and ATC can be performed together with an analog circuit.
[0050]
FIG. 14 is a block diagram showing a sixth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIGS. 1 and 13 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 16, among the three adjacent tracks in the track group formed on the optical disk, the read signal of the track Ti to be reproduced at the center is input to the analog AGC / ATC circuit 61 and the adjacent track on the inner periphery side. The read signal of Ti-1 is input to the analog AGC / ATC circuit 62, and the read signal of the adjacent track Ti + 1 on the outer peripheral side is input to the analog AGC / ATC circuit 63, and the amplitude is controlled to be constant. The
[0051]
The output read signals of the AGC / ATC circuits 61, 62, 63 are supplied to the A / D converters 50, 51, 52 of the next stage, sampled by the master clock, converted into digital signals, and A / D converters. The equalizer characteristic is given by the fixed equalizer (EQ) 53 of the next stage by 50 outputs. In this embodiment, AGC and ATC are performed only by the AGC / ATC circuits 61, 62 and 63 which are analog circuits.
[0052]
FIG. 15 is a block diagram showing a seventh embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as in FIG. The seventh embodiment of FIG. 15 is characterized in that the peak point information is extracted from the waveform equalized reproduction signal output from the subtractor 31 to the Viterbi decoder.
[0053]
That is, the waveform equalized reproduction signal extracted from the subtractor 31 is supplied to the peak detector 65, and the peak point is detected. In the peak detection, for example, when the polarity of the slope is inverted in relation to an adjacent point, information indicating the timing at which the previous sampling point exists is output as peak point information. The peak point information extracted from the peak detector 65 is input to the tap delay circuit 32. Thereby, a temporary discrimination result is obtained according to the same temporary discrimination algorithm as in FIG.
[0054]
FIG. 16 shows a block diagram of an eighth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as in FIG. The eighth embodiment shown in FIG. 16 reproduces recorded information without using the resampling DPLL 17 and the resampling circuits 18 and 19. That is, the output digital read signals of the AGC / ATC circuits 14, 15, 16 are directly supplied to the transversal filters 21, 25, 26 through the delay adjusters 20, 23, 24.
[0055]
The reproduction signal from which the crosstalk taken out from the subtractor 31 is removed and the waveform is equalized is supplied to the provisional discrimination circuit 33 and is also supplied to the peak detection / phase comparator 67 where the peak is detected. The phase of the detected peak point is compared with the phase of the bit clock from the voltage controlled oscillator (VCO) 69 to generate a phase error signal. This phase error signal is applied as a control voltage to an analog or digital voltage controlled oscillator (VCO) 69 through a loop filter 68 to variably control its output system clock frequency. The output system clock of the VCO 69 has a frequency that is a natural number multiple of the bit clock, and is applied to each block that requires a device clock.
[0056]
FIG. 17 is a block diagram showing a ninth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 19, among the three adjacent tracks in the track group formed on the optical disk, the read signal of the track Ti to be reproduced at the center is input to the analog AGC / ATC circuit 71 and the adjacent track on the inner periphery side. The read signal of Ti-1 is input to the analog AGC / ATC circuit 72, and the read signal of the adjacent track Ti + 1 on the outer periphery side is input to the analog AGC / ATC circuit 73, and the amplitude is controlled to be constant. The threshold is appropriately controlled.
[0057]
The output read signal of the AGC / ATC circuit 71 is given an equalizer characteristic by a fixed equalizer (EQ) 41 at the next stage, then supplied to the A / D converter 11, sampled by a bit clock, and converted into a digital signal. The The output read signals of the AGC / ATC circuits 72 and 73 are supplied to the A / D converters 12 and 13, sampled by the bit clock, and converted into digital signals. The output digital signals of the A / D converters 11, 12, 13 are supplied to the transversal filters 21, 25, 26 through the delay adjusters 20, 23, 24.
[0058]
Further, the output analog signal of the fixed equalizer 41 is supplied to a PLL circuit including a phase comparator 74 and loop filters 75 and 76 to be a system clock having a frequency that is a natural number multiple of the bit clock. On the other hand, the peak detector 77 uses, for example, the tap delay circuit 32 as information indicating the timing at which the previous sampling point exists when the polarity of the inclination is inverted in relation to an adjacent point. To supply. This embodiment also has the same features as the above embodiments.
[0059]
FIG. 18 shows a block diagram of a tenth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIGS. The tenth embodiment shown in FIG. 18 is configured to perform ATC / AGC only with an analog circuit and perform fixed threshold determination without using a digital VCO. In FIG. 18, the waveform equalized reproduction signal extracted from the subtractor 31 is output to the subsequent Viterbi decoding circuit, and supplied to the provisional discrimination circuit 45, where it is compared with a predetermined threshold value and has a peak. Detected and provisional discrimination is performed from the continuous pattern sequence of peak points using the algorithm described above.
[0060]
Note that the present invention is not limited to the above embodiment, and the error signal minimizes the tap coefficient of the transversal filter and the filtering characteristics based only on the signal level corresponding to the peak. You may make it variably control. FIG. 19 shows a block diagram of the eleventh embodiment in this case. In the figure, the same components as in FIG. The provisional determination circuit 100 performs determination using a fixed threshold value. The peak point information output from the delay adjustment 22 is supplied to the error selection 101 instead of the tap delay circuit. The error selection 101 extracts only the error signal corresponding to the peak timing from the error signal output from the subtractor 34 and supplies it to the multipliers / LPFs 28 and 29.
[0061]
FIG. 20 shows a block diagram of a twelfth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. The temporary discrimination circuit 102 performs discrimination using a fixed threshold value. The peak detection 103 detects a peak from the output signal output from the subtractor 31 and supplies peak point information to the error selection 104. The error selection circuit 104 extracts only the error signal corresponding to the peak timing from the error signal output from the subtractor 34 and supplies it to the multipliers / LPFs 28 and 29.
[0062]
FIG. 21 is a block diagram showing a thirteenth embodiment of recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. The temporary discrimination circuit 105 performs discrimination using a fixed threshold value. The peak point information output from the peak detector 77 is supplied to the error selection 106 instead of the tap delay circuit. The error selection unit 106 extracts only the error signal corresponding to the peak timing from the error signal output from the subtractor 34 and supplies it to the multipliers / LPFs 28 and 29.
[0063]
FIG. 22 shows a block diagram of a fourteenth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. The provisional discrimination circuit 107 performs discrimination using a fixed threshold value. The peak detection 108 detects a peak from the output signal output from the subtractor 31 and supplies peak point information to the error selection 109. The error selection circuit 109 extracts only an error signal corresponding to the peak timing from the error signal output from the subtractor 34 and supplies the error signal to the multipliers / LPFs 28 and 29.
[0064]
Note that the present invention is not limited to the above-described embodiment, and only the crosstalk removal function can be used without using partial response equalization. FIG. 23 shows a block diagram of the fifteenth embodiment in this case. In the figure, the same components as those in FIG. 19 are denoted by the same reference numerals, and the description thereof is omitted. The transversal filter, the multiplier / LPF, and the INV are deleted, and the output of the delay adjustment 20 is supplied to the subtractor 30.
[0065]
FIG. 24 is a block diagram showing a sixteenth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. The transversal filter, the multiplier / LPF, and the INV are deleted, and the output of the delay adjustment 20 is supplied to the subtractor 30.
[0066]
FIG. 25 shows a block diagram of a seventeenth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 21 are denoted by the same reference numerals, and the description thereof is omitted. The transversal filter, the multiplier / LPF, and the INV are deleted, and the output of the delay adjustment 20 is supplied to the subtractor 30.
[0067]
FIG. 26 is a block diagram showing an eighteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 22 are denoted by the same reference numerals, and the description thereof is omitted. The transversal filter, the multiplier / LPF, and the INV are deleted, and the output of the delay adjustment 20 is supplied to the subtractor 30.
[0068]
The present invention is not limited to the above embodiment. For example, the delay adjusters 20, 23 and 24 shown in FIG. 1 may be provided on the input side of the AGC / ATC circuits 14, 15 and 16. If there is a margin in the transversal filters 21, 25 and 26, they may be omitted.
[0069]
In the above embodiment, two circuit systems are provided for generating pseudo crosstalk signals exclusively for the read signals of two beams for two tracks adjacent to both sides of the track to be reproduced. If the apparatus has a known tilt sensor for detecting the irradiation angle with respect to the optical disc, based on the output signal of the tilt sensor, of the two-beam read signals for two tracks adjacent to both sides of the track to be reproduced By providing a switch circuit that selects only the one having more crosstalk components, the above-mentioned pseudo crosstalk signal generation circuit system can be made only one system.
[0070]
【The invention's effect】
As described above, according to the present invention, crosstalk removal for differential signals can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a first exemplary embodiment of the present invention.
FIG. 2 is a schematic explanatory diagram of an example of a differential signal.
FIG. 3 is a schematic explanatory diagram of an example of a positional relationship between a beam spot and a track by a three-beam method.
FIG. 4 is an explanatory diagram of partial response characteristics.
FIG. 5 is a diagram illustrating a relationship among characteristics of PR (a, b, b, a), a run length restriction rule RLL mode, and a provisional determination value of a provisional classifier.
6 is a flowchart for explaining the operation of an example of a temporary discriminator in FIG. 3;
FIG. 7 is a diagram (part 1) showing an example of a waveform before and after waveform equalization according to the present invention.
FIG. 8 is a diagram (part 2) illustrating a waveform example before and after waveform equalization according to the present invention.
FIG. 9 is a diagram (No. 3) illustrating a waveform example before and after waveform equalization according to the present invention.
FIG. 10 is a block diagram of a second exemplary embodiment of the present invention.
FIG. 11 is a block diagram of a third exemplary embodiment of the present invention.
FIG. 12 is a block diagram of a fourth embodiment of the present invention.
FIG. 13 is a block diagram of a fifth embodiment of the present invention.
FIG. 14 is a block diagram of a sixth embodiment of the present invention.
FIG. 15 is a block diagram of a seventh exemplary embodiment of the present invention.
FIG. 16 is a block diagram of an eighth embodiment of the present invention.
FIG. 17 is a block diagram of a ninth embodiment of the present invention.
FIG. 18 is a block diagram of a tenth embodiment of the present invention.
FIG. 19 is a block diagram of an eleventh embodiment of the present invention.
FIG. 20 is a block diagram of a twelfth embodiment of the present invention.
FIG. 21 is a block diagram of a thirteenth embodiment of the present invention.
FIG. 22 is a block diagram of a fourteenth embodiment of the present invention.
FIG. 23 is a block diagram of a fifteenth embodiment of the present invention.
FIG. 24 is a block diagram of a sixteenth embodiment of the present invention.
FIG. 25 is a block diagram of a seventeenth embodiment of the present invention.
FIG. 26 is a block diagram of an eighteenth embodiment of the present invention.
[Explanation of symbols]
11-13 A / D converter
14-16 AGC / ATC circuit
17 Resampling DPLL circuit
18, 19 Resampling circuit
20, 22, 23, 24 Delay adjuster
21 Transversal filter for equalizing waveform of playback signal of track to be played
25, 26 Transversal filter for generating pseudo crosstalk signal
27-29 Multiplier / LPF
30, 31, 34 Subtractor
32 tap delay circuit
32a Partial circuit of tap delay circuit
33 Temporary discrimination circuit
45, 100, 102, 105, 107 Temporary discrimination circuit with fixed threshold
65, 77, 103, 108 Peak detector
101, 104, 106, 109 Error selection

Claims (1)

In a recorded information reproducing apparatus for decoding a first reproduced signal read from an arbitrary recording track to be reproduced recorded on a recording medium,
A signal obtained by subtracting, from the first reproduction signal, a signal obtained by processing a second reproduction signal read from at least one recording track adjacent to any one recording track to be reproduced by a filter having a predetermined filtering characteristic. First subtracting means for outputting
Detecting means for detecting whether the first reproduction signal is a peak and outputting peak point information;
Receiving the peak point information and the output signal of the first subtracting means, a difference value between the output signal from the first subtracting means and a predetermined value at a timing when the peak point information indicates a peak is used as an error signal. Second subtracting means for outputting;
Coefficient generation means for variably controlling the filtering characteristic of the filter based on the error signal so that the error signal is minimized.

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