JP2001051747A5

JP2001051747A5 -

Info

Publication number: JP2001051747A5
Application number: JP1999228678A
Authority: JP
Filing date: 1999-08-12
Publication date: 2005-05-12

Description

【発明の名称】クロック制御回路およびクロック制御方法Patent application title: Clock control circuit and clock control method

Claims

A means for detecting that the PLL output clock output from the PLL oscillation circuit is unstable;
A clock source switching circuit that switches a clock source between a PLL output clock output from the PLL oscillation circuit and the other clocks;
When it is detected that the PLL output clock is unstable, the operation clock output is stopped, the clock source is switched to a clock other than the PLL output clock, and after the PLL output clock is stabilized, the clock source is PLL A clock state control circuit that performs control to switch to an output clock and output an operation clock generated based on the switched PLL output clock;
A clock control circuit comprising:

2. The clock control circuit according to claim 1, further comprising: one or more frequency-divided clock generation frequency-dividing circuits for dividing the PLL output clock to generate the operation clock.

A PLL oscillation circuit that generates a PLL output clock for generating a clock based on a reference clock serving as a reference and a feedback clock;
A divider circuit for feedback clock generation that divides the PLL output clock output from the PLL oscillation circuit to generate the feedback clock;
A clock source switching circuit that switches a clock source between a PLL output clock output from the PLL oscillation circuit and the other clocks;
When it is detected that the PLL output clock is unstable, the operation clock output is stopped and the clock source is switched to a clock other than the PLL output clock, and after the PLL output clock is stabilized, the clock source is PLL A clock state control circuit that performs control to switch to an output clock and output an operation clock generated based on the switched PLL output clock;
A clock control circuit comprising:

Multiplication factor setting means for outputting multiplication factor setting data for setting the multiplication factor of the PLL oscillation circuit;
When acquisition of multiplication factor setting data is permitted, the multiplication factor setting data supplied from the multiplication factor setting means is acquired and held, and the acquired multiplication factor setting data is output to the feedback clock generation divider circuit Buffer circuit, and
A comparison circuit comparing the multiplication factor setting data outputted from the multiplication factor setting means with the multiplication factor setting data outputted from the buffer circuit;
The clock state control circuit stops the output of the operation clock and switches the clock source to a clock other than the PLL output clock when the two multiplication factor setting data are different as a result of comparison in the comparison circuit, and the buffer 4. The clock control circuit according to claim 3, wherein the multiplication factor setting data outputted from the circuit is made to coincide with the multiplication factor setting data outputted from the multiplication factor setting means.

A difference detection circuit which detects and outputs a difference between the multiplication factor setting data outputted from the multiplication factor setting means and the multiplication factor setting data outputted from the buffer circuit;
A division ratio is set based on switching of the clock source by the clock source switching circuit and the difference between the two multiplication factor setting data detected by the difference detection circuit, and the PLL output is performed according to the set division ratio. One or more divider clock generation divider circuits for dividing the clock and generating an operation clock for output;
The clock control circuit according to claim 4, further comprising:

The feedback clock generation divider circuit outputs the operation timing signal to at least one division clock generation divider circuit, and the division clock generation divider circuit that has received the operation timing signal has the operation timing. The clock control circuit according to any one of claims 3 to 5, wherein the operation clock is synchronized with the PLL output clock and output based on a signal.

Arbitrary offset timing for operation of the other division clock generation divider circuit based on the operation timing signal of the division clock generation divider circuit having at least two division clock generation division circuits for one division clock generation 7. The clock control circuit according to claim 6, further comprising a counter circuit that synchronizes by.

Detects that the PLL output clock output from the PLL oscillation circuit is unstable or stable;
When the PLL output clock is unstable, the clock source is switched to a clock other than the PLL output clock, and the output of the operation clock generated based on the clock source is stopped.
A clock control method comprising switching a clock source to the PLL output clock after the PLL output clock is stabilized and outputting an operation clock generated based on the clock source.

9. The clock control method according to claim 8, wherein the operation clock is generated by dividing the PLL output clock.

Clock control that detects that the PLL output clock output from the PLL oscillation circuit is unstable or stable, switches the clock source between the PLL output clock and the other clocks based on the detection result, and outputs the clock In the method
When the PLL output clock is unstable, the output of the operation clock is stopped and the clock source is the other clock,
9. A clock control method comprising: outputting an operation clock by starting clock output from the clock source when the PLL output clock is stabilized.

The clock control method according to claim 10, wherein the operation clock is generated by dividing the clock source.

Detects that the PLL output clock output from the PLL oscillation circuit to which the clock source is supplied is unstable or stable;
When the PLL output clock is unstable, the output of the operation clock is stopped and the clock source is supplied to the operation clock generation circuit while bypassing the PLL oscillation circuit.
After the PLL output clock is stabilized, the clock source is supplied to the PLL oscillation circuit, and the PLL output clock is supplied to the operation clock generation circuit to start output of the operation clock. Control method.

The clock control method according to claim 13, wherein the operation clock generation circuit is a frequency divider circuit.

A means for detecting that the PLL output clock output from the PLL oscillation circuit to which the clock source is supplied is unstable or stable;
Operation clock generation means for generating an operation clock based on the PLL output clock;
When the PLL output clock is unstable, the output of the operation clock is stopped, and the clock source is supplied to the operation clock generation means by bypassing the PLL oscillation circuit, and the PLL output clock is stabilized. A clock state control circuit for supplying the clock source to the PLL oscillation circuit and supplying the PLL output clock to the operation clock generation circuit to start output of the operation clock;
A clock control circuit comprising:

15. The clock control circuit according to claim 14, wherein the operation clock generation unit is a frequency divider circuit.