JP2004086645A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of selecting the operational/non-operational state of a DLL (Delay Locked Loop), equalizing a reset release timing especially even if either a PLL (Phase Locked Loop) or the DLL is used, and generating a long reset release waiting time internally when using the DLL. <P>SOLUTION: A semiconductor circuit, which is applied to a clock pulse generator equipped with both the DLL and the PLL, is provided with the DLL 11 to multiply an external clock signal C2 of low frequency, the PLL 12 to multiply an external clock signal C1 of high frequency, a selector 13 to select one of the multiplied clock signals as an internal clock signal Cin, a delay 15 to delay an external reset signal R by synchronizing with the selected internal clock signal, and a selector 16 to select either the delayed reset signal or the external reset signal R as an internal reset signal Rin. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a microcomputer, and more particularly, to a technology that is effective when applied to a microcomputer including a clock pulse generator that can be properly used depending on the application, in which both a DLL (Delay Locked Loop) and a PLL (Phase Locked Loop) are mixed. .
[0002]
[Prior art]
According to the study by the present inventor, the following techniques can be considered for microcomputers.
[0003]
For example, in recent years, in CPUs and ASICs for mobile phones and mobile devices, in order to reduce power consumption and reduce the number of parts, a clock signal such as a clock signal for a clock is used as a source of a main clock signal (several M to several tens MHz) of a semiconductor circuit. A low frequency clock signal of about several tens kHz may be used. In order to multiply this clock signal by about several hundred to 1000 times and supply it to the main clock signal, a PLL, a DLL or the like is used. The DLL is a circuit that digitally controls an oscillator to perform multiplication. In the case of inputting a low-frequency clock signal, the PLL has problems such as an increase in area and an increase in jitter due to an increase in internal capacitance. Therefore, a DLL is mainly used to multiply a low-frequency clock signal by a high frequency.
[0004]
It is considered that microcomputers for mobile devices in the future will incorporate not only PLLs but also DLLs as built-in oscillators. Also, for backward compatibility, it is necessary for the user to be able to select whether to use the DLL or not.
[0005]
In addition, as a technique related to such a microcomputer, for example, a technique described in Japanese Patent Application Laid-Open No. 2001-290793 is cited. This publication discloses a microcomputer provided with an internal reset circuit so that an internal reset signal is applied after oscillation is stabilized after an external reset signal is input.
[0006]
[Problems to be solved by the invention]
By the way, as a result of the present inventor's study on the microcomputer as described above, the following has become clear.
[0007]
For example, as described above, a microcomputer for mobile devices in the future will be considered to be able to use both a DLL and a PLL in a mixed manner and to use them properly according to the application, but in this case, there are the following problems. In the following, an example of a semiconductor circuit having a circuit configuration in which both the DLL and the PLL are mixed and which can be selectively used depending on the application, which has been studied as a premise of the present invention by the present inventor, is shown in FIGS. This will be described with reference to FIG.
[0008]
As shown in FIG. 14, the semiconductor circuit includes an oscillation control circuit 1e and a core circuit 2 receiving a reset signal Rin and a clock signal Cin from the oscillation control circuit 1e. The configuration of the oscillation control circuit 1e includes a DLL 11 and a PLL (1) 12 for multiplying a clock signal, a selector 13 for selecting an output of the DLL 11 and an output of the PLL (1) 12, and a further multiplication of the selected clock signal. And a clock synchronizing circuit 17 for synchronizing the reset signal Rin to be sent to the core circuit 2 with the internal clock signal Cin when necessary. The external reset signal R and the external clock signal are input as inputs. C1 and C2, and a mode signal S for selecting which of the PLL (1) 12 and the DLL 11 to use from the outside.
[0009]
The reset sequence of the semiconductor circuit is as shown in the waveform charts of FIGS. 15A and 15B. As shown in FIG. 15A, when the PLL is selected by the mode signal S input from the outside and the PLL (1) 12 or the PLL (2) 14 is present, the PLL (1) 12, the PLL (2) The time from the start of operation 14) to the release of the reset is determined by the sum of the stabilization times (x and y, respectively) of PLL (1) 12 and PLL (2) 14.
[0010]
On the other hand, as shown in FIG. 15B, when the DLL is selected by the mode signal S, the time required until the reset is released is the stabilization time (x ′) of the DLL 11 and the time of the PLL (2) 14. The stabilization time of the low-frequency input DLL 11 is much longer than the stabilization time of the PLL, but the reset release time is longer than that of the case where the mode signal S is used to select the PLL. I need to delay it. Therefore, it is necessary to prepare two types of reset release timings for the semiconductor circuit. However, this is complicated, and it is necessary to generate a delay time (several ms) corresponding to (x ′ + y ′) other than the semiconductor circuit. .
[0011]
Therefore, an object of the present invention is to select the operation / non-operation of the DLL, and in particular, to use either the PLL or the DLL, the reset release timing can be the same, and a long reset release when the DLL is used. It is an object of the present invention to provide a microcomputer capable of generating a waiting time inside a semiconductor circuit.
[0012]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0014]
In order to achieve the above object, the present invention can generate an internal clock signal based on an external input clock signal of a microcomputer to which a high frequency (high speed) / low frequency (low speed) clock signal can be inputted from outside. The clock pulse generator is applied to a clock pulse generator capable of generating a controllable internal reset signal including a pull-in time of a clock generation circuit (DLL: multiplying circuit) based on an external reset signal. That is, the microcomputer according to the present invention has the following features.
[0015]
(1) A microcomputer according to the present invention comprises a first frequency multiplier for multiplying a first clock signal, and a second clock signal multiplied by the first frequency multiplier or a third clock signal having a frequency different from the first clock signal. And a delay circuit for delaying the first reset signal in synchronization with the internal clock signal selected by the first selection circuit, and a delay circuit for delaying the first reset signal in synchronization with the internal clock signal selected by the first selection circuit. A second selection circuit that selects one of the delayed second reset signal and the first reset signal and outputs the selected signal as an internal reset signal. For example, the first multiplying circuit includes a DLL circuit. Thereby, the operation / non-operation of the first frequency multiplier composed of the DLL circuit for multiplying the relatively low frequency can be selected, and the second clock signal or the third clock signal obtained by multiplying the externally input first clock signal can be selected. Whichever one is used, the reset release timing can be made the same. Further, a long reset release waiting time when the DLL circuit is used can be internally generated.
[0016]
(2) In the microcomputer according to the above (1), a second frequency multiplier for multiplying the third clock signal to a target frequency and outputting the same is provided in a stage preceding the first selector. Further, a third multiplying circuit is provided at the subsequent stage of the first selecting circuit to multiply the clock signal selected by the first selecting circuit to a target frequency and output as an internal clock signal. For example, the second multiplier circuit and the third multiplier circuit are composed of PLL circuits. Thereby, the reset release timing can be made the same regardless of whether the PLL circuit or the DLL circuit is used. Further, it is possible to cope with a case where the third clock signal needs to be further multiplied and a case where the selected clock signal needs to be further multiplied.
[0017]
(3) In the microcomputer of (1), when the first selection circuit selects the second clock signal multiplied by the first multiplication circuit, the oscillation stabilization output by the first multiplication circuit to generate the internal reset signal. Signals are used. Thus, the internal reset signal can be generated using the oscillation stabilization signal output from the first multiplier.
[0018]
(4) In the microcomputer of the above (1), the first multiplying circuit has a control circuit for reaching a target frequency by using a binary search method when the first multiplying circuit is started. As a result, the time to reach the target frequency is shortened, and the oscillation stabilization time of the first frequency multiplier can be shortened.
[0019]
(5) In the microcomputer of the above (1), the clock signal selected by the first selection circuit is controlled at a subsequent stage of the first selection circuit, so that the clock signal is unstable during the oscillation stabilization time of the first multiplication circuit. It has a logic circuit that performs a logical operation so that a signal is not output. As a result, an unstable clock signal is not output, so that unnecessary power consumption by the core circuit can be suppressed.
[0020]
(6) In the microcomputer described in (1), one of a clock signal selected by the first selection circuit and a fourth clock signal having a frequency different from the third clock signal is selected at a subsequent stage of the first selection circuit. And a third selection circuit for outputting the internal clock signal as an internal clock signal. This makes it possible to respond to the input of a plurality of clock signals.
[0021]
(7) In the microcomputer according to (1), an internal clock signal and an internal reset signal are input, and each of the first clock signal, the second clock signal, and the third clock signal is used as the internal clock signal. It has a core circuit including a plurality of modules that operate selectively. This makes it possible to realize low power consumption of the core circuit by controlling the frequencies of the input clock signals of a plurality of modules of the core circuit.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0023]
(Embodiment 1)
With reference to FIG. 1, an example of the configuration of the semiconductor circuit according to the first embodiment applied to the microcomputer of the present invention will be described. FIG. 1 shows a configuration diagram of a semiconductor circuit of the present embodiment.
[0024]
The semiconductor circuit of the present embodiment is applied to, for example, a clock pulse generator in which both a DLL and a PLL are mounted, and can be used properly according to the application. The internal circuit receives an external clock signal C1, C2 and an external reset signal R as an input. An oscillation control circuit 1 that generates Cin and an internal reset signal Rin, a core circuit 2 that operates using the internal clock signal Cin and the internal reset signal Rin generated by the oscillation control circuit 1 as inputs, and the like. For example, as an example, the external clock signal C1 has a high frequency of about 10 MHz, and the external clock signal C2 has a low frequency of about 32 kHz. The core circuit 2 includes various modules such as a central processing unit (CPU), various memories, and various controllers.
[0025]
The oscillation control circuit 1 is provided with a clock signal generation unit that generates the internal clock signal Cin by using the external clock signals C1 and C2 as inputs, and a reset signal generation unit that generates the internal reset signal Rin by using the external reset signal R as an input. ing.
[0026]
The clock signal generator of the oscillation control circuit 1 includes a DLL 11 for multiplying the low frequency external clock signal C2, a PLL (1) 12 for multiplying the high frequency external clock signal C1, an output of the DLL 11 and a PLL (1) 12 And a PLL (2) 14 for multiplying the clock signal selected by the selector 13 and outputting it as an internal clock signal Cin.
[0027]
In this clock signal generation unit, the DLL 11, PLL (1) 12, and PLL (2) 14 function as a frequency multiplier, and the selector 13 functions as a selector. The selector 13 receives a mode signal S for selecting which of the DLL 11 and the PLL (1) 12 to use. The mode signal S utilizes a mode signal input from the outside such as to select an operation state of an internal circuit. Note that the PLL (1) 12 and the PLL (2) 14 are not always necessary. When the external clock signal C1 is further multiplied, the PLL (1) 12 is required, and the clock signal after selection needs to be further multiplied. If there is, the PLL (2) 14 is required. If the PLL (1) is not provided, the selector 13 can select the external clock C1 and the clock signal multiplied by the DLL 11. If there is no PLL (2), the clock signal selected by the selector 13 can be output as the internal clock Cin.
[0028]
The reset signal generation unit of the oscillation control circuit 1 includes a delay 15 for delaying the external reset signal R, a selector 16 for selecting one of the external reset signal R and the output of the delay 15, and an output of the selector 16 for an internal clock. It is composed of a clock synchronizing circuit 17 that outputs the internal reset signal Rin in synchronization with the signal Cin.
[0029]
In this reset signal generation unit, the delay 15 functions as a delay circuit, and the selector 16 functions as a selection circuit. Further, the delay 15 can be constituted by, for example, a counter synchronized with the input clock signal C2. The above-described mode signal S is used as a selection signal of the selector 16.
[0030]
Next, an example of a reset sequence of the semiconductor circuit of the present embodiment will be described with reference to FIGS. 2A and 2B are waveform diagrams of a reset sequence of the semiconductor circuit of the present embodiment. FIG. 2A shows a case where a PLL is selected by a mode signal input from the outside. (B) shows a case where the DLL is selected by a mode signal input from the outside.
[0031]
As shown in FIG. 2A, when the PLL (1) 12 is selected by the mode signal S input from the outside, the time until the reset is released is (x + y) as in FIG. .
[0032]
As shown in FIG. 2B, when the DLL 11 is selected by the mode signal S input from the outside, the external reset signal R is transmitted to the internal reset signal Rin with a delay of the delay time DELAY by the delay 15, so that the mode signal S The internal reset signal Rin is supplied after the oscillation of the internal clock signal Cin is stabilized by adjusting the delay time DELAY by the delay 15, even if the release timing by the external reset signal R when the PLL (1) 12 is selected in the above is used. can do.
[0033]
Therefore, according to the semiconductor circuit of the present embodiment, the same reset release timing can be used regardless of whether the PLL (1) 12 or the DLL 11 is used. Further, the input clock signal C2 of the DLL 11 can be generated by using a clock signal for a clock, and therefore, it is not necessary to add a terminal in a semiconductor circuit already provided with a clock input terminal for a clock.
[0034]
When the selector 13 selects the external clock C1 (not shown), the external reset signal R is selected by the selector 16 because the delay time DELAY becomes unnecessary.
[0035]
(Embodiment 2)
An example of the configuration of the semiconductor circuit according to the second embodiment applied to the microcomputer of the present invention will be described with reference to FIG. FIG. 3 shows a configuration diagram of the semiconductor circuit of the present embodiment.
[0036]
Similar to the first embodiment, the semiconductor circuit of the present embodiment is applied to, for example, a clock pulse generator in which both a DLL and a PLL are mixed and can be selectively used depending on the application, and is different from the first embodiment. The point is that when a DLL is selected by a mode signal input from the outside, a DLL oscillation stabilization signal output from the DLL is used as an internal reset signal. In this example, a signal may be output to the DLL when the oscillation is stabilized, and this signal is used as an internal reset signal.
[0037]
That is, in the semiconductor circuit of the present embodiment, the oscillation control circuit 1a which receives the external clock signals C1 and C2 and the external reset signal R as inputs and generates the internal clock signal Cin and the internal reset signal Rin, outputs the external clock signal C2 to the DLL 11a. An external reset signal R is input, a DLL output clock signal Cdll and a DLL oscillation stabilization signal D are output, and this DLL oscillation stabilization signal D is input to the delay 15 and used for generating an internal reset signal Rin.
[0038]
Next, an example of a reset sequence of the semiconductor circuit according to the present embodiment will be described with reference to FIGS. 4A and 4B are waveform diagrams of a reset sequence of the semiconductor circuit according to the present embodiment. FIG. 4A shows a case where a PLL is selected by a mode signal input from the outside. (B) shows a case where the DLL is selected by a mode signal input from the outside.
[0039]
As shown in FIG. 4A, when the PLL (1) 12 is selected by the mode signal S input from the outside, the time until the reset is released is (x + y) as in FIG. .
[0040]
As shown in FIG. 4B, when the DLL 11a is selected by the mode signal S input from the outside, the DLL 11a starts operating by releasing the external reset signal R. After the oscillation of the DLL 11a is stabilized, a DLL oscillation stabilizing signal D is output. Further, the PLL (2) 14 starts operating when the power is turned on, when the operation of the DLL 11a is started, or when the oscillation of the DLL 11a is stabilized. After the output, the oscillation stabilization time of the PLL (2) 14 is required. Therefore, in the delay 15, the delay time DELAY corresponding to the oscillation stabilization time of the PLL (2) 14 is added to the DLL oscillation stabilization signal D, and the internal reset signal Rin is released.
[0041]
Therefore, also in the semiconductor circuit of the present embodiment, by using the DLL oscillation stabilization signal D output from the DLL 11a as the internal reset signal, either the PLL (1) 12 or the DLL 11a can be used as in the first embodiment. , The same reset release timing can be used, and the internal reset signal Rin can be released after the oscillation of the PLL (2) 14 is stabilized.
[0042]
Next, an example of the configuration of a DLL that outputs a DLL oscillation stabilization signal will be described with reference to FIGS. In addition, an example of the binary search method at the time of starting the DLL will be described with reference to FIGS. 7 and 8. FIG. 5 is a block diagram of the DLL, FIG. 6 is a block diagram of an oscillation circuit unit in the DLL, FIG. 7 is a flowchart of an operation sequence of the DLL, and FIG. 8 is a flowchart of binary search control when a frequency is determined. Here, as an example of the DLL, a method of using a binary search method to reach a target frequency when the DLL is activated is used.
[0043]
As shown in FIG. 5, the DLL 11a has a basic configuration of multiplying by n, and receives the input clock signal (C2), the reset signal (R), and the clock signal generated by the oscillation circuit unit 33 using the delay loop as inputs, and outputs a delay determination signal. A delay control unit 32 that receives an input clock signal (C2), a reset signal (R), and a delay determination signal to generate a delay control signal and a DLL oscillation stabilization signal (D); The oscillator circuit section 33 includes a delay loop that generates a multiplied output clock signal (Cdll) using a signal as an input.
[0044]
The phase control unit 31 includes an n-ary counter 34 and a frequency phase comparator 35. The delay control unit 32 includes a start-up control circuit 36, an up / down counter 37, and a delay control decoder 38. The oscillation circuit unit 33 including the delay loop includes a variable delay unit 39 and an inverter 40. Specifically, as shown in FIG. 6, for example, the oscillation circuit section 33 arbitrarily selects an inverter 40, for example, 1024 cascaded buffers 41 (details will be described later), and an output of each buffer 41. , And the like.
[0045]
The operation of the DLL 11a configured as described above is feedback control as described below. The oscillation circuit unit 33 generates a desired frequency by controlling the amount of delay by the delay control decoder 38 in the delay control unit 32. The output is frequency-divided by the phase control unit 31 using the n-ary counter 34 by 1 / n, and the frequency-phase comparator 35 compares the frequency-divided signal with the input clock signal (C2). As a result of the comparison, for example, if the phase of the input clock signal (C2) is earlier, it is necessary to reduce the delay amount of the delay loop. Therefore, the delay control unit 32 uses the delay determination signal and the up / down counter 37 controls the delay control decoder 38. Is reduced to speed up the output clock signal (Cdll). If the phase of the input clock signal (C2) is late, the reverse process is performed. In this way, the input clock signal (C2) is multiplied by feeding back the difference between the periods of the input clock signal (C2) and the multiplied output clock (Cdll) to the multiplied output clock (Cdll).
[0046]
Normally, the DLL does not detect how much the phase difference is at the time of phase comparison, and determines only whether it is early or late. Therefore, the operation after the phase comparison simply adjusts the number of delay stages by ± 1. Therefore, for example, when the number of delay stages is 1000, when the number of delay stages at the target frequency is 900, and when the initial value of the decoder at startup is 0, the time until output frequency stabilization is at least (input period × 900). Will be needed. If the input is 32 kHz, it is 28 ms, which is a very large value. Since the number of delay stages at the target frequency is not constant depending on the semiconductor process, voltage and temperature, it is impossible to match the initial value of the decoder. Therefore, there is a problem that the oscillation stabilization time is too long in the normal DLL method.
[0047]
Thus, in the present embodiment, as a countermeasure, the binary search method shown in FIGS. 7 and 8 is used to determine the number of delay stages when the DLL 11a is started. This control is performed by the start-up control circuit 36 included in the delay control unit 32 included in the DLL 11a. Here, for the sake of explanation, it is assumed that the up / down counter 37 has 10 bits. At this time, the number of delay stages is 1024.
[0048]
As shown in FIG. 7, when the DLL 11a receives a reset release (step S1), the up / down counter 37 is controlled to search for a target delay stage number by a binary search (step S2), and the input clock signal The target number of delay stages can be reached in about 10 cycles. When the binary search is completed, a process of adjusting the number of delay stages by ± 1 for the phase difference is performed, and feedback control is performed so that the output clock signal stably operates near the target multiplied frequency (step S3). ). When the binary search is completed, by setting a flag, it can be used outside the DLL as the DLL oscillation stabilization signal.
[0049]
Specifically, as shown in FIG. 8, in the binary search control at the time of determining the frequency, the value of the up / down counter 37 is first set to '1000000000000 corresponding to the 512th stage (1024/2) after the reset is released, as shown in FIG. Is set to ', and the determination is made at the 512th stage, and the process proceeds to the second time according to the result of this determination. In the second time, if the result of the determination is that the multiplied output clock signal is earlier than the input clock signal, the value of the up / down counter 37 is set to '1100000000000' corresponding to the 768th stage (512 + 512/2), and conversely if it is later. It is set to '010000000000' corresponding to the 256th stage (512-512 / 2) to determine whether it is early or late.
[0050]
Similarly, in the third time, it corresponds to '1110000000' corresponding to the 896th stage (768 + 256/2), '1010000000' corresponding to the 640th stage (768-256 / 2), and 384th stage (256 + 256/2). '0110000000', set to '001000000000' corresponding to the 128th stage (256-256 / 2) to determine whether it is early or late, and determine the target frequency by performing the same for the fourth and subsequent times Can be.
[0051]
Therefore, in the present embodiment, when the number of delay stages is determined by using the binary search method performed by using these control circuits when the DLL 11a is activated, the time required to reach the target number of delay stages is shortened. The oscillation stabilization time can be shortened.
[0052]
(Embodiment 3)
An example of the configuration of the semiconductor circuit according to the third embodiment applied to the microcomputer of the present invention will be described with reference to FIG. FIG. 9 shows a configuration diagram of the semiconductor circuit of the present embodiment.
[0053]
Similar to the first embodiment, the semiconductor circuit of the present embodiment is applied to, for example, a clock pulse generator in which both a DLL and a PLL are mixed and can be selectively used depending on the application, and is different from the first embodiment. The point is that a mechanism for preventing an unstable clock signal from entering the core circuit during the oscillation stabilization time of the DLL and the PLL is added. In this example, wasteful power consumption due to an unstable clock signal entering the core circuit can be suppressed.
[0054]
That is, in the semiconductor circuit of the present embodiment, the oscillation control circuit 1b which receives the external clock signals C1 and C2 and the external reset signal R to generate the internal clock signal Cin and the internal reset signal Rin is provided by the PLL (clock) in the clock signal generation unit. 2) An OR gate 18 is connected to the subsequent stage of 14, and a delay (1) 19 is connected between the selector 16 and the clock synchronizing circuit 17 in the reset signal generating unit. One of the OR gates 18 is a PLL. (2) The output of the selector 14 is input to the output 14 and the output of the selector 16 is input to the other. The output of the OR gate 18 is input to the clock synchronization circuit 17 and output as the internal clock signal Cin.
[0055]
Next, an example of a reset sequence of the semiconductor circuit of the present embodiment will be described with reference to FIGS. FIGS. 10A and 10B show waveform diagrams of a reset sequence of the semiconductor circuit of the present embodiment. FIG. 10A shows a case where a PLL is selected by a mode signal input from the outside. (B) shows a case where the DLL is selected by a mode signal input from the outside.
[0056]
As shown in FIG. 10A, when the PLL (1) 12 is selected by the mode signal S input from the outside, the core circuit 2 supplies the PLL (1) 12 and the PLL (2) 14 during the external reset. Unstable clock signal at the start of operation is not transmitted. When the external reset R is released, the clock signal starts to be supplied to the core circuit 2, and the internal reset is released after a delay time DELAY1 due to the delay (1) 19. The delay time DELAY1 is required for the number of cycles required until the core circuit 2 is stabilized, is a delay corresponding to several cycles of the internal clock, and can be constituted by an external clock signal or a counter synchronized with the internal clock signal.
[0057]
As shown in FIG. 10B, when the DLL 11 is selected by the mode signal S input from the outside, the unstable clock at the start of the operation of the DLL 11 and the PLL (2) 14 during the delay period DELAY by the delay 15 No signal is transmitted. After the clock signals of the DLL 11 and the PLL (2) 14 are stabilized, the delay of the time DELAY by the delay 15 ends, the clock signal starts to be supplied to the core circuit 2, and the internal reset is released after the delay time DELAY1.
[0058]
Therefore, according to the semiconductor circuit of the present embodiment, the same effects as those of the first embodiment can be obtained, and since the unstable clock signal does not enter the core circuit 2, wasteful consumption by the core circuit 2 is avoided. Power can be reduced.
[0059]
(Embodiment 4)
With reference to FIG. 11, an example of the configuration of the semiconductor circuit of the fourth embodiment applied to the microcomputer of the present invention will be described. FIG. 11 shows a configuration diagram of the semiconductor circuit of the present embodiment.
[0060]
Similar to the first embodiment, the semiconductor circuit of the present embodiment is applied to, for example, a clock pulse generator in which both a DLL and a PLL are mixed and can be selectively used depending on the application, and is different from the first embodiment. The point is that it is configured to be able to respond to the input of a plurality of clock signals.
[0061]
That is, in the semiconductor circuit of the present embodiment, the oscillation control circuit 1c has a selector 20 connected to the subsequent stage of the PLL (2) 14 in the clock signal generation unit, and the selector 20 and the previous stage selector 13a provide a plurality of clock signals. , And a reset signal generation unit is composed of an AND gate 21, a subtraction counter 22, an AND gate 23, an OR gate 24, etc., and furthermore, a plurality of mode signals S1, S2, , A logic circuit 25 for performing various mode controls based on.
[0062]
In the oscillation control circuit 1c, the output of the DLL 11a, the output of the PLL (1) 12, and the external clock signal C1 are input to the selector 13a at the preceding stage of the clock signal generating unit, and one of the clock signals is selected. The selector 20 receives the output of the PLL (2) 14 and the output of the selector 13a, selects one of the clock signals, and outputs it as an internal clock signal Cin. The selection by these selectors 13a and 13 is controlled by the logic circuit 25.
[0063]
In the reset signal generator of the oscillation control circuit 1c, a DLL oscillation stabilization signal D and a feedback signal of the reset signal generator are input to the AND gate 21, and the output of the AND gate 21 is supplied to the subtraction counter 22 as a count start signal. Is entered. The output of the subtraction counter 22 is input to an AND gate 23, where the AND gate 23 performs a logical operation on a control signal (a DLL is used when High and a DLL is not used when Low) input from the logic circuit 25. The output of the AND gate 23 is input to an OR gate 24 to which the external reset signal R is input to one side, and the internal reset signal Rin is output from the OR gate 24. Although the external reset signal R and the output clock signal of the DLL 11a are input to the subtraction counter 22, it is also possible to input the external clock signal C2 instead of the output clock signal of the DLL 11a.
[0064]
Next, an example of a reset sequence of the semiconductor circuit of the present embodiment will be described with reference to FIGS. 12A and 12B are waveform diagrams of a reset sequence of the semiconductor circuit according to the present embodiment. FIG. 12A shows a case where the DLL is used, and FIG. 12B shows a case where the DLL is not used. Show.
[0065]
In this semiconductor circuit, the logic circuit 25 selects the use / non-use of the DLL 11a and the use / non-use of the PLL (1) 12, 12 (2) 14 based on the inputs of the plurality of mode signals S1, S2,. A signal to be generated is supplied to the selectors 13a and 20 and the AND gate 23. As a result, when the DLL is used, the stabilization time of the DLL 11a is secured and the stabilization time of the PLL (2) 14 used at the same time is released after release by the external reset signal R as shown in FIG. It is possible to secure. When the DLL is not used, the external reset signal R becomes the internal reset signal Rin as it is as shown in FIG.
[0066]
Therefore, according to the semiconductor circuit of the present embodiment, the same effects as those of the first embodiment can be obtained, and it is possible to cope with the input of a plurality of clock signals.
[0067]
(Embodiment 5)
An example of the configuration of the semiconductor circuit according to the fifth embodiment applied to the microcomputer of the present invention will be described with reference to FIG. FIG. 13 shows a configuration diagram of the semiconductor circuit of the present embodiment.
[0068]
Similar to the first embodiment, the semiconductor circuit of the present embodiment is applied to, for example, a clock pulse generator in which both a DLL and a PLL are mixed and can be selectively used depending on the application, and is different from the first embodiment. The point is that a mechanism for using the low-frequency input clock signal of the DLL for reducing the power consumption of the core circuit is added. In this example, controlling the input clock frequencies of a plurality of modules in the core circuit is effective in reducing the power consumption of the core circuit.
[0069]
That is, in the semiconductor circuit of the present embodiment, the core circuit 2a includes a module (1) 51 for controlling a reset signal, a delay (1) 52 corresponding to the module (1) 51, and a plurality of clock signals. Are selectively inputted, and the selectors 55, 56,... Corresponding to the modules (2) 53, (3) 54,. Is done. The oscillation control circuit 1d has the same configuration as that of the first embodiment (FIG. 1), but outputs Cin, C1in, and C2in as internal clock signals. The delay (1) 52 has a delay equivalent to that of the selectors 55, 56,... And is necessary for adjusting the clock phases of the modules (1) 51, (2) 53, (3) 54,.
[0070]
An internal reset signal Rin is input to the module (1) 51, an internal clock signal Cin is input via the delay (1) 52, and a control signal for clock selection is supplied to each module (2) 53, (3). Are supplied to the selectors 55, 56,. Each of these modules (2) 53, (3) 54,... Receives an internal reset signal Rin, and outputs one of the internal clock signals Cin, C1in, C2in selected by the selectors 55, 56,. The signal is input, and the internal circuit of each module (2) 53, (3) 54,.
[0071]
Normally, when controlling the clock signal of the module, the clock signal is stopped or the frequency of the main clock signal (several M to several tens MHz) of the semiconductor circuit is input to the module under the control of the module (1) 51.
[0072]
However, in the present embodiment, the power consumption of the module is reduced by inputting the input clock signal C2in to the DLL 11, which is about 1000 times slower than the main clock signal, to the modules (2) 53, (3) 54,. It can be greatly reduced. For example, the present embodiment is effective for an interrupt control module that may be slow in processing. When the DLL 11 is used to output the internal clock Cin to a certain module, the internal clock C1in is output to another module to output, for example, the external clock signal C1 to a specific frequency required for a sound processing module or the like. It can also be used to input a clock signal to another module.
[0073]
Note that, in order to realize the present embodiment, the main clock signal and the external input clock signal may be asynchronous, so that the module input clock signal is converted from the main clock signal or the frequency obtained by dividing the frequency to the external input clock signal. When switching to a signal, it is necessary to prevent an unnecessary signal state of the module input clock signal from occurring when switching from the external input clock signal to the main clock signal or a frequency obtained by dividing the frequency. Therefore, the selectors 55, 56,... Are provided with logic for that purpose. The selectors 55, 56,... Can be connected to a High or Low fixed potential selected when stopping the clock signal.
[0074]
Therefore, according to the semiconductor circuit of the present embodiment, the same effects as those of the first embodiment can be obtained, and the input clocks of the plurality of modules (2) 53, (3) 54,. By controlling the frequency of each signal, low power consumption of the core circuit 2a can be realized.
[0075]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0076]
For example, in each of the embodiments, an example in which a PLL and a DLL are mounted is shown. However, the present invention is effective in a semiconductor circuit in which at least a DLL circuit is mounted as described in the first embodiment. It becomes.
[0077]
Further, the present embodiment is effective not only for the DLL circuit but also for a circuit requiring a sufficient oscillation stabilization time similarly to the DLL circuit.
[0078]
The present invention is suitable for a microprocessor as described above, and can also be applied to an oscillation circuit, a multiplication circuit, and the like.
[0079]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0080]
(1) A first multiplying circuit for multiplying the first clock signal, a first selecting circuit for selecting one of the multiplied second clock signal and the third clock signal, and a reset signal for synchronizing with the selected internal clock signal And a second selection circuit for selecting one of the delayed second reset signal and the first reset signal, thereby providing a first circuit for multiplying a relatively low frequency. The reset / release timing can be selected regardless of whether a second clock signal or a third clock signal obtained by multiplying a first clock signal input from the outside can be selected. Can be made the same, so that the specification can be simplified. Further, since a long reset release waiting time when using the DLL circuit can be internally generated, it is possible to reduce the number of parts of the entire product.
[0081]
(2) By providing a second frequency multiplier for multiplying the third clock signal before the first selection circuit and a third frequency multiplier for multiplying the selected clock signal after the first selection circuit, especially the second frequency multiplication circuit Regardless of whether the multiplying circuit, and / or the third multiplying circuit (PLL circuit), or the first multiplying circuit (DLL circuit) is used, the reset release timing can be made the same as in (1). In addition, when the third clock signal needs to be further multiplied or when the selected clock signal needs to be further multiplied, it is possible to cope well.
[0082]
(3) When the first selection circuit selects the second clock signal multiplied by the first multiplication circuit, the internal reset signal can be generated using the oscillation stabilization signal output from the first multiplication circuit. .
[0083]
(4) Since the first frequency multiplier has a control circuit using the binary search method, the time required to reach the target frequency when the first frequency multiplier is started is reduced, so that the oscillation stabilization time of the first frequency multiplier is reduced. It is possible to do.
[0084]
(5) Since a logic circuit for controlling the selected clock signal is provided at a subsequent stage of the first selection circuit, a logic operation can be performed so that an unstable clock signal is not output during the oscillation stabilization time of the first multiplication circuit. Therefore, unnecessary power consumption by the core circuit can be suppressed.
[0085]
(6) Since the third selection circuit that selects one of the selected clock signal and the fourth clock signal is provided at the subsequent stage of the first selection circuit, it is possible to appropriately cope with the input of a plurality of clock signals. .
[0086]
(7) By having a core circuit including a plurality of modules each operating by selecting any one of the internal clock signals as the internal clock signal, it is possible to control the frequencies of the input clock signals of the plurality of modules, respectively. Therefore, low power consumption of the core circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a semiconductor circuit according to a first embodiment applied to a microcomputer of the present invention.
FIGS. 2A and 2B are waveform diagrams showing a reset sequence of the semiconductor circuit according to the first embodiment of the present invention.
FIG. 3 is a configuration diagram showing a semiconductor circuit according to a second embodiment applied to the microcomputer of the present invention;
FIGS. 4A and 4B are waveform diagrams showing a reset sequence of the semiconductor circuit according to the second embodiment of the present invention.
FIG. 5 is a configuration diagram showing a DLL in the semiconductor circuit according to the second embodiment of the present invention;
FIG. 6 is a configuration diagram showing an oscillation circuit unit in a DLL in the semiconductor circuit according to the second embodiment of the present invention;
FIG. 7 is a flowchart showing an operation sequence of a DLL in the semiconductor circuit according to the second embodiment of the present invention;
FIG. 8 is a flowchart illustrating binary search control when a frequency is determined in the semiconductor circuit according to the second embodiment of the present invention;
FIG. 9 is a configuration diagram showing a semiconductor circuit according to a third embodiment applied to the microcomputer of the present invention.
FIGS. 10A and 10B are waveform diagrams showing a reset sequence of the semiconductor circuit according to the third embodiment of the present invention.
FIG. 11 is a configuration diagram showing a semiconductor circuit according to a fourth embodiment applied to the microcomputer of the present invention.
FIGS. 12A and 12B are waveform diagrams showing a reset sequence of the semiconductor circuit according to the fourth embodiment of the present invention.
FIG. 13 is a configuration diagram showing a semiconductor circuit according to a fifth embodiment applied to the microcomputer of the present invention.
FIG. 14 is a configuration diagram showing a semiconductor circuit studied as a premise of the present invention.
FIGS. 15A and 15B are waveform diagrams showing a reset sequence of a semiconductor circuit studied as a premise of the present invention.
[Explanation of symbols]
1,1a, 1b, 1c, 1d, 1e oscillation control circuit
2,2a core circuit
11,11a DLL
12,14 PLL
13, 13a, 16, 20 selector
15, 19 Delay
17 Clock Synchronous Circuit
18,24 OR gate
21,23 AND gate
22 Subtraction counter
25 Logic circuit
31 Phase control unit
32 Delay control unit
33 Oscillation circuit section
34 n-ary counter
35 frequency phase comparator
36 Start-up control circuit
37 Up / Down counter
38 Delay control decoder
39 Variable delay unit
40 inverter
41 buffer
42 Selector
51, 53, 54 modules
52 Delay
55, 56 selector

Claims (11)

A first multiplying circuit for multiplying the first clock signal;
A first selection circuit that selects one of the second clock signal multiplied by the first multiplication circuit or a third clock signal having a frequency different from the first clock signal and outputs the selected signal as an internal clock signal;
A delay circuit for delaying a first reset signal in synchronization with the internal clock signal selected by the first selection circuit;
And a second selection circuit for selecting one of the second reset signal or the first reset signal after the delay by the delay circuit and outputting the selected signal as an internal reset signal. The microcomputer according to claim 1,
The microcomputer according to claim 1, wherein the first multiplying circuit includes a DLL circuit. The microcomputer according to claim 1,
A microcomputer provided with a second multiplier for multiplying the third clock signal to a target frequency and outputting the same at a stage preceding the first selector. The microcomputer according to claim 1,
A microcomputer provided at a subsequent stage of the first selection circuit, comprising a third multiplication circuit for multiplying the clock signal selected by the first selection circuit to a target frequency and outputting it as an internal clock signal. The microcomputer according to claim 3 or 4,
The microcomputer according to claim 1, wherein the second multiplier and the third multiplier are formed of a PLL circuit. The microcomputer according to claim 1,
When selecting the second clock signal multiplied by the first multiplying circuit by the first selecting circuit, an oscillation stabilizing signal output from the first multiplying circuit is used to generate the internal reset signal. Microcomputer. The microcomputer according to claim 1,
The microcomputer according to claim 1, wherein the first multiplying circuit has a control circuit that uses a binary search method to reach a target frequency when the first multiplying circuit is started. The microcomputer according to claim 1,
A logic for controlling a clock signal selected by the first selection circuit at a subsequent stage of the first selection circuit to perform a logic operation so that an unstable clock signal is not output during the oscillation stabilization time of the first multiplication circuit. A microcomputer having a circuit. The microcomputer according to claim 1,
A third selection that selects one of a clock signal selected by the first selection circuit or a fourth clock signal having a frequency different from the third clock signal and outputs the selected clock signal as an internal clock signal at a subsequent stage of the first selection circuit. A microcomputer having a circuit. The microcomputer according to claim 1,
A plurality of internal clock signals to which the internal clock signal and the internal reset signal are input, each of which operates by selecting any one of the first clock signal, the second clock signal, and the third clock signal as the internal clock signal A microcomputer having a core circuit including the module of (1). The microcomputer according to claim 1,
When selecting the third clock signal, the microcomputer includes the second selection circuit that selects a reset signal that does not pass through the delay circuit and outputs it as an internal reset signal.

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