JP2000357400A - Standby system and method for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable screening a memory cell in which data retention is defective without separating a memory cell from an external power source. SOLUTION: A standby system of a semiconductor memory, in which each of plural chips connected to the outside power source has a memory cell 3 of a static RAM, is provided with a regulator circuit 1 lowering the voltage of an external power source supplied to a memory cell of a chip and making the memory cell a standby state, and a memory control circuit 2 outputting a control signal making the regulator circuit lower voltage of the external power source to a regulator circuit when defect of data retention is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a standby system and method for a semiconductor memory device. In particular, the present invention
AM (Static Random Access M)
The present invention relates to a semiconductor memory device standby system and method for detecting a data retention defect of a memory cell of a memory (static RAM).

[0002]

2. Description of the Related Art FIG. 5 is a diagram illustrating a circuit configuration of a conventional SRAM semiconductor memory device. Note that the same components are denoted by the same reference numerals and numbers throughout the drawings and will be described. In an SRAM semiconductor memory device, a plurality of memory cells 3 are provided in each of a plurality of chips or memory blocks. As shown in the figure, the memory cell 3 is formed on a silicon substrate and has a four-transistor, two-resistance type SRAM. MOS (Metal Oxide Sem)
(a metal oxide semiconductor).

In a memory cell 3, two CMOS (Com)
elementary MetalOxide Sem
icon (complementary metal oxide semiconductor) FE
T (Field Effect Transisto)
r; field-effect transistor) 31, 32 are crossed, and FF (Flip flop; flip-flop)
A circuit is configured to store data of bit D and bit inversion D, respectively. The CMOSFETs 31 and 32 are connected to an external power supply of a voltage Vcc via pull-up resistors R33 and R34.

[0004] Each of the CMOSFETs 31 and 32 has an MO.
SFETs 35 and 36 are connected, and MOSFETs 35 and 3
6 is connected to a word line and a data line,
Read the stored data from 1, 32 or MOS
Data is written to the FETs 31 and 32. In addition, SRA
A memory control circuit 2 is provided in the M semiconductor memory device. The memory control circuit 2 is connected to an external power supply of a voltage Vcc, has a CS (chip select) terminal for enabling a chip, and Performs read access control.

The power supply of the voltage Vcc is wired directly from an external power supply terminal of the chip or the memory block. By the way, in the memory cell 3, a cell leak may occur due to a silicon crystal defect or the like. When this cell leak occurs, the memory cell 3 has a data retention defect. As a method for detecting this data retention defect, it is known to perform a data retention test by lowering the voltage Vcc of the external power supply to the memory cell 3. Conventionally, screening of data retention failures related to the memory cells 3 of the chip is performed by disconnecting the memory cells 3 from the external power supply and lowering the voltage only for the memory cells 3 alone by the test power supply. .

[0006]

However, when screening the data retention failure by lowering the voltage of the external power supply on the substrate on which the chip of the memory cell 3 to be tested is mounted in the above-mentioned semiconductor memory device, ,
Peripheral devices do not operate because their voltage drops,
There is a problem that it is impossible to screen for data retention failure of the memory cell 3. In addition, it is very complicated to separate the memory cell 3 into a single product and perform the test. For this reason, screening for data retention failure cannot be performed sufficiently, and there is a problem in improving reliability.

Accordingly, the present invention has been made in view of the above problems, and provides a standby system and a method of a semiconductor memory device which enable screening of a data retention failure without disconnecting a memory cell 3 from an external power supply.

[0008]

According to the present invention, there is provided a standby system for a semiconductor memory device in which a plurality of chips connected to an external power supply are provided with static RAM memory cells, respectively. A regulator circuit for lowering the voltage of the external power supply supplied to the memory cell of the chip to make the memory cell standby; and reducing the voltage of the external power supply to the regulator circuit when detecting a data retention failure A standby system for a semiconductor memory device, comprising: a memory control circuit that outputs a control signal to the regulator circuit. Preferably, the memory cell of the static RAM has four transistors,
It is formed of two resistors or a TFT.

By this means, after the memory chip is mounted on the substrate, the data retention failure chip caused by the growth of silicon crystal defects generated during operation and use in the system or the like is specified and repaired, thereby improving the operation reliability of the system. It can be greatly improved and maintained. Preferably, the voltage dropped by the regulator circuit may be substantially half the voltage of the external power supply. This is because the dropped voltage is a voltage that causes a data retention failure.

Preferably, data is written to a memory cell before the voltage of the external power supply is lowered by the regulator circuit, and after the voltage of the external power supply is lowered, the data is returned to the original voltage and the data of the memory cell is read. Then, the written data is compared with the read data to detect a data retention defect. By this means, a data retention defective chip can be specified based on a comparison between read data and write data. Preferably,
The memory control circuit outputs to the regulator circuit a control signal for causing the regulator circuit to lower the voltage of the external power supply for the unused chip.

By this means, power consumption reduction control can be easily performed by user control according to the use map of the memory block. Furthermore, the present invention relates to a standby method for a semiconductor memory device in which a plurality of chips connected to an external power supply are provided with memory cells of a static RAM.
Dropping the voltage of the external power supply supplied to the memory cells of the chip to set the memory cells to standby; and setting the memory cells to standby when detecting a data retention failure. And a standby method for a semiconductor memory device.

By this means, similarly to the above-described invention, after mounting the memory chip on the substrate, the data retention failure chip caused by the growth of silicon crystal defects generated during operation and use in the system or the like is specified and repaired. The operational reliability of the system can be greatly improved and maintained.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a standby system of a semiconductor memory device according to the present invention. As shown in this figure, what is different from FIG. 4 is a regulator circuit 1 provided in each of a plurality of chips on which the memory cells 3 are mounted or in each of a plurality of memory blocks.

The regulator circuit 1 has an external voltage Vcc.
And supplies the voltage VccCELL to the memory cell 3
To the resistors R33 and R34. The memory control circuit 2 is provided with an external terminal for inputting a standby (STBY) signal. When the standby signal is input to the external terminal, the memory control circuit 2 outputs an STBY control signal to the regulator circuit 1. If there is no input of the STBY control signal from the memory control circuit 2, the regulator circuit 1 sets the voltage VccCELL as the voltage VccCELL of the external power supply.
Output cc as it is.

When an STBY control signal is input from the memory control circuit 2, the regulator circuit 1 drops the voltage Vcc of the external power supply and outputs the voltage VccCELL. Preferably, voltage VccCELL is about Vcc / 2. This is a voltage required for detecting a data retention failure. Peripheral circuits, peripheral devices, and the like other than the memory cell 3 are directly wired from an external power supply, and the power supply voltage Vcc is supplied as before.

FIG. 2 is a flowchart for explaining a series of operations of the standby system 2 of the semiconductor memory device in FIG. In step S11, data is written to the memory cell 3. In step S12, the memory control circuit 2 inputs a standby (STBY) signal to its external terminal. As a result, the static RAM changes from the read / write mode to the standby mode. In step S13, the memory control circuit 2 switches to the regulator circuit 1 for standby (STBY).
Outputs control signal.

In step S14, the voltage from the regulator circuit 1 to the memory cell 3 is changed from Vcc to VccCE.
Lower to LL. At this time, the voltage Vcc of the external power supply is supplied to the peripheral circuits and peripheral devices. In step S15, the data of the memory cell 3 is held. In step S16, the output of the standby (STBY) control signal from the regulator circuit 1 is released. In step S17, the voltage from the regulator circuit 1 to the memory cell 3 is returned from VccCELL to Vcc.
As a result, the static RAM returns from the standby mode to the read / write mode.

In step S18, the data in the memory cell 3 is read. In step S19, the write data in step S11 is compared with the read data in step S18. As described above, while the voltage supplied to the memory cell 3 is falling, the voltage of the external power supply is directly supplied to the peripheral circuits and the peripheral devices, and the peripheral circuits and the peripheral devices are operating. The screening for identifying the data retention failure of No. 3 has become possible.

Therefore, after the chip is mounted on the substrate, it is possible to identify and repair a data retention failure chip due to the growth of a silicon crystal defect generated during operation and use in a system or the like, thereby greatly improving the operation reliability of the system. Can be improved and maintained.

FIG. 3 is a flowchart for explaining another series of operations for the standby system 2 of the semiconductor memory device in FIG. In step S21, a use map of the memory block or the memory chip is displayed. In step S22, a standby signal is output to the memory control circuit 2 of the unused memory block or unused memory chip.

In step S23, the voltage from the regulator circuit 1 of the unused memory block or unused memory chip to the memory cell 3 is reduced from Vcc to VccCELL. In this manner, the voltage applied to the memory cell 3 of the unused memory block or the unused memory chip is reduced to about 1 /
2, the power consumption can be reduced to about 1/4. Therefore, power consumption reduction control can be easily performed by user control.

FIG. 4 is a diagram for explaining another example of the standby system of the semiconductor memory device in FIG. The memory cell 3 shown in this figure is a TFT (Thin Film)
Transistor (thin film transistor) SRAM
It is. This drawing differs from FIG. 1 in that MOSFETs 37 and 38 are used as resistors instead of the pull-up resistors R33 and R34. The same operation and effect as those of the configuration of FIG. 1 can be obtained in the configuration shown in FIG.

[0023]

As described above, according to the present invention,
In a substrate on which a memory chip is mounted, after data is written to the memory chip in the read / write mode, the operation is changed from an external terminal to the standby mode, whereby the memory cell voltage inside the chip is lowered and defective data retention is caused. Next, the operation is returned to the read / write mode, and after reading the data of the memory chip, the data retention defective chip can be specified by comparing it with the write data.

According to the above feature, after a memory chip is mounted on a substrate, a data retention failure chip caused by the growth of silicon crystal defects generated during operation and use in a system or the like is specified and repaired, thereby improving the operation reliability of the system. It can be greatly improved and maintained. Further, in the system using the chip or the memory block of the present invention, reduction control of power consumption can be easily performed by user control along the use map of the chip or the memory block.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a standby system of a semiconductor memory device according to the present invention.

FIG. 2 is a flowchart illustrating a series of operations of a standby system 2 of the semiconductor memory device in FIG. 1;

FIG. 3 is a flowchart illustrating another series of operations of the standby system 2 of the semiconductor memory device in FIG. 1;

FIG. 4 is a diagram illustrating another example of the standby system of the semiconductor memory device in FIG. 1;

FIG. 5 is a diagram illustrating a circuit configuration of a conventional SRAM semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Regulator circuit 2 ... Memory control circuit 3 ... Memory cell 31, 32 ... CMOS 33, 34 ... Resistance 35, 36, 37, 38 ... MOS

Claims (7)

[Claims] 1. In a standby system of a semiconductor memory device in which a plurality of chips connected to an external power supply are provided with memory cells of a static RAM, a voltage of the external power supply supplied to the memory cells of the chip is reduced. A regulator circuit for setting the memory cell to standby; and a memory control circuit for outputting to the regulator circuit a control signal for lowering the voltage of the external power supply to the regulator circuit when detecting a data retention failure. A standby system for a semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the memory cells of said static RAM are formed of four transistors and two resistors. 3. The standby system according to claim 2, wherein the memory cells of the static RAM are formed of TFTs. 4. The standby system according to claim 1, wherein a voltage dropped by said regulator circuit is substantially half of a voltage of said external power supply. 5. The regulator circuit writes data to a memory cell before lowering the voltage of the external power supply, and reads the data of the memory cell by lowering the voltage of the external power supply to return to the original voltage. 2. The standby system for a semiconductor memory device according to claim 1, wherein the data written is compared with the read data to detect a data retention defect. 6. The memory control circuit according to claim 1, wherein the memory control circuit outputs to the regulator circuit a control signal for causing the regulator circuit to drop the voltage of the external power supply to the unused chip. A standby system for the semiconductor memory device according to claim 1. 7. A standby method for a semiconductor memory device in which a plurality of chips connected to an external power supply are provided with memory cells of a static RAM, respectively, wherein a voltage of the external power supply supplied to the memory cells of the chip is reduced. Setting a standby state of the memory cell, and setting a standby state of the memory cell when a data retention failure is detected.