KR100630524B1 - Word line driving circuit with improved test signal path and semiconductor memory device with the same - Google Patents

Abstract

The present invention relates to a word line driving circuit having an improved test signal path and a semiconductor memory device including the same, wherein the word line driving circuit according to the present invention is connected to the word lines of the memory bank one by one, and is in a test mode. First to J (J is integer) word line drivers for enabling a word line corresponding to itself in response to the test control signal And first through J-th delay circuits respectively delaying a test control signal input to each of the second through J-th word line drivers in a test mode for a predetermined time. In the present invention, by enabling the word lines sequentially during the test operation, it is possible to prevent the power supply voltage from dropping and to reduce the peak current and the noise caused by the power supply voltage drop, thereby more accurately testing the semiconductor memory device. .

Word Line Driver Circuits, Test Control Signals, Memory Banks, Word Line Drivers

Description

Word line driving circuit with improved test signal path and semiconductor memory device including same

1 is a block diagram of a conventional word line driver circuit and a memory bank.

FIG. 2 is a timing diagram of signals related to the operation of the word line driver circuit shown in FIG. 1.

3 is a block diagram of a word line driver circuit and a memory bank according to an exemplary embodiment of the present invention.

4 is a detailed circuit diagram of the delay circuit shown in FIG. 3.

FIG. 5 is a timing diagram of signals related to the operation of the word line driver circuit shown in FIG. 3.

6 is a block diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

110, 221-224: word line driver circuit

120, 211-214: memory bank

DR1-DRJ: Word Line Driver

DL1-DL (J-1): Delay Circuit

231-233: main delay circuit

The present invention relates to a semiconductor device, and more particularly, to a word line driver circuit and a semiconductor memory device including the same.

In general, a semiconductor memory device manufactured through a series of processes is verified whether or not it operates normally through a test process. As one of the test items for the verification of the semiconductor memory device, there is a test process that repeatedly performs writing and reading operations of data in each memory cell. In this test process, word lines are alternately enabled or entire word lines are simultaneously enabled to stress the word lines connected to the respective memory cells. To this end, a test signal for enabling the entire word lines at one time is input to the word line driver circuit.

1 is a block diagram of a conventional word line driver circuit and a memory bank. Referring to FIG. 1, word line drivers DR1 -DRN (N is an integer) of the word line driver circuit 11 are respectively arranged in word lines WL1 -WLN (N is an integer) of the memory bank 12. Connected. The word line drivers DR1 -DRN simultaneously enable the word lines WL1 -WLN in response to a test control signal TALLWD in a test mode. However, when the word lines WL1 to WLN are simultaneously enabled as shown in FIG. 2, a drop phenomenon of the power supply voltage VPP may be temporarily generated. Referring to FIG. 2, when the word lines WL1 to WLN are simultaneously enabled, the power supply voltage VPP drops to the voltage VDD / 2 level. As a result, there is a problem that other circuits using the voltage VPP may malfunction, thereby obtaining an undesired test result.

Accordingly, an object of the present invention is to provide a word line driving circuit having an improved test signal path that can prevent the power supply voltage from dropping by sequentially enabling word lines during a test operation.

Another object of the present invention is to provide a semiconductor memory device including a word line driving circuit having an improved test signal path that can prevent the power supply voltage from dropping by sequentially enabling word lines during a test operation. It is.

The word line driving circuit according to the present invention for achieving the above technical problem is connected to the word lines of the memory bank one by one, and in response to the test control signal in the test mode, enable the word line corresponding to itself First to J (J is integer) word line drivers; And first through J-th delay circuits respectively delaying a test control signal input to each of the second through J-th word line drivers in a test mode for a predetermined time. The first through J-1 delay circuits are connected in series with each other. The first delay circuit delays the test control signal to output the delayed test control signal to the second delay circuit and the second word line driver, and each of the second to J-1 delay circuits is connected to its input terminal. The delayed test control signal received from the signal is further delayed and output to the delay circuit connected to its output stage and the corresponding word line driver.

In accordance with another aspect of the present invention, a semiconductor memory device is connected to a plurality of memory banks one by one, and sequentially in response to a test control signal in a test mode, word lines of a corresponding memory bank one by one. A plurality of word line driver circuits for enabling the circuits; And main delay circuits respectively delaying a test control signal to be input to some of the plurality of word line driving circuits in a test mode for a predetermined time. Preferably, at least one of the plurality of word line driver circuits directly receives a test control signal prior to being delayed.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a block diagram of a word line driver circuit and a memory bank according to an exemplary embodiment of the present invention. Referring to FIG. 3, the word line driver circuit 110 includes word line drivers DR1-DRJ (J is an integer) and delay circuits DL1-DL (J-1) (J is an integer). . The word line drivers DR1 to DRJ are connected to the word lines WL1 to WLJ (J is an integer) of the memory bank 120. The word line drivers DR1-DRJ respond to test control signals TALLWD and TALLWD1-TALLWD (J-1) (J is an integer) in a test mode, respectively, and correspond to the corresponding word lines WL1-WLJ. Enable each). In addition, the word line drivers DR1 to DRJ respectively respond to the word line enable signals WD1 to WDJ (where J is an integer) in the normal mode to respectively correspond to the corresponding word lines WL1 to WLJ. Enable. The delay circuits DL1-DL (J-1) are connected in series with each other, and output terminals of the delay circuits DL1-DL (J-1) are input terminals of the word line drivers DR2-DRJ. Are further connected to each other. The delay circuit DL1 delays the test control signal TALLWD for a predetermined time and outputs the delayed test control signal TALLWD1 to the delay circuit DL2 and the word line driver DR2. The delay circuit DL2 delays the delayed test control signal TALLWD1 for the set time and outputs the delayed test control signal TALLWD2 to the delay circuit DL3 and the word line driver DR3. do. The delay circuits DL3-DL (J-1) also operate similarly to the delay circuits DL1 and DL2, so that the delayed test control signals TALLWD3-TALLWD (J-1) may be respectively applied to the word line. Output to the drivers DR3-DRJ. As a result, as the test control signal TALLWD is delayed by the delay circuits DL1-DL (J-1), respectively, the test control signal is sequentially applied to the word line drivers DR1-DRJ. (TALLWD) is entered. Accordingly, the word line drivers DR1 to DRJ sequentially enable the word lines WL1 to WLJ.

Next, a configuration and detailed operation of the delay circuits DL1 -DL (J-1) will be described with reference to FIG. 4. In FIG. 4, an embodiment of the delay circuit DL1 is illustrated. Since the configuration and specific operation of the delay circuits DL2-DL (J-1) are similar to the delay circuit DL1, the operation of the delay circuit DL1 will be described. The delay circuit DL1 includes a delay unit 130 and a driver 140. The delay unit DL1 includes PMOS transistors P1-P3, NMOS transistors N1-N3, resistors R1 and R2, a NAND gate 131, and an inverter 132. When the test control signal TALLWD is enabled, the PMOS transistor P1 is turned off and the NMOS transistor N1 is turned on. As a result, the first internal signal V1 of low level is output from the output node D1. In addition, in response to the first internal signal V1, the PMOS transistor P2 is turned on and the NMOS transistor N2 is turned off. As a result, the second internal signal V2 of high level is output from the output node D2. In this case, the NMOS transistor N3 connected to the output node D1 and the PMOS transistor P3 connected to the output node D2 operate as a capacitor, and the first and second internal signals V1, Delay each V2). The NAND gate 131 outputs a low level logic signal (not shown) in response to the test control signal TALLWD and the second internal signal V2, and the inverter 132 outputs the NAND gate 131. Inverts the output signal, and outputs a high-level logic signal (LOG). The driver 140 includes inverters 141 and 142 and outputs the logic signal LOG as a delayed test control signal TALLWD1.

Next, the operation of the word line driver circuit 100 configured as described above will be described in detail. In the normal mode, a row decoder (not shown) enables one or some of the word line enable signals WD1 -WDJ for a write or read operation of the data. As a result, corresponding word line drivers (one or part of DR1-DRJ) receiving the enabled word line enable signals (one or part of WD1-WDJ) enable the corresponding word lines. On the other hand, in the test mode, a control circuit (not shown) enables the test control signal TALLWD. The test control signal TALLWD is input to the word line driver DR1 and the delay circuit DL1, and the word line driver DR1 responds to the test control signal TALLWD, and thus the word line WL1. Enable). Thereafter, the delay circuit DL1 delays the test control signal TALLWD for a predetermined time and outputs the delayed test control signal TALLWD1 to the delay circuit DL2 and the word line driver DR2. . The word line driver DR2 enables the corresponding word line WL2 in response to the delayed test control signal TALLWD1. The delay circuit DL2 delays the delayed test control signal TALLWD1 for the predetermined time and outputs the delayed test control signal TALLWD2 to the delay circuit DL3 and the word line driver DR3. Thereafter, the word line drivers DR3-DRJ and the delay circuits DL3-DL (J-1) operate similarly to those described above. As a result, as shown in FIG. 5, the word lines WL1 to WLJ are sequentially enabled at set time intervals. Therefore, the power supply voltage VPP can be prevented from being momentarily lowered below the operating voltage. In addition, since the word lines WL1-WLJ are sequentially enabled, the peak current and noise generated in the word lines WL1-WLJ are reduced so that memory cells can be accurately tested.

6 is a block diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 6, the semiconductor memory device 200 may include memory banks 211-214, word line driving circuits 221-224, and main delay circuits 231-233. In FIG. 6, for the sake of simplicity, the drawings of other detailed circuit blocks of the semiconductor memory device 200 are omitted, and operations related to the omitted internal circuit blocks may be understood by those skilled in the art. Therefore, detailed description thereof will also be omitted. In addition, although only four memory banks and word line driving circuits and three main delay circuits are illustrated in FIG. 6, the memory bank, the word line driving circuit, and the main delay circuits included in the semiconductor memory device 200 are illustrated. The number can be increased or decreased as needed. The word line driving circuits 221-224 are respectively connected to the memory banks 211-214 one by one. The word line driving circuits 221-224 respectively respond to the test control signals TALLWD, TALLWD ', TALLWD' ', and TALLWD' '' in a test mode, so as to correspond to word lines (not shown) of a corresponding memory bank. ) Sequentially enable one by one. Further, the word line driving circuits 221-224 respectively respond to word line enable signals WD11-WD1J, WD21-WD2J, WD31-WD3J, and WD41-WD4J (J is an integer) in the normal mode. Enables one or some of the word lines of the corresponding memory bank. Here, since the configuration and specific operation of each of the word line driving circuits 221 to 224 are substantially the same as the word line driving circuit 110 described above with reference to FIG. 3, a detailed description thereof will be omitted. .

The main delay circuits 231, 232, and 233 are connected in series with each other, and output terminals of the main delay circuits 231, 232, and 233 are respectively connected to input terminals of the word line driving circuits 221-224. More connected. The main delay circuit 231 delays the test control signal TALLWD for a predetermined time and outputs the delayed test control signal TALLWD 'to the main delay circuit 232 and the word line driver circuit 222. do. The main delay circuit 232 delays the delayed test control signal TALLWD 'for the set time and drives the delayed test control signal TALLWD &quot; with the main delay circuit 233 and the word line. It outputs to the circuit 223. In addition, the main delay circuit 233 delays the delayed test control signal TALLWD '' for the set time and outputs the delayed test control signal TALLWD '' 'to the word line driving circuit 224. do. As a result, as the test control signal TALLWD is delayed by the main delay circuits 231, 232, and 233, respectively, the test control signal (sequential to the word line driving circuits 221-224). TALLWD) is entered. Accordingly, the word line driving circuits 221-224 sequentially enable word lines of the corresponding memory banks 211-214. Here, since the configuration and detailed operation of the main delay circuits 231, 232, and 233 are similar to those of the delay circuit DL1 described above with reference to FIG. 4, a detailed description thereof will be omitted.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, since the word lines are sequentially enabled during the test operation, the power supply voltage can be prevented from dropping, and the peak current and the noise due to the power supply voltage drop can be reduced, thereby providing a semiconductor memory. Test your device more accurately.

Claims (14)

In a word line driving circuit of a semiconductor memory device, First to J (J is integer) word line drivers connected correspondingly to the word lines of the memory bank one by one and enabling a word line corresponding to the word line in response to a test control signal in a test mode; And First to J-th delay circuits respectively delaying the test control signal to be input to each of the second to J-th word line drivers in the test mode for a predetermined time period; The first to J-1 delay circuits are connected in series with each other, and the first delay circuit delays the test control signal to output a delayed test control signal to the second delay circuit and the second word line driver. Each of the second through J-1 delay circuits further delays a delayed test control signal received from a delay circuit connected to an input terminal thereof, and outputs the delayed test control signal connected to its output terminal and a word line driver corresponding thereto. Word line driving circuit. The method of claim 1, Each of the first to J-th word line drivers enables a word line corresponding to the word line enable signal in response to a word line enable signal in a normal mode. The method of claim 1, And the first to Jth word line drivers respectively enable the word lines one by one at the set time interval in response to the test control signal. delete The method of claim 1, Each of the first to J-1 delay circuits includes A delay unit delaying an input test control signal for the set time; And And a driver for receiving an output signal of the delay unit and outputting the received signal to a corresponding word line driver as the delayed test control signal. In a semiconductor memory device including a plurality of memory banks, A plurality of word line driver circuits correspondingly connected to each of the plurality of memory banks and sequentially enabling word lines of a corresponding memory bank one by one in response to a test control signal in a test mode; And Main delay circuits for respectively delaying the test control signal to be input to some of the plurality of word line driving circuits in the test mode for a first set time; At least one of the plurality of word line driver circuits directly receives the test control signal prior to being delayed. The method of claim 6, Each of the plurality of word line driver circuits enable one or some of the word lines of the corresponding memory bank in response to word line enable signals, respectively, in a normal mode. The method of claim 6, wherein each of the plurality of word line driver circuits, First to J (J is integer) word line drivers correspondingly connected to word lines of a memory bank corresponding to the corresponding one, and enabling a word line corresponding to the corresponding word line in response to the test control signal; And And first to J-th delay circuits respectively delaying the test control signal to be input to each of the second to J-th word line drivers for a second set time in the test mode. The method of claim 8, And each of the first through J-1 word line drivers enables the corresponding word line in response to a word line enable signal in a normal mode. The method of claim 8, And the first to Jth word line drivers respectively enable the word lines one by one at the second set time interval in response to the test control signal. The method of claim 8, The first to J-1 delay circuits are connected in series with each other, and the first delay circuit delays the test control signal to output a delayed test control signal to the second delay circuit and the second word line driver. Each of the second to J-1 delay circuits further delays a delayed test control signal received from a delay circuit connected to an input terminal and outputs the delayed test control signal to a word line driver corresponding to the delay circuit connected to an output terminal. The method of claim 8, Each of the first to J-1 delay circuits includes A delay unit delaying an input test control signal for the second predetermined time; And And a driver for receiving the output signal of the delay unit and outputting the received signal to the corresponding word line driver as the delayed test control signal. The method of claim 8, Each of the main delay circuits, A delay unit delaying an input test control signal for the first predetermined time; And And a driver that receives an output signal of the delay unit and outputs the received signal to a corresponding word line driver circuit as the delayed test control signal. In a word line driving circuit of a semiconductor memory device, A first word line driver coupled to the first word line and enabling the first word line in response to a test control signal in a test mode; A first delay circuit for delaying the test control signal for a first set time and outputting a first delay test control signal; A second word line driver for enabling a second word line in response to the first delay test control signal; A second delay circuit for delaying the first delay test control signal for a second set time and outputting a second delay test control signal; And And a third word line driver for enabling a third word line in response to the second delay test control signal.

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