JPH01241100A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To relieve a faulty bit in an unused area so as to improve the yield of a semiconductor memory by causing the memory to incorporate a decoder circuit composed of information writable storage elements and, when the unused area is produced, writing the address information of the unused area in the decoder circuit at the time of manufacture and detecting the address pattern corresponding to the unused area so as to control the data. CONSTITUTION:It is assumed that the addresses 1,000-1FFF of the memory space of a mask ROM 1 are an unused area 11 and addresses 30,000-32FFF are another unused area 11. Decoders 2 and 4 are provided to the mask ROM so that no wrong data can be outputted even if the addresses of the unused area 11 and 12 are designated when faults of memory cells take place in such unused areas 11 and 12. Since a faulty bit can be relieved by controlling the readout of information even if the faulty bit is contained in the unused areas when an address signal designating the unused areas is inputted as mentioned above, the yield of this memory can be increased without increasing the chip area.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory, and particularly relates to a semiconductor memory such as a mask ROM in which information is written during the manufacturing stage and has a built-in decoder to improve yield. .

[Prior Art and Problems to be Solved by the Invention] Recently, various methods have been used to improve the yield of mask ROMs as dimensions become smaller and storage capacities become larger. As the method described in Section 1, mask ROMs with built-in error correction circuits have been partially put into practical use. However, this method has the disadvantage that the chip area increases by more than 20% due to the built-in test bits.

As a second method, a spare array used in RAM or the like is provided, and if there is a defective array, it is replaced with the spare array. However, in the case of a mask ROM, information is written at the manufacturing stage, making it difficult to apply.

On the other hand, as capacity increases, the possibility that the entire memory space will not be used and unused areas will occur is increasing, and if a defective bit occurs in an unused area, the area that will not actually be accessed is increased. Therefore, even though there is no practical problem, it is difficult to distinguish between the used area and the unused area during the shipping test, so there is a problem that the product must be treated as a defective product.

Therefore, the main object of the present invention is to provide a built-in decoder circuit consisting of a memory element in which information can be written, so that when an unused area occurs, the address information of this area is transferred to the decoder circuit during manufacturing. An object of the present invention is to provide a semiconductor memory capable of controlling data by detecting an address pattern corresponding to an unused area for writing.

[Means for Solving the Problems] The present invention relates to a semiconductor memory in which information is written at the manufacturing stage, in which data indicating an area where no information is written is written in advance, and an address signal indicating a corresponding area is used. The device is configured to include a decoder that controls the reading of information in response to the input of the information.

[Operation] The semiconductor memory according to the present invention controls the reading of information when an address signal indicating an unused area is input, so that even if the unused area contains a defective bit, it can be repaired. Therefore, it is possible to improve the yield without increasing the chip area.

[Embodiment of the Invention] FIG. 1 is an electric circuit diagram showing a decoder included in an embodiment of the invention, and FIG. 2 is a diagram showing a storage area of a mask ROM.

As shown in FIG. 2, in the memory space of the mask ROMI, addresses 1000 to IFFF are unused areas 11, and addresses 30000 to 32FFF are unused areas 12.
Assume that If there is a defective memory cell in such an unused area 11.12, the unused area 1
In order to prevent erroneous data from being output even if 1.12 is addressed, decoders 2 and 4 as shown in FIG. 1 are provided in the mask ROM. Decoder 2 specifies unused area 11, and decoder 4 specifies unused area 1.
2 is specified.

In the decoder 2, transistors 21 to 26 (high VTH) which switch at a relatively high input voltage are connected in series, and the drain of the transistor 21 is a P-channel MOS.
It is connected to the power supply +V via transistor 6, and the source of transistor 26 is grounded via an enhancement transistor 37 that switches at a relatively low input voltage.

Address signals A18-A12 are applied to each gate of each transistor 21-26 and 37.

Furthermore, enhancement transistors 31 to 36 are connected in series, with the drain of transistor 31 being connected to the source of transistor 6, and the transistor 36 connected in series.
The source of is grounded through a high VTH transistor 27. Addresses 1a A18-A12 are given to the gates of transistors 31-36 and 27, respectively. Note that the drain of the transistor 22 and the source of the transistor 31.

The drain of transistor 23 and the source of transistor 32, the drain of transistor 24 and the source of transistor 33, the drain of transistor 25 and transistor 3
The source of transistor 4, the drain of transistor 26 and the source of transistor 35, and the drain of transistor 37 and the source of transistor 36 are connected, respectively.

On the other hand, the decoder 4 includes high VTN transistors 41° enhancement transistors 52, 53 . High VTN transistors 44, 45. An enhancement transistor 56 and a high voltage transistor 47 are connected in series, and the drain of the transistor 41 is connected to the transistor 6.
The source of the transistor 47 is grounded. And each transistor 41, 52, 53, 4
Address signals A18-A12 are applied to each gate of 4, 45° 56 and 47. Further, an enhancement transistor 51. High vTH transistor 42.43
．． Enhancement transistor 54°55, high VTH
) The transistor 46 and the enhancement transistor 57 are each connected in series, the drain of the transistor 51 is connected to the source of the transistor 6, and the source of the transistor 57 is grounded. And transistor 5
Address signals A18-A12 are applied to each gate of 1.42.43.54, 55.46 and 57.

Furthermore, the drain of the transistor 52 and the transistor 5
1 source, the drain of transistor 53 and the source of transistor 42, the drain of transistor 44 and the source of transistor 43, the drain of transistor 45 and the source of transistor 54, the drain of transistor 56 and the source of transistor 55, and the train of transistor 47 and the transistor 46 sources are each connected. Further, one input terminal of an AND gate 7 is connected to the source of the transistor 6, and the output data of the sense amplifier is applied to the other input terminal of the AND gate 7. The output of AND gate 7 is outputted as output data via output buffer 8.

Although not shown, the mask ROMI is addressed by address signals AO to A18, and A12 to A18 degrees of the address signals A12 to A18 are applied to the above-mentioned decoder 2.4.

Next, the operation will be explained. Now address signal A12
"H", A12 "L", A13 to A18 "L",
When A12 to A18 are set to 'H', transistor 3
1 to 37 become conductive, transistors 21 to 27 become non-conductive, one input terminal of AND gate 7 becomes "L", the gate is closed, and the output data of the sense amplifier is no longer output. That is, the output of the AND gate 7 becomes, for example, "H" in the same way as the unused data.

Therefore, even if the unused area 11 of the mask ROMI is addressed by the address signals AO to A18 and erroneous data is read, the AND gate 7 prevents the data from being output.

Similarly, address signals A17, 16.1312 are
When set to Hs, the transistors 51 to 57 become conductive, and one input terminal of the AND gate 7 becomes 'L' level, and the AND gate 7 is closed. Even if the used area 12 is addressed, incorrect data will not be output.

[Effects of the Invention] As described above, according to the present invention, a decoder is provided in which data indicating an area in which no information is written is written in advance, and an address signal indicating a corresponding area is input. Since reading of information is controlled accordingly, defective bits in unused areas can be repaired and yield can be improved.

′ Moreover, the same effect can be achieved not only when applied to unused areas, but also when areas containing the same data are occupied. Note that the decoder can be placed in the empty space of the input/output circuit around the memory array, and it is possible to improve the yield without increasing the chip area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing an unused area of the mask ROM. In the figure, 1 is a mask ROM, 2.4 is a decoder, and 6
is a P-channel MOS transistor, 7 is an AND gate,
8 is an output buffer, 11.12 is an unused area, 21 to 2
7. 41 to 47 are enhancement transistors, 31
~37.51-57 indicate high VT+ transistors.

Claims (1)

[Claims] In a semiconductor memory in which information is written during the manufacturing stage, data indicating an area where no information is written is written in advance, and in response to input of an address signal indicating the corresponding area. , equipped with a decoder that controls the reading of information,
semiconductor memory.