JP2000260871A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent damage and opening defect of a substrate, when a plurality of contact holes with different depths are formed simultaneously by a method, wherein two or more kinds of insulating films with different etching rates are used. SOLUTION: This manufacturing method is provided with a process, in which a first interlayer insulating film 1 is formed on a substrate pattern in a semiconductor substrate 20, on which the substrate pattern having a step, is formed, a process in which a second interlayer insulating film 2 is formed on the first interlayer insulating film, the method is provided with a process in which the surface of the second interlayer insulating film 2 is flattened, the method is provided with a process in which a plurality of contact holes, with different depths, reaching the substrate pattern are made so as to pass the first and second interlayer insulating films. The etching rate of the first interlayer insulating film 1 and the etching rate of the second interlayer insulating film 2 under the same etching conditions are constituted so as to be different. In addition, when the surface of the second interlayer insulating film 2 is flattened by a chemical mechanical polishing(CMP), the first interlayer insulating film 1 acts as a stopper film of the CMP operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of forming a plurality of contact holes having different depths.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device having a plurality of contact holes having different depths from each other will be described below.
This will be described by taking an iCMOS process as an example.

The BiCMOS process technology is a technology for simultaneously forming a bipolar transistor and a MOS transistor on the same semiconductor substrate, and is used for manufacturing an analog-digital mixed LSI or the like.

FIG. 4 is a cross-sectional view of a representative device manufactured by a BiCMOS process when a bipolar transistor generally called a two-layer polysilicon self-aligned structure is provided. FIG. 4A shows a chemical mechanical polishing (C
FIG. 4B shows a case where the insulating film is flattened by MP) or etch back, and FIG. 4B shows a case where the insulating film is not flattened.

As shown in FIG. 4A, in a bipolar transistor portion 9 having a two-layer polysilicon self-aligned structure, an electrical connection between an emitter region 12 and a base region 14 is made in order to form an active region of the transistor finely. To connect
The polysilicon electrodes 11 and 13 are used as extraction electrodes. In particular, since the emitter polysilicon electrode 11 is formed in a portion where the base polysilicon electrode 13 is opened,
The portion of the emitter polysilicon electrode 11 becomes higher. As a result, the pattern of the bipolar transistor section 9 is relatively higher than that of the MOS transistor section 10, and a step occurs.

As described above, when the insulating film 15 is formed on the underlying pattern having a step, as shown in FIG.
The step h of the insulating film is generated according to the step g of the underlying pattern. If this step is equal to or greater than the depth of focus of the exposure apparatus, the resolution of the resist pattern is reduced when the resist is patterned by lithography in order to form the contact holes 16a, 16b, 16c, and 16d and a wiring pattern in a later step. This causes a defect.

Therefore, in order to increase the focus margin when patterning a resist by lithography, reflow by heat treatment, overall etch back by dry etching, and a CMP process are used.
The surface of the insulating film is planarized. Therefore, FIG.
By performing the flattening process as shown in (a), the thickness of the interlayer insulating film 15 varies depending on the positions where the contact holes 16a, 16b, 16c, and 16d are opened.

In particular, as the lithography becomes finer, the depth of focus becomes shallower, so that a CMP process capable of completely flattening the wafer surface is often used.
For this reason, the difference in the thickness of the insulating film due to the step of the underlying pattern becomes remarkable, and a technique for simultaneously forming a plurality of contact holes having different depths is required.

[0009]

Since the conventional semiconductor device is configured as described above, the contact hole 16d whose opening depth is relatively deep as shown in FIG. Relatively shallow contact hole 16
When both are processed by etching simultaneously, if the etching time is set so that the contact hole 16d having a large opening depth can be sufficiently opened, excessive etching is performed in the contact hole 16a having a small opening depth. Progresses, and the underlying pattern is damaged due to an increase in the amount of over-etching.

On the other hand, a contact hole 16a having a small depth
If the etching time is set so that the opening can be formed, the etching is completed before the etching proceeds to the underlying pattern in the contact hole 16d having a large depth, resulting in a defective opening of the contact hole.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on a base substrate; A step of forming a film, a step of forming a second insulating film on the first insulating film, a step of flattening the surface of the second insulating film, and the first and second insulating films Forming a plurality of contact holes having different depths to reach the underlying circuit pattern. In the etching for forming the contact hole, the etching rate of the first insulating film is different from the etching rate of the second insulating film under the same etching condition. When planarizing the surface of the second insulating film by CMP,
The first insulating film is configured to function as a CMP stopper film.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a base circuit pattern on a semiconductor substrate having the base circuit pattern having a step formed thereon; A step of forming a second insulating film on the first insulating film, a step of forming a third insulating film on the second insulating film, and a step of flattening the surface of the third insulating film And forming a plurality of contact holes having different depths through the first, second, and third insulating films and reaching the underlying circuit pattern. The second insulating film is configured to have a high etching selectivity under conditions for etching the third insulating film. Further, when the surface of the third insulating film is planarized by CMP, the second insulating film is configured to act as a stopper film of CMP.

[0013] In a method of manufacturing a semiconductor device according to another embodiment of the present invention, in a semiconductor substrate having a stepped base circuit pattern formed thereon, a step of forming a first insulating film on the base pattern; A step of flattening the surface of the first insulating film, a step of removing the first insulating film on a desired region of the base pattern by a desired thickness with a resist mask or the like, and Forming a second insulating film on the film, flattening the surface of the second insulating film, and forming a plurality of depths reaching the underlying circuit pattern through the first and second insulating films. Forming contact holes of different sizes. Under the same etching condition, the etching rate of the first insulating film and the etching rate of the second insulating film are different from each other.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below more specifically with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view of a semiconductor device shown in the order of steps for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Referring to FIG. 1A, a base pattern is formed on a semiconductor substrate 20, and a first interlayer insulating film 1 and a second interlayer insulating film 2 are formed thereon. Here, the thickness a of the second interlayer insulating film 2 is configured to be equal to or larger than the step b of the underlying pattern. Next, the surface of the second interlayer insulating film 2 is flattened by a flattening process such as CMP and etch back.

Here, the shaving amount of the second interlayer insulating film 2 by the flattening process is set to be equal to or less than the film thickness a immediately after the deposition of the second interlayer insulating film. Further, when the surface of the second interlayer insulating film 2 is flattened by CMP, the processing speed of the first interlayer insulating film 1 is sufficiently low under the condition that the second interlayer insulating film 2 is flattened by CMP. First interlayer insulating film 1
Is formed so as to act as a CMP stopper film, as shown in FIG. 1B, the step of the underlying pattern is formed in the contact hole portion having a large opening depth by flattening the second interlayer insulating film. And a structure in which the second interlayer insulating film 2 is buried by the film thickness b due to the above, the film thickness of the flattened insulating film is reduced by the film thickness c of the first insulating film, and the thickness of the underlying pattern. Since the sum of the steps b can be set to (b + c), the thickness of the insulating film after flattening can be accurately controlled.

Next, a resist mask 6 which has been subjected to patterning for opening the contact holes 7a and 7b is formed by lithography. Thereafter, contact holes 7a and 7b are opened by etching. On this occasion,
As shown in FIG. 1C, first, a contact hole 7a having a large opening depth is formed by selectively etching only the second interlayer insulating film 2 without etching the first interlayer insulating film 1. Is etched to the upper part of the first interlayer insulating film 1. Under this condition, since the first interlayer insulating film 1 is not etched, the etching ends when the upper portion of the first interlayer insulating film 1 is exposed. Next, a contact hole 7b having a small opening depth and a contact hole 7a having a large opening depth are simultaneously formed under the conditions for etching the first interlayer insulating film 1. The contact holes 7a and 7b formed by the above steps can be completed at the same time, so that the contact holes 7a and 7b occur in the prior art.
Damage to the underlying pattern due to excessive etching in a contact hole having a shallow opening can be prevented.

Further, by setting the etching conditions so that the etching rate of the second interlayer insulating film 2 is sufficiently higher than that of the first interlayer insulating film 1, the same etching condition can be obtained without changing the etching conditions. Even if the contact holes are etched all at once under the above etching conditions, the etching of the contact holes 7b and 7a having a shallow opening can be completed almost simultaneously, and the formation of the underlying pattern in the shallow contact holes 7b can be completed. Damage can be reduced.

Further, even when there are three or more contact holes having different depths, the etching for forming the contact holes can be completed simultaneously by the manufacturing method of the present invention.

(Second Embodiment) In a second embodiment of the present invention, the interlayer insulating film has a three-layer structure, and the second interlayer insulating film 2 is used as an etching stopper film when forming a contact hole. It is characterized by acting.

FIG. 2 is a sectional view of a semiconductor device shown in the order of steps for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. 2A, a base pattern is formed on a semiconductor substrate 20, and a first interlayer insulating film 1, a second interlayer insulating film 2, and a third interlayer insulating film 8 are formed thereon. . Here, the thickness d of the third interlayer insulating film 8 is configured to be equal to or greater than the step b of the underlying pattern. Next, the surface of the third interlayer insulating film 8 is flattened by a flattening process such as CMP and etch back. Here, the shaving amount of the third interlayer insulating film 8 by the flattening process is set to be equal to or less than the thickness d of the third interlayer insulating film 8. When the surface of the third interlayer insulating film 8 is planarized by CMP, the third interlayer insulating film 8 is
Under the condition of flattening with P, if the processing speed of the second interlayer insulating film 2 is sufficiently low and the second interlayer insulating film 2 is configured to act as a stopper film for CMP, FIG.
As shown in (b), the third interlayer insulating film 8 is formed by a thickness b due to a step of the underlying pattern in a portion where a contact hole 7a having a large opening depth is formed by flattening the third interlayer insulating film 8. 8 can be formed, and the thickness of the insulating film after planarization is reduced by the thickness c of the first insulating film, the thickness e of the second insulating film, and Since the sum (b + c + e) can be obtained, the thickness of the insulating film after planarization can be accurately controlled.

Next, a resist mask 6 which has been subjected to patterning for opening the contact holes 7a and 7b is formed by lithography. Thereafter, contact holes 7a and 7b are opened by etching. On this occasion,
As shown in FIG. 2C, first, a contact hole 7a having a large opening depth is formed by selectively etching only the third interlayer insulating film 8 without etching the second interlayer insulating film 2. Is etched to the upper part of the second interlayer insulating film 2. Under this condition, since the second interlayer insulating film 2 is not etched, the etching ends when the surface of the second interlayer insulating film 2 is exposed. Next, the second interlayer insulating film 2 existing in the contact hole 7b having a small opening depth and the contact hole 7a having a large opening depth is etched under the conditions for etching the second interlayer insulating film 2, and subsequently, Then, contact holes 7a and 7b having different depths are formed depending on the conditions for etching the first interlayer insulating film 1.

The contact holes 7a and 7b formed by the above-described processes can be simultaneously etched in the formation of the contact holes. Damage to the underlying pattern due to excessive etching can be prevented.

Here, the first interlayer insulating film 1 and the third interlayer insulating film 8 may be of the same film type. In the case where a silicon oxide film is used for the first interlayer insulating film 1 and the third interlayer insulating film 8, by using a silicon nitride film as the second interlayer insulating film 2, the processing speed of CMP can be reduced. Extremely slow delay can be easily realized, and the second interlayer insulating film 2 can be used as a CMP stopper film.

(Third Embodiment) In a third embodiment of the present invention, a structure in which a second insulating film having a thickness corresponding to the etching rate ratio is buried above the first insulating film. Is formed, the etching of the contact hole having a shallow opening depth and the etching of the deep contact hole are simultaneously completed.

FIG. 3 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 3A, after a first interlayer insulating film 1 is formed on a semiconductor substrate on which a base pattern is formed, a first interlayer insulating film 1 is formed by a planarization process such as CMP and etch back. The surface of the film 1 is flattened. Next, patterning is performed using a resist mask, and a region including the contact hole 7b having a small depth is removed by a depth f by etching. At this time, as shown in FIG. 3B, the thickness for removing the first interlayer insulating film 1 by etching is f, the etching rate of the first interlayer insulating film 1 is V2, and the second interlayer insulating film 2 is Where V1 is the etching rate and Δh is the difference in the thickness of the insulating film due to the step of the underlying pattern, the etching amount f is set so that f = Δh (V1 / (V2−V1)). . Next, after removing the resist, the second interlayer insulating film 2 is formed, and the CMP is performed.
Then, the surface is flattened by etch back.

Hereinafter, a resist mask 6 which has been patterned to open the contact holes 7a and 7b is formed by lithography, and the contact holes 7a and 7b are opened by etching.

Here, by setting the etching conditions as in the equation, the difference in etching time caused by the difference in depth between the contact hole 7b having a small opening and the contact hole 7a having a large depth can be obtained. It can be eliminated, and damage to the underlying pattern due to overetch can be prevented.

In the same etching condition, when the etching rate of the second interlayer insulating film 2 is higher than that of the first interlayer insulating film 1, the same method can be used to form a deep contact. A similar effect can be obtained by forming a structure in which the second interlayer insulating film 2 having a high etching rate is buried above the hole 7a.

[0030]

As described above, according to the present invention, by using two or more types of insulating films having different etching rates, the etching for forming the contact holes can be simultaneously completed regardless of the opening depth of the contact holes. This can prevent damage to the base and poor opening when simultaneously forming a plurality of contact holes having different depths.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device shown in the order of steps for explaining a first embodiment of the present invention;

FIG. 2 is a sectional view of a semiconductor device shown in the order of steps for explaining a second embodiment of the present invention;

FIG. 3 is a sectional view of a semiconductor device shown in order of steps for describing a third embodiment of the present invention;

FIG. 4 is a cross-sectional view of a semiconductor device for describing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 First interlayer insulating film 2 Second interlayer insulating film 3 Polysilicon electrode 4 Field insulating film 5 Diffusion layer 6 Resist mask 7a, 7b Contact hole 8 Third interlayer insulating film 20 Semiconductor substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/90 ACF term (Reference) 4M104 BB01 DD05 DD08 DD16 DD17 DD67 DD72 DD75 EE08 EE12 EE17 FF21 FF27 GG14 GG15 5F004 AA03 AA11 EA23 EA28 EB01 5F033 KK01 KK04 QQ09 QQ11 QQ21 QQ25 QQ31 QQ35 QQ39 QQ48 QQ49 RR04 RR06 TT02 XX00

Claims (5)

[Claims] A step of forming a first insulating film on the base pattern on a semiconductor substrate on which a base pattern having a step is formed; and forming a second insulating film on the first insulating film. Forming, flattening the surface of the second insulating film, and forming a plurality of contact holes having different depths reaching the base pattern through the first and second insulating films. A method of manufacturing a semiconductor device, comprising: a step of etching a first insulating film under an identical etching condition; and a step of etching a second insulating film under the same etching condition. 2. The method according to claim 1, wherein the second insulating film is chemically mechanically polished (C
MP), the processing speed of the first insulating film is sufficiently low, and the first insulating film
2. The film according to claim 1, wherein said film acts as a stopper film.
The manufacturing method of the semiconductor device described in the above. 3. A step of forming a first insulating film on the base pattern on a semiconductor substrate on which a base pattern having a step is formed, and forming a second insulating film on the first insulating film. A step, a step of forming a third insulating film on the second insulating film, a step of flattening the surface of the third insulating film, and the first, second, and third insulating films Forming a plurality of contact holes having different depths reaching the underlying pattern through the substrate, wherein the second insulating film is etched under the condition of etching the third insulating film. A method of manufacturing a semiconductor device having a high etching selectivity. 4. Under the condition that the third insulating film is planarized by CMP, the processing speed of the second insulating film is sufficiently low, and the second insulating film acts as a CMP stopper film. The method for manufacturing a semiconductor device according to claim 3, wherein: 5. A step of forming a first insulating film on the underlying pattern on a semiconductor substrate on which an underlying pattern having a step is formed; and flattening a surface of the first insulating film; A step of removing the first insulating film on a desired region of the base pattern by a desired thickness, a step of forming a second insulating film on the first insulating film, and a step of forming the second insulating film A method of manufacturing a semiconductor device, comprising: a step of flattening a surface of a semiconductor device; and a step of forming a plurality of contact holes having different depths reaching the base pattern through the first and second insulating films. A method of manufacturing a semiconductor device, wherein an etching rate of the first insulating film is different from an etching rate of the second insulating film under the same etching condition.