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KR100587036B1 - Contact formation method of semiconductor device - Google Patents

Contact formation method of semiconductor device Download PDF

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Publication number
KR100587036B1
KR100587036B1 KR1019990046340A KR19990046340A KR100587036B1 KR 100587036 B1 KR100587036 B1 KR 100587036B1 KR 1019990046340 A KR1019990046340 A KR 1019990046340A KR 19990046340 A KR19990046340 A KR 19990046340A KR 100587036 B1 KR100587036 B1 KR 100587036B1
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contact
film
forming
etching
insulating
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KR20010038381A (en
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정성웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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    • H01L21/02104—Forming layers
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract

본 발명은 반도체소자의 컨택 형성방법에 관한 것으로, 종래 반도체소자의 컨택 형성방법은 컨택이 형성되는 산화막이 복잡하고 미세한 구조물 상부에 증착되면서 약한 부분이 생기게 되고, 이 부분이 컨택홀 형성시 오버식각되면서 보이드가 발생하여 주변 컨택과 단락이 발생 할 수 있으며, 컨택홀 형성 시 캡질화막에 손상을 입혀 워드라인과 컨택이 단락될 수 있으므로 캡질화막의 높이를 확보함에 따라 게이트의 높이가 높아져 종횡비가 증가하는 문제점이 있었다. 따라서, 본 발명은 모스 트랜지스터가 형성된 반도체기판 상부에 식각이 빠른 제 1절연막을 증착하는 희생층 형성공정과; 상기 제 1절연막 상부에 감광막을 도포하고 상기 모스 트랜지스터의 공통 소스/드레인영역을 포함한 소정의 위치에만 감광막이 남도록 패터닝 한 후 이를 마스크로 제 1절연막을 건식식각하여 제거하는 컨택설정공정과; 상기 감광막을 제거하고, 상기 형성한 구조물 상부전면에 식각이 느린 제 2절연막을 증착하고 상기 제 1절연막이 드러나도록 평탄화하는 절연막 형성공정과; 상기 제 1절연막을 소스/드레인영역이 드러나도록 식각하는 컨택홀 형성공정과; 상기 형성한 구조물의 상부전면에 폴리실리콘을 증착하고, 상기 제 2절연막이 드러나도록 에치백하여 평탄화하는 컨택 형성공정으로 이루어지는 반도체소자의 컨택 형성방법을 통해 컨택홀이 형성되는 과정에서 보이드가 발생하지 않으므로 컨택간 단락을 방지할 뿐만 아니라 컨택홀 주변소자에 손상을 주지 않으므로 워드라인과 컨택간을 절연하는 캡질화막의 두께를 줄일 수 있는 효과가 있다.The present invention relates to a method for forming a contact of a semiconductor device, in the conventional method of forming a contact of a semiconductor device, the oxide film on which a contact is formed is deposited on a complicated and fine structure, and a weak portion is formed. As a result, voids may occur and peripheral contacts and short circuits may occur. When forming a contact hole, the cap nitride layer may be damaged and the word line and the contact may be shorted. There was a problem. Accordingly, the present invention provides a sacrificial layer forming process of depositing a first etching film having a rapid etching on a semiconductor substrate on which a MOS transistor is formed; A contact setting step of applying a photoresist film over the first insulation film, patterning the photoresist film to remain only at a predetermined position including a common source / drain region of the MOS transistor, and then dry etching and removing the first insulation film with a mask; An insulating film forming step of removing the photoresist film, depositing a second etch film having a slow etching on the upper surface of the formed structure, and planarizing the first insulating film to be exposed; Forming a contact hole to etch the first insulating layer to expose a source / drain region; Voids are not generated in the process of forming a contact hole through a contact forming method of a semiconductor device comprising a contact forming process of depositing polysilicon on the upper surface of the formed structure and etching back to planarize the second insulating layer to be exposed. Therefore, not only prevents short-circuits between the contacts but also does not damage the peripheral elements of the contact holes, thereby reducing the thickness of the cap nitride layer insulating the word line and the contact.

Description

반도체소자의 컨택 형성방법{CONTACT FORMATION METHOD OF SEMICONDUCTOR DEVICE} CONTACT FORMATION METHOD OF SEMICONDUCTOR DEVICE

도 1은 종래 반도체소자의 컨택 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for forming a contact of a semiconductor device.

도 2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***

10 : 반도체기판 20 : 1차 절연막10: semiconductor substrate 20: primary insulating film

30 : 2차 절연막 40 : 폴리실리콘30: secondary insulating film 40: polysilicon

PR10 : 감광막 PR10: photosensitive film

본 발명은 반도체소자의 컨택 형성방법에 관한 것으로, 특히 희생층을 이용하여 컨택홀 형성시 주변소자에 손상을 주지 않고 주변 컨택간 단락을 방지하기에 적당하도록 한 반도체소자의 컨택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device suitable for preventing a short circuit between peripheral contacts without damaging the peripheral device when forming a contact hole using a sacrificial layer. .

종래 반도체소자의 컨택 형성방법을 도 1a 내지 도 1c의 수순단면도를 참고로 하여 설명하면 다음과 같다. A method of forming a contact of a conventional semiconductor device will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1C.

모스 트랜지스터(MT1,MT2)가 형성된 반도체기판(1) 상부에 절연막(2)을 증착하는 절연막 형성공정과; 상기 절연막(2) 상부에 감광막(PR1)을 도포하고 상기 모스트랜지스터(MT1,MT2)의 공통 소스/드레인영역(S/D1)위치에 맞도록 패터닝 한 후 이를 마스크로 공통 소스/드레인영역(S/D1)이 드러나도록 건식식각하는 컨택홀 형성공정과; 상기 감광막(PR1)을 제거하고, 상기 형성된 구조물의 상부전면에 폴리실리콘(3)을 증착하고, 상기 절연막(2)이 드러나도록 에치백하여 평탄화하는 컨택 형성공정으로 이루어진다. An insulating film forming step of depositing an insulating film 2 on the semiconductor substrate 1 on which the MOS transistors MT1 and MT2 are formed; The photoresist film PR1 is coated on the insulating layer 2 and patterned to match the common source / drain regions S / D1 of the MOS transistors MT1 and MT2, and then the common source / drain regions S are used as a mask. A contact hole forming process for dry etching to reveal D1); The photoresist film PR1 is removed, a polysilicon 3 is deposited on the upper surface of the formed structure, and the contact forming process is etched back so that the insulating film 2 is exposed and planarized.

먼저, 도 1a에 도시한 바와같이 모스 트랜지스터(MT1,MT2)가 형성된 반도체기판(1) 상부에 절연막(2)을 증착한다. First, as shown in FIG. 1A, an insulating film 2 is deposited on the semiconductor substrate 1 on which the MOS transistors MT1 and MT2 are formed.

그 다음, 도 1b에 도시한 바와같이 상기 절연막(2) 상부에 감광막(PR1)을 도포하고 상기 좌측 모스 트랜지스터(MT1)와 우측 모스 트랜지스터(MT2)가 공통으로 사용하는 소스/드레인영역(S/D1)과 전기적으로 연결되는 컨택을 형성하기 위해서 상 기 소스/드레인영역(S/D1)의 위치를 중심으로 상기 각 모스 트랜지스터(MT1,MT2)의 게이트 일부가 식각영역에 포함되도록 감광막(PR1)을 패터닝한 후 이를 이용하여 상기 소스/드레인영역(S/D1)이 드러나도록 절연막(2)을 식각하여 컨택홀을 형성한다. Next, as shown in FIG. 1B, a photoresist film PR1 is coated on the insulating film 2, and a source / drain region S / which is commonly used by the left MOS transistor MT1 and the right MOS transistor MT2. In order to form a contact electrically connected to D1), the photoresist film PR1 is formed such that a part of the gate of each of the MOS transistors MT1 and MT2 is included in the etching region based on the position of the source / drain regions S / D1. After patterning, the insulating layer 2 is etched to expose the source / drain regions S / D1 to form contact holes.

상기와 같은 자기정렬 컨택 식각방법은 모스 트랜지스터의 게이트 사이의 모든 영역을 컨택홀로 사용할 수 있는 이점과 함께 게이트의 도전막(워드라인)을 보호하는 캡질화막(a)을 손상시킬 수 있는 단점이 있다. The self-aligned contact etching method as described above has the advantage that all regions between the gates of the MOS transistors can be used as contact holes, and can also damage the cap nitride layer (a) protecting the conductive film (word line) of the gate. .

그 다음, 도 1c에 도시한 바와같이 상기 감광막(PR1)을 제거하고, 상기 형성된 구조물 상부전면에 폴리실리콘(3)을 증착하고 이를 상기 절연막(2)이 드러나도록 에치백하여 컨택을 형성한다.Next, as shown in FIG. 1C, the photoresist film PR1 is removed, and polysilicon 3 is deposited on the entire upper surface of the formed structure and etched back to expose the insulating film 2 to form a contact.

그러나, 상기한 바와같은 종래 반도체소자의 컨택 형성방법은 컨택이 형성되는 산화막이 복잡하고 미세한 구조물 상부에 증착되면서 약한 부분이 생기게 되고, 이 부분이 컨택홀 형성시 오버식각되면서 보이드가 발생하여 주변 컨택과 단락이 발생 할 수 있으며, 컨택홀 형성 시 캡질화막에 손상을 입혀 워드라인과 컨택이 단락될 수 있으므로 캡질화막의 높이를 확보함에 따라 게이트의 높이가 높아져 종횡비가 증가하는 문제점이 있었다.However, in the conventional method of forming a contact of a semiconductor device as described above, a weak portion is formed while the oxide film on which the contact is formed is deposited on a complicated and fine structure, and the portion is over-etched during the formation of the contact hole, thereby generating a void. There is a problem that the short circuit may occur, the word line and the contact may be short-circuited due to damage to the cap nitride layer when forming the contact hole, so that the height of the gate is increased to secure the height of the cap nitride layer, thereby increasing the aspect ratio.

본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 식각비가 다른 희생층을 이용하여 컨택홀 형성시 기 형성된 소자에 손상을 주지 않으면서도 게이트 사이의 모든 영역을 컨택으로 사용할 수 있는 반도체소자의 컨택 형성방법을 제공하는데 있다. The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to use all sacrificial layers having different etching ratios without damaging the devices formed when forming contact holes. It is to provide a contact forming method of a semiconductor device that can be used as a contact.

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 컨택 형성방법은 모스 트랜지스터가 형성된 반도체기판 상부에 일반 산화막에 비해 100배 이상의 빠른 식각 속도를 갖는 제 1절연막을 증착하는 희생층 형성공정과; 상기 제 1절연막 상부에 감광막을 도포하고 상기 모스 트랜지스터의 공통 소스/드레인영역을 포함한 소정의 위치에만 감광막이 남도록 패터닝 한 후 이를 마스크로 제 1절연막을 건식식각하여 제거하는 컨택설정공정과; 상기 감광막을 제거하고, 상기 형성한 구조물 상부전면에 식각이 느린 제 2절연막을 증착하고 상기 제 1절연막이 드러나도록 평탄화하는 절연막 형성공정과; 상기 제 1절연막을 소스/드레인영역이 드러나도록 식각하는 컨택홀 형성공정과; 상기 형성한 구조물의 상부전면에 폴리실리콘을 증착하고, 상기 제 2절연막이 드러나도록 에치백하여 평탄화하는 컨택 형성공정으로 이루어지는 것을 특징으로한다.The contact forming method of the semiconductor device for achieving the object of the present invention as described above is a sacrificial layer forming process of depositing a first insulating film having a etch rate of 100 times faster than a normal oxide film on the semiconductor substrate on which the MOS transistor is formed; ; A contact setting step of applying a photoresist film over the first insulation film, patterning the photoresist film to remain only at a predetermined position including a common source / drain region of the MOS transistor, and then dry etching and removing the first insulation film with a mask; An insulating film forming step of removing the photoresist film, depositing a second etch film having a slow etching on the upper surface of the formed structure, and planarizing the first insulating film to be exposed; Forming a contact hole to etch the first insulating layer to expose a source / drain region; Polysilicon is deposited on the upper surface of the formed structure, and the contact forming process is etched back and planarized so that the second insulating film is exposed.

상기한 바와같은 본 발명에 의한 반도체소자의 컨택 형성방법을 첨부한 도 2a 내지 도 2e의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 2a to 2e with the method of forming a contact of the semiconductor device according to the present invention as described above in detail as an embodiment as follows.

먼저, 도 2a에 도시한 바와같이 모스 트랜지스터(MT10,MT20)가 형성된 반도체기판(10) 상부에 절연막으로 쓰이는 일반적인 산화막에 비해 100배이상 빠른 식각속도를 가지는 hydrogen silsesquioxane를 이용한 제 1절연막(20)을 증착하여 희생층을 형성한다.First, as shown in FIG. 2A, the first insulating layer 20 using hydrogen silsesquioxane has an etching rate that is 100 times faster than a general oxide layer used as an insulating layer on the semiconductor substrate 10 on which the MOS transistors MT10 and MT20 are formed. Deposited to form a sacrificial layer.

그 다음, 도 2b에 도시한 바와같이 상기 제 1절연막(20) 상부에 음성감광막(PR10)을 도포하고 종래 컨택홀 형성 시 사용하던 감광막 마스크를 이용하여 노광 및 현상하여 상기 모스 트랜지스터(MT10,MT20)의 공통 소스/드레인영역(S/D10)을 중심으로 하여 모스 트랜지스터(MT10,MT20)의 게이트의 일부를 포함하는 위치에만 감광막(PR10)을 남기고, 이를 마스크로 제 1절연막(20)을 건식식각하여 제거함으로써 컨택홀이 형성될 부분을 설정할 수 있다.Next, as illustrated in FIG. 2B, a negative photoresist film PR10 is coated on the first insulating layer 20, and exposed and developed using a photoresist mask used in forming a conventional contact hole, thereby forming the MOS transistors MT10 and MT20. The photoresist film PR10 is left only at a position including a part of the gates of the MOS transistors MT10 and MT20 around the common source / drain region S / D10 of FIG. 8), and the first insulating film 20 is dried using the mask. By etching and removing, the portion where the contact hole is to be formed can be set.

그 다음, 도 2c에 도시한 바와같이 상기 감광막(PR10)을 제거하고, 상기 형성한 구조물 상부전면에 식각이 느린 제 2절연막(30)을 증착하고 상기 제 1절연막(20)이 드러나도록 화학기계적연마 등의 방법으로 평탄화하여 절연막을 다시 형성한다.Next, as shown in FIG. 2C, the photoresist film PR10 is removed, and a second etch slow film 30 is deposited on the upper surface of the structure, and the chemical mechanical process is performed so that the first insulation film 20 is exposed. The insulating film is formed again by flattening by polishing or the like.

그 다음, 도 2d에 도시한 바와같이 상기 제 1절연막(20)을 상기 형성한 제 2절연막(30)과 식각비가 차이가 많은 식각물(etchant)을 이용하여 소스/드레인영역 (S/D10)이 드러나도록 식각하여 컨택홀을 형성하는데, 상기 공정에서 제 1절연막(20)은 제 2절연막(30)에 비해 100배이상 식각이 빠르므로 제 1절연막(20)이 식각되어도 형성되는 컨택홀 주변의 소자는 손상을 입지 않는다.Next, as shown in FIG. 2D, the source / drain region S / D10 is formed by using an etchant having a large etch ratio different from that of the second insulating layer 30 on which the first insulating layer 20 is formed. The contact hole is formed by etching so that the first insulating layer 20 is 100 times faster than the second insulating layer 30 in this process, so that the contact hole is formed even when the first insulating layer 20 is etched. The device is not damaged.

그 다음, 도 2e에 도시한 바와같이 상기 형성한 구조물의 상부전면에 폴리실리콘(40)을 증착하고, 상기 제 2절연막(30)이 드러나도록 에치백하여 평탄화한다.Next, as illustrated in FIG. 2E, polysilicon 40 is deposited on the upper surface of the formed structure, and etched back to planarize the second insulating layer 30 to be exposed.

상기한 바와같은 본 발명에 의한 반도체소자의 컨택 형성방법은 식각이 빠른 희생층으로 컨택이 형성될 부분을 설정하고 그 이외의 부분은 식각이 느린 절연막이 형성되도록한 후 상기 희생층을 제거하는 방법을 통해 컨택홀이 형성되는 과정에서 보이드가 발생하지 않으므로 컨택간 단락을 방지할 뿐만 아니라 컨택홀 주변소자에 손상을 주지 않으므로 워드라인과 컨택간을 절연하는 캡질화막의 두께를 줄일 수 있 는 효과가 있다.In the method of forming a contact of a semiconductor device according to the present invention as described above, a portion in which a contact is to be formed is formed as a fast-etching sacrificial layer, and the other part is a method of removing the sacrificial layer after forming an insulating film having a slow etching. Since voids do not occur in the process of forming contact holes, it prevents short-circuits between the contacts and damages the peripheral elements of the contact holes, thereby reducing the thickness of the cap nitride layer insulating the word lines and the contacts. have.

Claims (4)

모스 트랜지스터가 형성된 반도체기판 상부에 일반 산화막에 비해 100배 이상의 빠른 식각 속도를 갖는 제 1절연막을 증착하는 희생층 형성공정과;A sacrificial layer forming step of depositing a first insulating film having an etch rate of 100 times faster than a general oxide film on a semiconductor substrate on which a MOS transistor is formed; 상기 제 1절연막 상부에 감광막을 도포하고 상기 모스 트랜지스터의 공통 소스/드레인영역을 포함한 소정의 위치에만 감광막이 남도록 패터닝 한 후 이를 마스크로 제 1절연막을 건식식각하여 제거하는 컨택설정공정과;A contact setting step of applying a photoresist film over the first insulation film, patterning the photoresist film to remain only at a predetermined position including a common source / drain region of the MOS transistor, and then dry etching and removing the first insulation film with a mask; 상기 감광막을 제거하고, 상기 형성한 구조물 상부전면에 식각이 느린 제 2절연막을 증착하고 상기 제 1절연막이 드러나도록 평탄화하는 절연막 형성공정과; An insulating film forming step of removing the photoresist film, depositing a second etch film having a slow etching on the upper surface of the formed structure, and planarizing the first insulating film to be exposed; 상기 제 1절연막을 소스/드레인영역이 드러나도록 식각하는 컨택홀 형성공정과; Forming a contact hole to etch the first insulating layer to expose a source / drain region; 상기 형성한 구조물의 상부전면에 폴리실리콘을 증착하고, 상기 제 2절연막이 드러나도록 에치백하여 평탄화하는 컨택 형성공정으로 이루어지는 것을 특징으로하는 반도체소자의 컨택 형성방법.And depositing polysilicon on the upper surface of the formed structure, and etching back to planarize and expose the second insulating layer to expose the second insulating layer. 제 1항에 있어서, 상기 컨택설정공정에서 감광막 패턴은 컨택홀 형성시 사용하는 마스크를 음성감광막에 적용하여 형성하는 것을 특징으로하는 반도체소자의 컨택 형성방법. The method of claim 1, wherein the photoresist pattern is formed by applying a mask used to form a contact hole to the voice photoresist in the contact setting process. 삭제delete 제 1항에 있어서, 상기 제 1절연막은 hydrogen silsesquioxane인 것을 특징으로하는 반도체소자의 컨택 형성방법.The method of claim 1, wherein the first insulating layer is hydrogen silsesquioxane.
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JPS63129632A (en) * 1986-11-20 1988-06-02 Sumitomo Electric Ind Ltd Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation
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JPS63129632A (en) * 1986-11-20 1988-06-02 Sumitomo Electric Ind Ltd Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation
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KR0135690B1 (en) * 1994-07-20 1998-04-24 김주용 Fabrication method of contact in semiconductor device
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