GB2144302A

GB2144302A - Signal processing circuit

Info

Publication number: GB2144302A
Application number: GB08419101A
Authority: GB
Inventors: Eric Paul Batterman
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1983-07-27
Filing date: 1984-07-26
Publication date: 1985-02-27
Also published as: HK22793A; CS269961B2; JPH0693780B2; AU573236B2; FR2557410B1; JPS6052186A; AU3119684A; FI842926A; FI76901B; KR920005219B1; DE3427669A1; KR850000864A; IT8422043A0; GB2144302B; DE3427669C2; AT404200B; ATA245184A; CA1219338A; IT1176474B; PT78978A

Abstract

A signal processing circuit is provided which comprises: a plurality of cascaded delaying means 10, 12, 14, 16, 18 successively delaying input signals; a means 100 for detecting magnitude changes of the input signals; and selective coupling means 20, 22 responsive to the detecting means, for selectively coupling the inputs of certain of the delaying means to the inputs of selected others of the delaying means to enhance the transition times of input signals, thereby providing sharper edges at colour boundaries in a video signal. <IMAGE>

Description

SPECIFICATION Signal Processing Circuit The present invention relates to signal processing circuitry and, in particular, to circuitry for enhancing the rise and fall times of signal transitions.

When signals are processed through systems having limited bandwidth or slew rate, the rise and fall times of transitions between signal levels is correspondingly limited. I.e., lower bandwidth produces more gradual transitions. In a television (TV) system, for example, the bandwidth of the chrominance signals is limited by the transmission system standard. In the NTSC system, the I chrominance component signal has 1.5 Megahertz (MHz) bandwidth and the Q chrominance component signal has 0.5 MHz bandwidth. Not infrequently, TV receiver circuitry processes both I and 0 chrominance component signals with 0.5 MHz bandwidth.

For most picture conditions, the chrominance signal processing described above is satisfactory, even though it is desirable that the rise and fall times be improved. However, limited chrominance signal rise and fall times tend to make the edges of objects less well defined and to suffer from poor color fidelity. These undesirable picture effects are particularly evident when the object has a well defined edge which the high bandwidth (4.2 MHz) luminance signal can reproduce but which the lower bandwidth chrominance signals cannot, and further when the color of the object is substantially different from that of the background.

Thus, there is a need for circuitry which will enhance (e.g., decrease) signal rise and fall times when certain transitions occur and for detectors of such transitions. It is noted that conventional peaking circuits which emphasize the higher frequency components of a signal relative to the lower frequency components thereof are of limited effect where the higher frequency components have been severely attenuated due to restricted signal bandwidth.

Accordingly, the signal processing circuit of the present invention comprises: a plurality of cascaded delaying means successively delaying input signals; means for detecting magnitude transitions of the input signals; and selective coupling means between inputs of ones of the delaying means responsive to the detecting means.

In the drawings: Figure 1 is a schematic diagram in block diagram form of apparatus including an embodiment of the present invention; Figures 2a and 2b are diagrams illustrating signals in the apparatus of Figure 1; and Figures 3-7 are schematic diagrams of modifications to, and alternate embodiments of, portions of the apparatus of Figure 1.

Although the signals in the following description are referred to as digital signals, it is understood that the present invention is satisfactorily practiced with many different types of signals, for example, sampled data signals of both analog and digital types, and analog signals. In the drawing, broad arrows illustrate signal paths for multi-bit, parallel digital signals whereas line arrows illustrate signal paths for single-bit or serial digital signals, or for analog signals.

Figure 1 illustrates a signal transition enhancement circuit including a transition detector. The circuit is adapted for processing digital chrominance signals in a television receiver having digital signal processing circuitry. The receiver produces digital chrominance signals CS which are further processed by apparatus employing the present invention to produce enhanced digital chrominance signals CS'.

In the following description, the operation of delay stages 10, 12, 14, 1 6 and 1 8 and of MUX's 20 and 22 to effect enhancement of rise and fall time is described first. The operation of transition detector 100 is described thereafter.

Assuming initially that multiplexers (MUX) 20 and 22 couple signals at locations D and C to their respective outputs, input signals CS are successively delayed by cascade-coupled delay stages 10, 12, 14, 6 and 1 8 so that output signals CS' are simply input signals CS delayed in time. Each of delay stages 10, 12, 14, 1 6 and 1 8 is, for example, an eight-bit parallel latch responsive to a clocking signal fsc Clocking signal fsc has a repetition rate related to the color subcarrier frequency, i.e., about 3.58 MHz in the NTSC TV system.Thus, CS' is delayed in time from CS by five cycles of clocking signal fsc When transistions of signals CS occur which satisfy certain predetermined criteria of magnitude and rise or fall time, transition detector 100 develops and applies control signal MC to MUXs 20 and 22 so that MUXs 20 and 22 selectively couple inputs of ones of the delay stages to inputs of others of the delay stages. Specifically, MUX 20 couples the input of delay stage 12 to the input of delay stage 14 and uncouples the output of delay stage 12 therefrom. Similarly MUX 22 couples the input of delay stage 18 to the input of delay stage 1 6 and uncouples the output of delay stage 14 therefrom.

Consider, for example, the time sequence of samples A, B, C, D, E, F of signal CS shown in Figure 2a as forming a transition from a lower magnitude to a higher magnitude (positive-going transition).

(Note that, in the case of sampled data systems, either analog or digital, the signal maintains the value it has for the entire period. The straight line drawn between samples is for illustrative purposes only in this type of system). The time interval represented by Figure 2a is that in which the time sequence of samples of CS have been clocked through delay stages 10, 12, 14, 16 and 1 8. Thus, the samples designated by the sample-designating letters in Figure 2a correspond to the values of the samples at the signal paths at corresponding signal-path-designating letters in Figure 1. That is, signal CS is at this time at the magnitude indicated by sample F and was at the magnitude indicated by sample A five cycles of clocking signal fsc previously.Solid line 50 connects the samples A-F so as to illustrate the rise time of the transition represented by the samples A-F.

Consider further that at this time this sequence of samples have magnitudes such that detector 100 develops control signal MC activating MUXs 20 and 22 as described above. Then, MUX 20 substitutes the value of sample E for sample D at the input to delay stage 14 and MUX 22 substitutes the value of sample B for the value of sample C at the input to delay stage 1 6. These substitutions are respectively indicated by arrows 54 and 52 and the substituted sample values from samples E and B are respectively designated as D' and C' in Figure 2a. At the next occurring cycle of clocking signal fisc.

the samples B, C', D', E, F are respectively latched in delays 18, 16, 14, 12 and 1 0, and detector 100 removes control signal MC because the transition detection criteria are no longer satisfied. In response to further cycles of fisc, signal CS' will include the modified sequence of samples A, B, C', D', E, F (i.e.

the magnitudes A, B, B, E, E, F in sequence) which has a transition having enhanced (decreased) rise time. Phantom line 56 connects the samples in the modified sequence so as to illustrate the enhanced rise time of the transition represented thereby.

By way of further example, consider the sequence of samples of signal CS shown in Figure 2b as forming a transition from a higher magnitude to a lower magnitude (negative-going transition), illustrated by line 60. In accordance with the operation described above in relation to Figure 2a, substitutions 62 and 64 are made by MUXs 20 and 22, respectively, in response to control signal MC so that the modified sequence A, B, B, E, E, F of signal CS' representing an enhanced fall time, illustrated by phantom line 66, is produced.

Transition detector 100, and the predetermined criteria by which occurrence of a transition is detected, will now be described. A transition of a waveform is a change of instantaneous amplitude from one amplitude level to another amplitude level, and can be described in terms of the difference between the levels and the time required for the change of level. For sampled data, of which digital signals are an example, a transition can be described in terms of the magnitudes of samples or groups of samples, and the number of samples over which a magnitude change occurs.

Detector 100 detects a transition when the sampled data signal magnitudes are relatively close in magnitude for each of two groups of consecutive successive samples, and when the difference in magnitudes as between non-consecutive samples is substantial. Specifically, in a sequence of six cons'ecutive successive samples, a transition is detected when 1) the first and second samples (first group of consecutive samples) are relatively close in magnitude to each other, 2) the fifth and sixth samples (second group of consecutive samples) are relatively close in magnitude to each other, and 3) when the magnitudes of the second and fifth samples (two non-consecutive samples) substantially differ from each other.These criteria establish that the first, second, fifth and sixth samples are not part of a transition, and that a substantial transition occurs between the two groups of samples, such as is illustrated by Figures 2a and 2b.

Transition detector 100 of Figure 1 includes subtractor 30 which develops the absolute value of the difference between the magnitudes of consecutive samples E and F which is applied to comparator 32. Comparator 32 produces an output to apply an enabling level to one input of AND gate 46 when the absolute value of the difference lE-FI is less than the relatively small value REF-1. Similarly, subtractor 34 develops the absolute value of the difference between consecutive samples A and B and comparator 36 applies an enabling level to a second input of AND gate 46 when the difference IA--BI is less than the relatively small value REF-2.In addition, subtractor 40 develops from non-consecutive samples B and E the absolute value of the difference IB-E which, if it is greater than a substantial minimum value MIN, causes comparator 42 to apply an enabling level to a third input of AND gate 46.

Assuming that enabling signal EN is present, coincidence at the inputs of AND gate 46 produces control signal MC to cause MUXs 20 and 22 to respectively apply the value of sample E to the input of delay stage 14 and the value of sample B to the input of delay stage 1 6 as described above. These criteria for detection of a transition are summarized in Table I.

TABLE I Test criteria at No. Elements AND gate 46 1. 30,32 iE-FJ < REF-1 2. 34, 36 /A--BI < REF-2 3. 40,42 IB-EI > MlN 4. 48 EN= 1 Control device 48 develops enabling signal EN which enables and disables detector 1 00. Control device 48 is, for example, a transition detector developing enabling signal EN in response to transitions in luminance signals YS. Signals CS and YS are related in time because they are component signals representing the same picture. Control device 48 can be omitted.

Element 47 is a pulse generator or digital one-shot responsive to AND gate 46, and clock signal fsc to generate a pulse MC (e.g. one sample period wide) and cannot output a subsequent pulse for e.g.

two sample periods. One-shot 47 precludes continuous recirculation of samples around the loop including multiplexer 22 and delay stage 16 which may occur with the transition detection merged into the transition enhancement circuit. Alternatively, if the transition detector and enhancement circuit use separate but parallel delay stages, one-shot 47 is not required.

Transition detector 200 shown in Figure 3 is a modification of detector 100 in which additional detection criteria must be satisfied to produce control signal MC. The additional detection criteria ensure that the transition will only be enhanced if it is a relatively smooth and monotonic transition, thereby avoiding the loss of valid, relatively higher frequency sample information.

This is achieved by additional detection criteria requiring that the transition magnitude difference between the second and fifth samples not exceed a maximum value, and that the magnitudes of the third and fourth samples are intermediate the average of the magnitudes of the second and fifth samples and the magnitudes of the second and fifth samples, respectively.

Detector 200 includes subtractors 30, 34 and 40, and comparators 32, 36 and 42 which correspond to like numbered elements of detector 100 described above. Referring to both Figure 2 and Figure 3, comparator 44 applies an enabling level to an input of AND gate 46' when the absolute value of the difference B-El developed by subtractor 40 is less than a maximum value MAX, which is itself greater than the minimum value MIN. Subtractor 40 also develops a sign bit SB which indicates whether the transition is positive- or negative-going and which is employed to simplify the comparator structure for testing the additional detection criteria.

Criteria indicating smoothness and monotonicity of a transition are tested by comparators 70, 74, 84 and 88 as follows. Comparator 70 compares samples B and C, the result of which comparison is selectively inverted by controllable inverter block 72 in response to sign bit SB. Thus, one input of AND gate 46' is enabled when the criterion B < C is satisfied for positive-going transitions and when the criterion B > C is satisfied for negative-going transitions. Similarly, comparator 74 and controllable inverter block 76 enable one input of AND gate 46' when the criterion D < E is satisfied for positivegoing transitions and when the criterion D > E is satisfied for negative-going transitions. This ensures that the magnitudes of samples C and D are intermediate those of samples B and E providing a first indication of monotonicity.

Adder circuit 80 and divide-by-two circuit 82 develop the average of the magnitudes of samples B and E, which average is indicated by the phantom lines at level 2(B+E) in Figures 2a and 2b. For sampled analog signals, circuits 80 and 82 are a resistive network; for digital signals, circuit 80 is an adder and circuit 82 is a bit shifter implemented by wired connections. Comparator 84 and controllable inverter block 86 enable an input of AND gate 46' when the criterion C < 2 (B+E) is satisfied for positive-going transitions and when C > 2(B+E) is satisfied for negative-going transitions.Similarly, comparator 88 and controllable inverter block 90 enable an input of AND gate 46' when the criterion D > 2 (B+E) is satisfied for positive-going transitions and when D < 3(B+E) is satisfied for negative-going transitions. This ensures that the magnitude of sample C is intermediate the average level of B and E and the magnitude of sample B, and that the magnitude of sample D is intermediate the average level and the magnitude of sample E, thereby providing a further indication of monotonicity.

AND gate 46' develops control signal MC in response to coincidence of signals at all of its inputs.

These criteria for detection are summarized in Table II.

TABLE II Test criteria at AND gate 46' Positive-going Negative-going No. Elements transition transition 1. 30,32 IE-Fl < REF-1 E--F| < REF-1 2. 34, 36 A-Bi < REF-2 iAB| < REF-2 3. 40,42 iB-EI > MIN lB-El > MIN 4. 40,44 IB--EI < MPX /B--E/ < MAX 5. 70,72 B < C B > C 6. 74,76 D < E D > E 7. 80,82,84,86 C < T(E+B) C > 2(B+E) 8. 80, 82, 88, 90 D > -21(E+B) D < -21(B+E) 9. 48 EN=1 EN=1 For an eight-bit digital chrominance signal having values corresponding to the decimal values zerot through 255, the following nominal comparison levels are satisfactory:: REF-1 =8, REF-2=8, MIN=48, MAX=255.

The remaining portion of Figure 3 shows control circuit 48 comprising a luminance signal transition detection system. Luminance signal YS are successively delayed by delaying stages 310, 312, 314, 31 6 and 318 and are applied to transition detector 300. Detector 300 is, for example, of like structure to that of either detector 100 or 200 as described above except that the control signal therefrom is applied to AND gate 46' as enabling signal EN. Delaying stages 310--318 may be a delay line existing as part of an FIR or comb filter within the luminance processing circuitry.

Figures 4 and 5 show embodiments useful, for example, as a substitute for comparators 32, 36, or 44 of Figures 1 and 2. These embodiments may be used where the digital samples are represented in sign-magnitude form. Inverted input AND gate 32' of Figure 4 responds to a selected number of the more significant bits (MSB) (but not the sign bit) of the difference produced by subtractor 30 all being 'O' to apply an enabling level to AND gate 46 or 46'. NOR gate 32" of Figure 4 responds to a selected number of the MSBs of the absolute value of the difference produced by subtractor 30 being all 'O' to apply an enabling level to AND gate 46 or 46'.

The level of reference level REF-1 provided by gate 32' or 32" is given by [2N-1] where N is the number of lesser significant bits (LSB) not connected thereto and is listed in Table lli.

TABLE Ill AND gate 32' and NOR gate 32": MSBs applied LSBs not applied Value of REF-1 8 0 0 7 1 1 6 2 3 5 3 7 4 4 15 3 5 31 2 6 63 1 7 127 Figure 6 shows an embodiment useful, for example, as a substitute for comparator 42 of Figure 2 when the digital samples are represented in sign-magnitude form. OR gate 42' responds to any one of the MSBs of the absolute value of the difference produced by subtractor 40 being a '1' to apply an enabling level to AND gate 46 or 46'. The level of reference MIN is given by 12N 11 where N is the number of LSBs not connected to OR gate 42'.

Modifications are contemplated within the scope of the present inventior set forth in the claims following. For example, subtractor 80, divide circuit 82, comparator 88 and inverter block 90 of Figure 2 can be eliminated and samples C and D applied directly to comparator 84. This provides a monotonicity indication where the criterion C < D is satisfied for positive-going transitions and when C > D is satisfied for negative-going transitions. Further, the comparator arrangements of Figures 4, 5 and 6 illustrate that the absolute value of the difference magnitude is obtained for digital numbers in sign-magnitude form by excluding the sign bit SB from the comparison.

The number of delaying stages 10, 12, 14... employed, the repetition rate of clocking signal fsc, the ones of the successively delayed samples of signals CS applied to detectors 100 and 200, and the location of MUXs 20 and 22 in the cascade of delaying stages all influence the rise and fall time detection limits and the degree to which the rise and fall times are enhanced. For example, to enhance the transitions of luminance signal samples produced at four times the color subcarrier frequency (i.e.

45C~14.32 MHz for the NTSC system), a greater number of delaying stages are required. Moreover, the numbers of samples in the groups thereof can be greater or lesser than the two samples (A, B and E, F) described herein, and the number of samples between those groups can be greater or lesser than the two samples (C, D) described herein.

Transitions faster than those illustrated in Figures 2a and 2b can be enhanced so long as there is at least one signal sample within the transition. l.e., so long as the two samples compared to detect a transition are non-consecutive. For example, the circuit of Figure 1 can be modified so that signal samples E and C of Figure 2 are compared by subtractor 40 and comparator 42 to detect a transition in which case delay stages 12 and 14 and multiplexer 20 are the principal elements and only the substitutions 54 and 64 of Figures 2a and 2b are effected. Thus, MUX 22 can be eliminated and delay stage 14 coupled directly to delay stage 1 6.

While the transition enhancement described herein has referred to decreasing the rise and fall times of transitions, the present invention is also useful to increase rise and fall times. In this modification, MUX 20 is interposed before delay stage 12 and receives signal samples E and D at its inputs, MUX 22 is interposed before delay stage 18 and receives signal samples C and B at its inputs, delay stage 12 is coupled to delay stage 14, and delay stage 14 is coupled to delay stage 1 6. Thus, detector 100 produces control signal MC to cause sample C to be substituted for sample B and sample D to be substituted for sample E.

By way of further example, controllable inverter blocks 72, 76, 86 and 90 can be eliminated and multiplexers can be added to reverse the inputs to each of comparators 70, 74, 84 and 88. Still further, other digital number systems can be processed by the circuitry of the present invention by insertion of converters, such as the twos-complement-to-binary converter of Figure 7, at appropriate locations within transition detectors 100 and 200.

Claims

1. A signal processing circuit comprising: an input for receiving input signals and an output at which output signals responsive to said input signals are produced; a plurality of delaying means coupled in cascade between said input and said output for successively delaying said input signals; detecting means, coupled to said plurality of delaying means and responsive to ones of said successively delayed input signals, for detecting a magnitude transition of said input signals; and means, coupled to said plurality of delaying means and to said detecting means, for selectively coupling an input of one of said delaying means to an input of another one of said delaying means in response to said detecting of said magnitude transition.

2. The circuit of Claim 1 wherein said one of said delaying means is more proximate said input than is said other one of said delaying means.

3. The circuit of Claim 1 wherein said one of said delaying means is more proximate said output than is said other one of said delaying means.

4. The circuit of Claim 1 further comprising second means, coupled to said delaying means and to said detecting means, for selectively coupling an input of a second one of said delaying means to an input of a second other one of said delaying means in response to said detecting of said magnitude transition.

5. The circuit of Claim 4 wherein said one of said delaying means is more proximate said input than is said other one of said delaying means, and said second one of said delaying means is more proximate said output than is said second other one of said delaying means.

fi The circuit of Claim 1 wherein said detecting means includes comparison means for detecting a magnitude difference between non-consecutive ones of said successively delayed input signals which exceeds a predetermined value.

7. The circuit of Claim 6 wherein said detecting means further includes second comparison means for detecting a magnitude difference between further ones of said successively delayed input signals which is less than a second predetermined value.

8. The circuit of Claim 1 further comprising control means for developing an enabling signal, and means for applying said enabling signal to said detecting means to enable said detecting of a magnitude transition.

9. The circuit of Claim 8 wherein said control means develops said enabling signal in response to a transition of a second input signal which is related in time to said input signals received at said input.

10. The circuit of Claim 9 wherein said input signals are representative of chrominance components of television signals and wherein said second input signals are representative of luminance components thereof.

11. A signal processing circuit comprising: first and second delaying means, having respective inputs and outputs, for respectively delaying signals applied to said inputs; multiplexing means having a first input to which the output of said first delaying means is coupled, having a second input and having an output coupled to the input of said second delaying means, said multiplexing means for selectively coupling its first and second inputs to its output in response to a control signal; means for applying input signals to the input of said first delaying means and to the second input of said multiplexing means; detecting means for developing said control signal in response to a predetermined magnitude condition of said input signals and for applying said control signal to said multiplexing means.

12. The circuit of Claim 11 wherein said detecting means comprises a comparing means for developing said control signal in response to the magnitude of said input signals changing in excess of a predetermined amount.

1 3. The circuit of Claim 11 further comprising: third delaying means, having an input and an output, for delaying signals applied to its input; second multiplexing means, having a first input to which the output of said second delaying means is coupled, having a second input to which the output of said third delaying means is coupled, and having an output coupled to the input of said third delaying means, said multiplexing means for selectively coupling its first and second inputs to its output in response to said control signal.

1 4. The circuit of Claim 13 wherein said detecting means comprises comparing means having a first input to which the input of one of said first, second and third delaying means is coupled, having a second input to which the output of one of said first, second and third delaying means is coupled, and having an output, for developing said control signal at its output in response to the magnitudes of signals at its first and second inputs differing by said predetermined amount.

1 5. The circuit of Claim 11 further comprising: control means for developing an enabling signal, and means for applying said enabling signal to said detecting means to enable said detecting of a magnitude transition, wherein said control means develops said enabling signal in response to a transition of a second input signal which is related in time to said input signals received at said input.

1 6. The circuit of Claim 1 , wherein: said plurality of delaying means provides a plurality of signal samples successively delayed in time; and said detecting means comprises first detecting means responsive to a first group of said signal samples for developing a first indication when the magnitude of the samples in said first group differ by less than a first predetermined value, second detecting means responsive to two of said signal samples for developing a second indication when the magnitudes of said two signal samples differ by more than a second predetermined value, and indication developing means for developing a detection indication in response to said first and second indications.

17. The circuit of Claim 1, wherein: said plurality of delaying means provides a plurality of signal samples successively delayed in time; and said detecting means comprises first detecting means responsive to a first group of said signal samples for developing a first indication when the magnitude of the samples in said first group differ by less than a first predetermined value, second detecting means responsive to a second group of said signal samples for developing a second indication when the magnitude of the samples in said second group differ by less than a second predetermined value, third detecting means responsive to two of said signal samples for developing a third indication when the magnitudes of said two signal samples differ by more than a third predetermined value, and indication providing means for developing a detection indication in response to said first, second and third indications.

1 8. The circuit of Claim 1 7 wherein at least one of said first and second detecting means comprises: combining means for developing an indication of the difference between the magnitudes of two signal samples of said first group; and comparing means for developing said first indication when the magnitude of said difference indication is less than said first predetermined value.

1 9. The circuit of Claim 1 8 wherein said signal samples are digital signals and wherein said combining means is a digital subtractor.

20. The circuit of Claim 1 9 wherein said comparing means includes an AND gate for detecting coincidence of inverses of a predetermined number of the more significant bits of said difference indication developed by said digital subtractor.

21. The circuit of Claim 19 wherein said comparing means includes a NOR gate responsive to a predetermined number of the more significant bits of said difference indication developed by said digital subtractor.

22. The circuit of Claim 1 7 wherein said third detecting means comprises: combining means for developing an indication of the difference between the magnitudes of said two signal samples; and comparing means for developing said third indication when the magnitude of said difference indication exceeds said third predetermined value.

23. The circuit of Claim 22 wherein said signal samples are digital signals and wherein said combining means is a digital subtractor.

24. The circuit of Claim 23 wherein said comparing means includes an OR gate responsive to a predetermined number of the more significant bits of said difference indication developed by said digital subtractor.

25. The circuit of Claim 17 wherein said indication providing means includes an AND gate responsive to coincidence of said first, second and third indications for developing said detection indication.

26. The circuit of Claim 1 7 wherein said first group includes at least two consecutive signal samples and said second group includes at least two consecutive signal samples other than those included in said first group.

27. The circuit of Claim 17 wherein said two signal samples include first and second nonconsecutive signal samples.

28. The circuit of Claim 27 further comprising fifth detecting means for developing a fifth indication when the magnitudes of signal samples intermediate said first and second non-consecutive signal samples are intermediate the magnitudes of said first and second non-consecutive signal samples, and wherein said indication providing means is further responsive to said fifth indication for developing said detection indication.

29. The circuit of Claim 27 wherein at least two signal samples intervene between said first and second non-consecutive signal samples, further comprising fifth detecting means for developing a fifth indication that the sequence of magnitudes of said first, intervening and second signal samples is monotonic.

30. The circuit of Claim 29 wherein said fifth detection means comprises: means for developing a magnitude value intermediate that of said first and second nonconsecutive signal samples; first means for comparing the magnitude of one of said intervening signal samples to said intermediate magnitude value; second means for comparing the magnitude of another one of said intervening signal samples to said intermediate magnitude value; wherein said fifth indication includes indications developed by said first means and said second means.

31. The circuit of Claim 1, wherein: said plurality of delaying means provides a plurality of signal samples successively delayed in time; and said detecting means comprises first detecting means responsive to a first group including at least two consecutive ones of said signal samples for developing a first indication when the magnitude of the samples in said first group differ by less than a first predetermined value, second detecting means responsive to a second group of said signal samples for developing a second indication when the magnitude of the samples in said second group differ by less than a second predetermined value, said second group including at least two consecutive ones of said signal samples other than those included in said first group, third detecting means responsive to first and second non-consecutive ones of said signal samples for developing a third indication when the magnitudes of said first and second signal samples differ by more than a third predetermined value, wherein at least one signal sample intervenes between said first and second signal samples, fourth detecting means for developing a fourth indication that the sequence of magnitudes of said first intervening and second signal samples is monotonic, and indication indicating means for developing said detection indication in response to said first, second, third and fourth indications.

32. The circuit of Claim 31 wherein said fourth detecting means develops said fourth indication when the magnitudes of said signal samples intervening between said first and second non consecutive signal samples are intermediate the magnitudes of said first and second non-consecutive signal samples.

33. The circuit of Claim 31 wherein at least two signal samples intervene between said first and second non-consecutive signal samples, and wherein said fourth detection means comprises: means for developing a magnitude value intermediate that of said first and second nonconsecutive signal samples; first means for comparing the magnitude of one of said intervening signal samples to said intermediate magnitude value; second means for comparing the magnitude of another one of said intervening signal samples to said intermediate magnitude value; wherein said fourth indication includes indications developed by said first means and said second means.

34. The circuit of Claim 33 wherein said fourth detecting means develops said fourth indication when the magnitudes of said signal samples intervening between said first and second nonconsecutive signal samples are intermediate the magnitudes of said first and second non-consecutive signal samples.

35. The circuit of Claim 1, wherein: said plurality of delaying means provides respective pluralities of samples of first and second signals, each successively delayed in time; and said detecting means comprises first detecting means responsive to a first group of said first signal samples for developing a first indication when the magnitude of the samples in said first group differ by less than a first predetermined value, second detecting means responsive to a second group of said first signal samples for developing a second indication when the magnitude of the samples in said second group differ by less than a second predetermined value, third detecting means responsive to two of said first signal samples for developing a third indication when the magnitudes of said two signal samples differ by more than a third predetermined value, fourth detecting means responsive to a first group of said second signal samples for developing a fourth indication when the magnitude of the samples in said first group differ by less than a fourth predetermined value, fifth detecting means responsive to a second group of said second signal samples for developing a fifth indication when the magnitude of the samples in said second group differ by less than a fifth predetermined value, sixth detecting means responsive to two of said second signal samples for developing a sixth indication when the magnitudes of said two signal samples differ by more than a sixth predetermined value, and indication developing means for developing said detection indication in response to said first, second, third, fourth, fifth and sixth indications.

36. A signal processing circuit comprising: an input for receiving input signals, and an output at which output signals responsive to said input signals are produced; a plurality N of delaying means coupled in cascade between said input and said output for successively delaying samples of said input signals, wherein N is an integer; first multiplexing means, interposed in said cascade coupling of said delaying means, having an output coupled to an input of a Jth one of said delaying means, and having first and second inputs respectively coupled to the outputs of a (J-1 )th and a (J-2)th ones of said delaying means, where J is an integer no greater than N, said first multiplexing means for selectively coupling its first and second inputs to its output in response to a control signal;; second multiplexing means, interposed in said cascade coupling of said delaying means, having an output coupled to the input of a (K-l)th one of said delaying means, and having first and second inputs respectively coupled to the outputs of a Kth and a (K-1 )th ones of said delaying means, where K is an integer no greater than N, said second multiplexing means for selectively coupling its first and second inputs to its output in response to said control signal; first detecting means, coupled to said delaying means and responsive to a first group of at least two consecutive input signal samples, for detecting that the magnitudes of said first group of consecutive input signal samples are within a predetermined range of relative magnitudes:: second detecting means, coupled to said delaying means and responsive to a second group of at least two other consecutive input signal samples, for detecting that the magnitudes of said second group of consecutive input samples are within a predetermined range of relative magnitudes; third detecting means, coupled to said delaying means and responsive to two non-consecutive input signal samples, for detecting that the magnitudes of said two non-consecutive input signal samples differ by at least a predetermined amount; and means for developing said control signal in response to said detecting by said first, second and third detecting means and for applying said control signal to said first and second multiplexing means.

37. The circuit of Claim 36 wherein said two non-consecutive samples include one sample from each of said first and second groups of consecutive samples.

38. The circuit of Claim 36 further comprising control means for developing an enabling signal and means for applying said enabling signal to said means for developing to enable said developing of said control signal.

39. The circuit of Claim 38 wherein said control means develops said enabling signal in response to a transition of a second input signal which is related in time to said input signals received at said input.

40. The circuit of Claim 39 wherein said input signals are representative of chrominance components of television signals and wherein said second input signals are representative of luminance components thereof.

41. A signal processing circuit substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings or any of the modifications thereof described with reference to Figures 3 to 7.