JPH0396176A - Video noise reduction device - Google Patents

Abstract

PURPOSE:To reduce video noise by setting a condition equivalent to video noise and replacing the video noise with a video signal of one preceding or over of scanning line when the video noise takes place. CONSTITUTION:When a difference between video signals between scanning lines is larger as d2 or over and a level change during a prescribed period in a scanning line is small as d1 or below, it is highly possible that a signal after a video signal Sa is video noise. Since an output of an AND circuit 9 is logical 1 in this case, a video changeover device 3 is switched and a content of a 1H memory, that is, a video signal of one preceding or over of scanning line is outputted. That is, since video signals of adjacent scanning lines have a relation, the effect is less even with replacement. Thus, the video noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a satellite broadcast receiving device, and more particularly to a video noise reduction device for digital satellite broadcasting.

[Prior Art] Conventional satellite broadcast receiving devices do not particularly reduce video noise.

[Problem to be solved by the invention J As mentioned above, conventional satellite broadcasting receivers do not particularly reduce video noise, so when the electric field strength weakens due to rain or snow, the receiver's cathode ray tube This has the disadvantage that horizontal white or black image noise is generated on the display screen, making the image difficult to see.

[Means for Solving the Problems 1] Therefore, an object of the present invention is to provide a novel video noise reduction device that solves the above-mentioned problems. A memory that can record, a shift register that delays the video signal, a window combiner that compares the video signal delayed by the memory and shift register with the current video signal, and two systems of video, the current one and the one delayed by one scanning line. A circuit device configured with a video switcher that switches signals enables effective reduction of video noise.

[Example] Next, details of the specific structure and effects of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which a four-clock shift register 1, an IH memory 2 that records one scanning line of a video signal, and a video signal of the shift register 1 and a video signal of the IH memory 2. Video switcher to switch 3. , video signal of shift register 1 and 1H
Window comparator 4 for comparing video signals in memory;
A window comparator 5 that compares the input video signal with the video signal of the shift register 1 delayed by one clock, a window comparator 6 that compares the input video signal with the video signal of the shift register 1 delayed by two clocks, and the input video signal. a window comparator 7 that compares the video signal of the shift register 1 delayed by 3 clocks with the video signal of the shift register 1 delayed by 4 clocks, a window comparator 8 that compares the video signal of the human input with the video signal of the shift register 1 delayed by 4 clocks, window comparators 4, 5, 6, 7. It is constructed by comprising an AND circuit 9 and the like which performs a logical product of the outputs of 8.

Next, the operation of the embodiment shown in FIG. 1 will be explained. This circuit is premised on handling digitized composite video signals. Assume that it is converted to an 8-bit digital signal? may be 7 bits or 9 bits depending on the case.

The video signal expressed as an 8-bit digital signal is transmitted through a 4-clock shift register 1, a window comparator 5,
6, 7. 8 is input. Further, video signals delayed by 1 clock, 2 clocks, 3 clocks, and 4 clocks are output from the shift register 1, and are input to window comparators 5, 6, 7, and 8, respectively. Window comparators 5, 6, 7. 8 is the level " when the absolute value of the input difference + x - y + is less than the preset value d1
1” is output.

Therefore, the condition for outputting "1" from the window comparator 5 is that the difference between the current video signal and the video signal one clock ago is less than d1. Similarly, the condition for "1" to be output from the window converter 6 is when the difference between the current video signal and the video signal two clocks ago is less than d1; This is when the difference between the video signal and the video signals before the 3rd and 4th clock is less than d■.

Window comparators 5, 6, 7. The output of the window comparator 4 is added to the output of the window comparator 8, and an AND circuit 9 performs a logical product. Now, if we exclude the output from window comparator 4, window comparators 5, 6,
7. The AND of the outputs of 8 becomes "1" when the difference between the current video signal and the video signal four clocks earlier is 2d1 or less. This means that, based on the video signal delayed by 4 clocks (hereinafter referred to as Sa), the video signal up to 4 clocks later is within a certain width of 2d.

FIG. 2 shows a video signal near Sa. The vertical axis represents the level of the video signal, and the horizontal axis represents the passage of time.

The level of the video signal (to the left of Sa) before Sa changes greatly, but it is less than 2d during the four clocks after Sa. At this time, window comparators 5, 6, 7.
All outputs of 8 become "1".

The window comparator 4 compares the outputs of Sa and the IH memory 2, and outputs a level "61" when the absolute value lx-yl of the difference between the inputs exceeds d2.

That is, when the difference between Sa and the video signal one scanning line before is d2 or more, the output becomes "°1".

FIG. 3 shows Sa and the video signal before one scanning line.

Here, since the difference is greater than d2, the output of the window comparator 4 is ""P9.

FIG. 4 is a summary of FIGS. 2 and 3.

The AND circuit 9 is the logical product of the window comparator 4 and the window comparator 8, so it is AN.
The output of the D circuit 9 becomes "1" when the video signal after four clocks from Sa and one scanning line before becomes as shown in FIG. Video signals of adjacent scanning lines have a property that they are related. On the other hand, video noise often appears as a signal at a certain level during a period shorter than one scanning line. In the case of Figure 4, the difference in video signals between one scanning line is d
Since the level change is large at 2 or more and the change in level during a certain period within the scanning line is small at d1 or less, there is a high possibility that the area after Sa is video noise. At this time, AND circuit 9
Since the output of ``1'' becomes ``1'', switch the video switch 3 and
The contents of the H memory, that is, the video signal of one scanning line or earlier is output. Since the video signals of adjacent scanning lines are related, even if they are replaced, there is little effect, and video noise can be reduced. At the same time, since a video signal that does not include video noise is input to the 1H memory 2, an appropriate video signal is always stored for replacement. When the output of the AND circuit 9 becomes "0", that is, when the conditions shown in FIG. 4 are not satisfied, it is not video noise, so the video switcher 3 outputs Sa, and also inputs Sa to the IH memory.

[Effect of the Invention J As explained above, the present invention has the advantage that video signals often have a relationship between adjacent scanning lines, and moreover, often appear at a predetermined video level within one scanning line. By focusing on this, we set the conditions for considering it as video noise, and when video noise occurs, we replace it with the video signal from the l scanning line or earlier, thereby reducing video noise very effectively. It has the unique effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing changes in the level of a video signal between four clocks, and FIG. 3 is a diagram showing changes in the level of a video signal between one scanning line. The diagram shown in FIG. 4 is a diagram showing changes in the level of the video signal between four clocks and between one scanning line. [Description of symbols] 1... 4-clock shift register, 2... IH memory for recording one scanning line of video signal, 3... Video signal of shift register 1 and video signal of 1H memory 2 4...Window comparator 15...Compares the video signal of the shift register 1 with the video signal of the IH memory.Compares the input video signal with the video signal of the shift register 1 delayed by one clock. 6... A window comparator that compares the input video signal with the video signal of the shift register 1 delayed by 2 clocks, 7... The input video signal and the video signal of the shift register 1 delayed by 3 clocks. 8... A window comparator that compares the input video signal with the video signal of the shift register 1 delayed by 4 clocks, 9... Window comparator 4,
AND circuit that takes the AND of the outputs of 5, 6, 7, and 8.

Claims (1)

[Claims] (1) A memory capable of recording one scanning line of the video signal, a shift register that delays the video signal, and a window comparator that compares the video signal delayed by the memory and shift register with the current video signal; A video noise reduction device characterized by having a video switcher that switches between two systems of video signals, the current one and the one delayed by one scanning line.