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EP0843890A1 - Appareil et procede permettant un depot ameliore de couches minces de revetement et de fiches conformes dans des contacts a fort allongement - Google Patents

Appareil et procede permettant un depot ameliore de couches minces de revetement et de fiches conformes dans des contacts a fort allongement

Info

Publication number
EP0843890A1
EP0843890A1 EP97919587A EP97919587A EP0843890A1 EP 0843890 A1 EP0843890 A1 EP 0843890A1 EP 97919587 A EP97919587 A EP 97919587A EP 97919587 A EP97919587 A EP 97919587A EP 0843890 A1 EP0843890 A1 EP 0843890A1
Authority
EP
European Patent Office
Prior art keywords
substrate
contacts
target
biasing
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97919587A
Other languages
German (de)
English (en)
Inventor
Corey A. Weiss
Bruce Gittleman
Jeffrey M. Bulson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Sony Corp
Materials Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Materials Research Corp filed Critical Sony Corp
Publication of EP0843890A1 publication Critical patent/EP0843890A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates

Definitions

  • This invention relates generally to the formation of
  • invention relates to the formation of conductive liners
  • apertures are oftentimes referred to in the art as contacts or vias
  • the contacts are
  • the metal plug is any metal plug.
  • the metal plug is any metal plug.
  • interconnect layers make electrical contact to the semiconductor
  • the contacts are formed in the various metal
  • interconnect layers by etching, masking or other techniques known
  • the interconnecting metal layers or plugs are deposited into the contact to provide for the electrical interconnection between the
  • Such films and layers can be deposited by generally known
  • CVD chemical vapor deposition
  • physical vapor deposition physical vapor deposition
  • PVD vapor deposition
  • sputter deposition In sputter deposition, a target of
  • a working gas is introduced into the vacuum chamber
  • the target is
  • the dislodged or sputtered material deposits onto the substrate
  • ratio of a contact is the ratio of the contact length to its width (or
  • aspect ratios e.g., aspect ratios ⁇ 1 .5.
  • the plate collimator is typically positioned parallel
  • a collimator has a series of tubes, the walls of which intercept some of the material sputtered from the target.
  • the collimator tubes increases, and a greater percentage of the total
  • the invention allows lower aspect ratio collimators to
  • the invention allows greater utilization of the collimator by
  • nitride will generally produce films which exhibit low resistivity, low impurity concentrations and regular crystal morphologies.
  • deposition inside the contact still may be generally non-uniform
  • Fig. 1 illustrates a substrate 10 having an upper surface
  • substrate 1 0 has sidewall 1 8 and a bottom surface 20.
  • overhang protrudes into the contact
  • a conductive liner film 26 such as titanium or titanium
  • nitride might be deposited by sputter deposition or CVD (see Fig.
  • layer of aluminum might be deposited by sputtering or a plug layer
  • void 30 therein often referred to as a keyhole.
  • keyholes Such keyholes
  • the present invention provides improved bottom and
  • the invention is utilized to deposit liner films
  • the present invention reduces the overhang
  • the invention further facilitates plugging
  • the present invention utilizes a sputter deposition
  • biasing system which is operably coupled to the substrate during
  • the collimator is
  • An electrical biasing system is operably coupled to the substrate
  • the collimator provides near-normal incidence of the
  • the collimator affects the ion bombardment
  • the present invention provides more uniform conformal liner layer
  • deposited into the contacts are generally free of voids or keyholes
  • the sheet is collimation without substrate bias.
  • the sheet is collimation without substrate bias.
  • the sheet is collimation without substrate bias.
  • a collimator having an aspect ratio between 1 and 2 is utilized.
  • the present invention is particularly concerned with the present invention
  • Fig. 1 is a cross-sectional view of a contact having a
  • Fig. 2 is a cross-sectional view of a contact
  • Fig. 3 is a diagrammatic cross-sectional view of a
  • Fig. 4A is a graph of deposition rate and substrate
  • Fig. 4B is a graph of
  • Fig. 4C is a graph of the ratio of net sputtered flux
  • Fig. 4D is a bar graph of deposition rate as a function
  • Fig. 5A is a bar graph of the measured resistivity of a
  • Fig. 5B is a
  • Figs. 6A, 6B and 6C are sheet resistance uniformity
  • Fig. 7 is a bar graph of the measured reflectivity of
  • FIGs. 8A, 8B and 8C are photographs of various components
  • substrate contact liners with a conformal film deposited with 450 V
  • Fig. 3 illustrates an equipment configuration for
  • system 30 for practicing the present invention includes a
  • processing housing 32 which defines therein a processing chamber
  • Housing 32 is operably coupled to a
  • a substrate 38 is supported on a
  • substrate support 40 which is preferably operable to clamp
  • a target mount 42 which is bonded to a target 44 of material to be
  • a collimator 46 having a plurality of apertures 48 defined therein.
  • the apertures 48 may be
  • collimator 46 provides
  • a shield 50 surrounds target 44 and prevents sputter
  • deposition particles from depositing onto the walls of chamber 34.
  • the shield 50 is preferably grounded and may be removed and
  • the target support 42 and target 44 are electrically connected
  • target 44 is negatively biased with respect to
  • collimator 46 which is maintained at ground potential.
  • gas is introduced into chamber 34 from a process gas
  • the gas is preferably introduced between the cathode
  • a plasma which is illustrated in Fig. 3 as a
  • plasma cloud 56 Contained within plasma cloud 56 are various
  • particles 60 travel in the process chamber 34 toward substrate 38.
  • the apertures 48 of collimator 46 have a defined
  • collimator 46 As may be appreciated, collimator apertures 48 with
  • high aspect ratios have deep depths 62 and/or narrow widths 64
  • collimator apertures having smaller aspect ratios i.e., wide
  • sputter particle 60b has an
  • sputtered particle 60a has a flight
  • collimator apertures 48 to pass through the collimator and deposit
  • Collimators generally are utilized to provide sputter deposition of
  • collimator 46 generally be intercepted by collimator 46. The greater the aspect
  • collimators provide assistance in filling contacts by
  • collimator with a high aspect ratio apertures such as 2.5 or above
  • invention provides conformal coating of high aspect ratio contacts
  • the present invention provides a conformal liner in a
  • substrate support 40 and substrate 38 are operably connected
  • substrate 38 is
  • Substrate 38 is negatively biased with respect to the
  • collimator 46 which is typically maintained at ground potential.
  • Ionized plasma particles of plasma cloud 56 such as particles 59
  • Ionized particles 59 are attracted to surface 45 and
  • invention provides collimated etching and focuses the etching
  • One particular advantage of the invention is the
  • the invention provides increased yield of
  • etching of the invention are acceptable for the industry.
  • Substrates were processed with no bias (zero volts), 200 and 400 volt DC bias, and 250 and 450 volt RF bias (at 1 3.56
  • the collimator utilized had an aspect ratio of 1 .5, and
  • the sputter cathode utilized was an ICC-1 2 rotating
  • the magnet with a Ti target was maintained at 1 .452 inches.
  • the rotating magnet behind the target was maintained at 1 .452 inches.
  • Deposition rate was measured as a function of RF and
  • the film proximate the strip is measured for calculation of the
  • Model P-1 Long Scan Profiler available from
  • Fig. 4A illustrates graphs of measured wafer-to-ground
  • Fig. 4B illustrates a graph of deposition rate and wafer-
  • the sheet resistance was measured at the wafer
  • Resistivity was derived by multiplying
  • the resistivity of the wafer tended to increase with the
  • the deposited layer as it is contemporaneously etched during
  • titanium is expected during biased deposition which will also act to
  • Fig. 5B illustrates the sheet resistance uniformity
  • the sheet resistant uniformity generally improves with
  • Figs. 6A, 6B and 6C illustrate the improved sheet
  • FIG. 6A illustrates the interwafer sheet resistance uniformity for zero volts bias
  • Figs. 6B and 6C illustrate the interwafer sheet resistance uniformity
  • the substrate of Fig. 6C has a substantially improved sheet
  • NanoSpec/AFT Microarea Gauge available from Nanometrics of
  • the present invention further provides improved step
  • FIGs. 8A, 8B and 8C are photographs of
  • Figs. 8A-8C show a deposition of titanium in sub-0.5
  • Fig. 8A illustrates a contact 90
  • the deposited film 92 is conformal
  • FIG. 8B illustrates a more narrow contact 98
  • the film 1 00 is very conformal and does
  • the film 1 00 is

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

L'invention porte sur un système et un procédé de métallisation sous vide comprenant un système à vide (36), une cible (44), un collimateur (46) et un substrat (38). La cible (44) est polarisée et bombardée pour déposer une couche d'un matériau sur le substrat (38) en passant par un collimateur (46). Le substrat (38) peut être polarisé pour permettre son attaque en même temps que le dépôt.
EP97919587A 1996-04-26 1997-04-15 Appareil et procede permettant un depot ameliore de couches minces de revetement et de fiches conformes dans des contacts a fort allongement Withdrawn EP0843890A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63829096A 1996-04-26 1996-04-26
US638290 1996-04-26
PCT/IB1997/000522 WO1997041598A1 (fr) 1996-04-26 1997-04-15 Appareil et procede permettant un depot ameliore de couches minces de revetement et de fiches conformes dans des contacts a fort allongement

Publications (1)

Publication Number Publication Date
EP0843890A1 true EP0843890A1 (fr) 1998-05-27

Family

ID=24559418

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97919587A Withdrawn EP0843890A1 (fr) 1996-04-26 1997-04-15 Appareil et procede permettant un depot ameliore de couches minces de revetement et de fiches conformes dans des contacts a fort allongement

Country Status (7)

Country Link
EP (1) EP0843890A1 (fr)
JP (1) JPH11509049A (fr)
KR (1) KR19990028451A (fr)
AU (1) AU2400497A (fr)
CA (1) CA2225446A1 (fr)
TW (1) TW417223B (fr)
WO (1) WO1997041598A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002007198A2 (fr) * 2000-07-18 2002-01-24 Applied Materials, Inc. Depot de films de tantale de faible contrainte
JP2005082873A (ja) * 2003-09-10 2005-03-31 Applied Materials Inc 膜形成方法
EP2201148B1 (fr) * 2007-10-26 2011-09-28 OC Oerlikon Balzers AG Application de hipims (pulvérisation cathodique magnétron à impulsions haute puissance) à des trous d'interconnexion en silicium par métallisation lors de l'encapsulation d'une plaquette en trois dimensions
US20100096253A1 (en) * 2008-10-22 2010-04-22 Applied Materials, Inc Pvd cu seed overhang re-sputtering with enhanced cu ionization

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4925542A (en) * 1988-12-08 1990-05-15 Trw Inc. Plasma plating apparatus and method
EP0735577A3 (fr) * 1994-12-14 1997-04-02 Applied Materials Inc Procédé et appareillage de dépÔt

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9741598A1 *

Also Published As

Publication number Publication date
JPH11509049A (ja) 1999-08-03
TW417223B (en) 2001-01-01
AU2400497A (en) 1997-11-19
CA2225446A1 (fr) 1997-11-06
KR19990028451A (ko) 1999-04-15
WO1997041598A1 (fr) 1997-11-06

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