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WO2003042424A1 - Plasma auto-ionise et a couplage inductif destine a une pulverisation et a une repulverisation - Google Patents

Plasma auto-ionise et a couplage inductif destine a une pulverisation et a une repulverisation Download PDF

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Publication number
WO2003042424A1
WO2003042424A1 PCT/US2002/036940 US0236940W WO03042424A1 WO 2003042424 A1 WO2003042424 A1 WO 2003042424A1 US 0236940 W US0236940 W US 0236940W WO 03042424 A1 WO03042424 A1 WO 03042424A1
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WO
WIPO (PCT)
Prior art keywords
target
chamber
plasma
substrate
level
Prior art date
Application number
PCT/US2002/036940
Other languages
English (en)
Inventor
Peijun Ding
Rong Tao
Zheng Xu
Daniel C. Lubben
Suraj Rengarajan
Michael A. Miller
Arvind Sundarrajan
Xianmin Tang
John C. Forster
Jianming Fu
Roderick C. Mosely
Fusen Chen
Praburam Gopalraja
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/685,978 external-priority patent/US6582569B1/en
Priority claimed from US09/993,543 external-priority patent/US6610184B2/en
Priority claimed from US10/202,778 external-priority patent/US20030116427A1/en
Priority to KR1020107009485A priority Critical patent/KR101179726B1/ko
Priority to JP2003544237A priority patent/JP5296956B2/ja
Priority to US10/495,506 priority patent/US8696875B2/en
Priority to KR1020127010137A priority patent/KR101312690B1/ko
Priority to KR1020047007317A priority patent/KR100993046B1/ko
Priority to CN028271017A priority patent/CN1656243B/zh
Priority to KR1020107009487A priority patent/KR101179727B1/ko
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Publication of WO2003042424A1 publication Critical patent/WO2003042424A1/fr
Priority to US10/608,306 priority patent/US7041201B2/en
Priority to US11/124,524 priority patent/US7569125B2/en
Priority to US11/184,615 priority patent/US20050255691A1/en
Priority to US11/933,157 priority patent/US8668816B2/en
Priority to US12/182,988 priority patent/US20090233438A1/en
Priority to US14/205,260 priority patent/US10047430B2/en
Priority to US16/033,166 priority patent/US20180327893A1/en

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    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • C—CHEMISTRY; METALLURGY
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3435—Applying energy to the substrate during sputtering
    • C23C14/345—Applying energy to the substrate during sputtering using substrate bias
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3457—Sputtering using other particles than noble gas ions
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C23C14/354—Introduction of auxiliary energy into the plasma
    • C23C14/358—Inductive energy
    • H—ELECTRICITY
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    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H—ELECTRICITY
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
    • H01J37/3402—Gas-filled discharge tubes operating with cathodic sputtering using supplementary magnetic fields
    • H01J37/3405—Magnetron sputtering
    • H01J37/3408—Planar magnetron sputtering
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/332—Coating
    • H01J2237/3322—Problems associated with coating
    • H01J2237/3327—Coating high aspect ratio workpieces
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers

Definitions

  • the invention relates generally to sputtering and resputtering.
  • the invention relates to the sputter deposition of material and resputtering of deposited material in the formation of semiconductor integrated circuits.
  • Semiconductor integrated circuits typically include multiple levels of metallization to provide electrical connections between large numbers of active semiconductor devices.
  • Advanced integrated circuits particularly those for microprocessors, may include five or more metallization levels.
  • aluminum has been the favored metallization, but copper has been developed as a metallization for advanced integrated circuits.
  • a typical metallization level is illustrated in the cross-sectional view of FIG. 1.
  • a lower-level layer 110 includes a conductive feature 112. If the lower-level layer 110 is a lower-level dielectric layer, such as silica or other insulating material, the conductive feature 112 may be a lower-level copper metallization, and the vertical portion of the upper-level metallization is referred to as a via since it interconnects two levels of metallization. If the lower-level layer 110 is a silicon layer, the conductive feature 112 may a doped silicon region, and the vertical portion of the upper-level metallization formed in a hole is referred to as a contact because it electrically contacts silicon.
  • An upper-level dielectric layer 114 is deposited over the lower-level dielectric layer 110 and the lower-level metallization 112.
  • the holes include lines and trenches.
  • the holes have a complex shape. In some applications, the hole may not extend through the dielectric layer. The following discussion will refer to only via holes, but in most circumstances the discussion applies equally well to other types of holes with only a few modifications well known in the art.
  • the dielectric is silicon oxide formed by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS) as the precursor.
  • PECVD plasma-enhanced chemical vapor deposition
  • TEOS tetraethylorthosilicate
  • low-k materials of other compositions and deposition techniques are being considered.
  • Some of the low-k dielectrics being developed can be characterized as silicates, such as fluorinated silicate glasses.
  • silicate (oxide) dielectrics will be directly described, but it is contemplated that other dielectric compositions may be used.
  • a via hole is etched into the upper-level dielectric layer 114 typically using, in the case of silicate dielectrics, a fluorine-based plasma etching process.
  • the via holes may have widths as low as 0.18 ⁇ m or even less.
  • the thickness of the dielectric layer 114 is usually at least 0.7 ⁇ m, and sometimes twice this, so that the aspect ratio of the hole may be 4:1 or greater. Aspect ratios of 6:1 and greater are being proposed.
  • the via hole should have a vertical profile.
  • a liner layer 116 may be deposited onto the bottom and sides of the hole and above the dielectric layer 114.
  • the liner 116 can perform several functions. It can act as an adhesion layer between the dielectric and the metal since metal films tend to peel from oxides. It can also act as a barrier against inter-diffusion between the oxide-based dielectric and the metal. It may also act as a seed and nucleation layer to promote the uniform adhesion and growth and possibly low-temperature reflow for the deposition of metal filling the hole and to nucleate the even growth of a separate seed layer.
  • One or more liner layers may be deposited, in which one layer may function primarily as a barrier layer and others may function primarily as adhesion, seed or nucleation layers.
  • a conductive metal such as copper, for example
  • Conventional aluminum metallizations are patterned into horizontal interconnects by selective etching of the planar portion of the metal layer 118.
  • a technique for copper metallization called dual damascene, forms the hole in the dielectric layer 114 into two connected portions, the first being narrow vias through the bottom portion of the dielectric and the second being wider trenches in the surface portion which interconnect the vias.
  • CMP chemical mechanical polishing
  • An aspect ratio as used herein is defined as the ratio of the depth of the hole to narrowest width of the hole, usually near its top surface. Via widths of 0.18 ⁇ m are also common and the value will further decrease.
  • the diffusion barrier may be formed from a bilayer of Ta/TaN, W7WN, or Ti/TiN, or of other structures. Barrier thicknesses of 10 to 50nm are typical. For copper interconnects, it has been found useful to deposit one or more copper layers to fulfill the nucleation and seed functions.
  • PVD physical vapor deposition
  • a DC magnetron sputtering reactor has a target which is composed of the metal to be sputter deposited and which is powered by a DC electrical source. The magnetron is scanned about the back of the target and projects its magnetic field into the portion of the reactor adjacent the target to increase the plasma density there to thereby increase the sputtering rate.
  • conventional DC sputtering (which will be referred to as PVD in contrast to other types of sputtering to be introduced) predominantly sputters neutral atoms.
  • the typical ion densities in PVD are often less than 10 9 cm "3 .
  • PVD also tends to sputter atoms into a wide angular distribution, typically having a cosine dependence about the target normal.
  • Such a wide distribution can be disadvantageous for filling a deep and narrow via hole 122 such as that illustrated in FIG. 2, in which a barrier layer 124 has already been deposited.
  • the large number of off-angle sputter particles can cause a layer 126 to preferentially deposit around the upper corners of the hole 122 and form overhangs 128. Large overhangs can further restrict entry into the hole 122 and cause inadequate coverage of the sidewalls 130 and bottom 132 of the hole 122.
  • the overhangs 128 can bridge the hole 122 before it is filled and create a void 134 in the metallization within the hole 122.
  • a void 134 Once a void 134 has formed, it is often difficult to reflow it out by heating the metallization to near its melting point. Even a small void can introduce reliability problems. If a second metallization deposition step is planned, such as by electroplating, the bridged overhang make subsequent deposition more difficult. [0011]
  • One approach to ameliorate the overhang problem is long-throw sputtering in which the sputtering target is spaced relatively far from the wafer or other substrate being sputter coated.
  • the target-to-wafer spacing can be at least 50% of wafer diameter, preferably more than 90%, and more preferably more than 140%.
  • the off-angle portion of the sputtering distribution is preferentially directed to the chamber walls, but the central-angle portion remains directed substantially to the wafer.
  • the truncated angular distribution can cause a higher fraction of the sputter particles to be directed deeply into the hole 122 and reduce the extent of the overhangs 128.
  • a similar effect can be accomplished by positioning a collimator between the target and wafer. Because the collimator has a large number of holes of high aspect ratio, the off-angle sputter particles tend to strike the sidewalls of the collimator, and the central-angle particles tend to pass through.
  • Both long-throw targets and collimators typically reduce the flux of sputter particles reaching the wafer and thus tend to reduce the sputter deposition rate. The reduction can become more pronounced as throws are lengthened or as collimation is tightened to accommodate via holes of increasing aspect ratios. [0012] Also, the length that long throw sputtering may be increased may be limited. At the few milliTorr of argon pressure often used in PVD sputtering, there is a greater possibility of the argon scattering the sputtered particles as the target to wafer spacing increases. Hence, the geometric selection of the forward particles may be decreased.
  • a yet further problem with both long throw and collimation is that the reduced metal flux can result in a longer deposition period which can not only reduce throughput, but also tends to increase the maximum temperature the wafer experiences during sputtering. Still further, long throw sputtering can reduce over hangs and provide good coverage in the middle and upper portions of the sidewalls, but the lower sidewall and bottom coverage can be less than satisfactory.
  • Another technique for deep hole lining and filling is sputtering using a high-density plasma (HDP) in a sputtering process called ionized metal plating (IMP).
  • HDP high-density plasma
  • IMP ionized metal plating
  • a typical high-density plasma is one having an average plasma density across the plasma, exclusive of the plasma sheaths, of at least 10 11 cm “3 , and preferably at least 10 12 cm “3 .
  • a separate plasma source region is formed in a region away from the wafer, for example, by inductively coupling RF power into a plasma from an electrical coil wrapped around a plasma source region between the target and the wafer.
  • the plasma generated in this fashion is referred to as an inductively coupled plasma (ICP).
  • ICP inductively coupled plasma
  • An HDP chamber having this configuration is commercially available from Applied Materials of Santa Clara, California as the HDP PVD Reactor. Other HDP sputter reactors are available.
  • the higher power ionizes not only the argon working gas, but also significantly increases the ionization fraction of the sputtered atoms, that is, produces metal ions.
  • the wafer either self-charges to a negative potential or is RF biased to control its DC potential.
  • the metal ions are accelerated across the plasma sheath as they approach the negatively biased wafer. As a result, their angular distribution becomes strongly peaked in the forward direction so that they are drawn deeply into the via hole. Overhangs become much less of a problem in IMP sputtering, and bottom coverage and bottom sidewall coverage are relatively high.
  • IMP sputtering using a remote plasma source is usually performed at a higher pressure such as 30 milliTorr or higher.
  • the higher pressures and a high- density plasma can produce a very large number of argon ions, which are also accelerated across the plasma sheath to the surface being sputter deposited.
  • the argon ion energy is often dissipated as heat directly into the film being formed.
  • Copper can dewet from tantalum nitride and other barrier materials at elevated temperatures experienced in IMP, even at temperatures as low at 50 to 75 C. Further, the argon tends to become embedded in the developing film.
  • IMP can deposit a copper film as illustrated at 136 in the cross-sectional view of FIG.
  • SSS SSS
  • a sufficiently high density of copper ions develops that the copper ions will resputter the copper target with yield over unity.
  • the supply of argon working gas can then be eliminated or at least reduced to a very low pressure while the copper plasma persists.
  • Aluminum is believed to be not readily susceptible to SSS.
  • Some other materials, such as Pd, Pt, Ag, and Au can also undergo SSS.
  • Depositing copper or other metals by sustained self-sputtering of copper has a number of advantages.
  • the sputtering rate in SSS tends to be high.
  • There is a high fraction of copper ions which can be accelerated across the plasma sheath and toward a biased wafer, thus increasing the directionality of the sputter flux.
  • Chamber pressures may be made very low, often limited by leakage of backside cooling gas, thereby reducing wafer heating from the argon ions and decreasing scattering of the metal particles by the argon.
  • SIP sputtering uses a variety of modifications to a fairly conventional capacitively coupled magnetron sputter reactor to generate a high-density plasma (HDP) adjacent to the target and to extend the plasma and guide the metal ions toward the wafer.
  • HDP high-density plasma
  • Relatively high amounts of DC power are applied to the target, for example, 20 to 40kW for a chamber designed for 200mm wafers.
  • the magnetron has a relatively small area so that the target power is concentrated in the smaller area of the magnetron, thus increasing the power density supplied to the HDP region adjacent the magnetron.
  • the small-area magnetron is disposed to a side of a center of the target and is rotated about the center to provide more uniform sputtering and deposition.
  • the magnetron has unbalanced poles, usually a strong outer pole of one magnetic polarity surrounding a weaker inner pole of the other polarity.
  • the magnetic field lines emanating from the stronger pole may be decomposed into not only a conventional horizontal magnetic field adjacent the target face but also a vertical magnetic field extending toward the wafer.
  • the vertical field lines extend the plasma closer toward the wafer and also guide the metal ions toward the wafer.
  • the vertical magnetic lines close to the chamber walls act to block the diffusion of electrons from the plasma to the grounded shields. The reduced electron loss is particularly effective at increasing the plasma density and extending the plasma across the processing space.
  • SIP sputtering may be accomplished without the use of RF inductive coils.
  • the small HDP region is sufficient to ionize a substantial fraction of metal ions, estimated to be between 10 and 25%, which effectively sputter coats into deep holes.
  • the ionized sputtered metal atoms are attracted back to the targets and sputter yet further metal atoms.
  • the argon working pressure may be reduced without the plasma collapsing. Therefore, argon heating of the wafer is less of a problem, and there is reduced likelihood of the metal ions colliding with argon atoms, which would both reduce the ion density and randomize the metal ion sputtering pattern.
  • a further advantage of the unbalanced magnetron used in SIP sputtering is that the magnetic field from the stronger, outer annular pole projects far into the plasma processing area towards the wafer.
  • This projecting field has the advantage of supporting a strong plasma over a larger extent of the plasma processing area and to guide ionized sputter particles towards the wafer.
  • the magnetic coil is particularly effective in combining SIP sputtering in a long-throw sputter reactor, that is, one having a larger spacing between the target and the wafer because the auxiliary magnetic field supports the plasma and further guides the ionized sputter particles.
  • Lai discloses in US Patent 5,593,551 a smaller coil in near the target.
  • Metal may also be deposited by chemical vapor deposition (CVD) using metallo-organic precursors, such as Cu-HFAC-VTMS, commercially available from Schumacher in a proprietary blend with additional additives under the trade name CupraSelect.
  • CVD chemical vapor deposition
  • a thermal CVD process may be used with this precursor, as is very well known in the art, but plasma enhanced CVD (PECVD) is also possible.
  • PECVD plasma enhanced CVD
  • the CVD process is capable of depositing a nearly conformal film even in the high aspect-ratio holes.
  • a film may be deposited by CVD as a thin seed layer, and then PVD or other techniques may be used for final hole filling.
  • CVD copper seed layers have often been observed to be rough.
  • the roughness can detract from its use as a seed layer and more particularly as a reflow layer promoting the low temperature reflow of after deposited copper deep into hole. Also, the roughness indicates that a relatively thick CVD copper layer of the order of 50nm may be needed to reliably coat a continuous seed layer. For the narrower via holes now being considered, a CVD copper seed layer of a certain thickness may nearly fill the hole. However, complete fills performed by CVD can suffer from center seams, which may impact device reliability.
  • Electrochemical plating is yet another copper deposition technique that is being developed. In this method, the wafer is immersed in a copper electrolytic bath. The wafer is electrically biased with respect to the bath, and copper electrochemically deposits on the wafer in a generally conformal process. Electroless plating techniques are also available. Electroplating and its related processes are advantageous because they can be performed with simple equipment at atmospheric pressure, the deposition rates are high, and the liquid processing is consistent with the subsequent chemical mechanical polishing.
  • Electroplating however, imposes its own requirements.
  • a seed and adhesion layer is usually provided on top of the barrier layer, such as of Ta/TaN, to nucleate the electroplated copper and adhere it to the barrier material.
  • the generally insulating structure surrounding the via hole 122 requires that an electroplating electrode be formed between the dielectric layer 114 and the via hole 122.
  • Tantalum and other barrier materials are typically relatively poor electrical conductors, and the usual nitride sublayer of the barrier layer 124 which faces the via hole 122 (containing the copper electrolyte) is even less conductive for the long transverse current paths needed in electroplating.
  • a good conductive seed and adhesion layer are often deposited to facilitate the electroplating effectively filling the bottom of the via hole.
  • a copper seed layer deposited over the barrier layer 124 is typically used as the electroplating electrode. However, a continuous, smooth, and uniform film is preferred. Otherwise, the electroplating current will be directed only to the areas covered with copper or be preferentially directed to areas covered with thicker copper. Depositing the copper seed layer presents its own difficulties. An IMP deposited seed layer provides good bottom coverage in high aspect-ratio holes, but its sidewall coverage can be small such that that the resulting thin films can be rough or discontinuous. A thin CVD deposited seed can also be too rough. A thicker CVD seed layer, or CVD copper over IMP copper, may require an excessively thick seed layer to achieve the required continuity. Also, the electroplating electrode primarily operates on the entire hole sidewalls so that high sidewall coverage is desired. Long throw provides adequate sidewall coverage, but the bottom coverage may not be sufficient.
  • One embodiment of the present invention is directed to sputter depositing a liner material such as tantalum or tantalum nitride, by combining long- throw sputtering, self-ionized plasma (SIP) sputtering, inductively-coupled plasma (ICP) resputtering, and coil sputtering in one chamber.
  • SIP self-ionized plasma
  • ICP inductively-coupled plasma
  • Long-throw sputtering is characterized by a relatively high ratio of the target-to-substrate distance and the substrate diameter.
  • Long-throw SIP sputtering promotes deep hole coating of both the ionized and neutral deposition material components. ICP resputtering can reduce the thickness of layer bottom coverage of deep holes to reduce contact resistance.
  • ICP coil sputtering can deposit a protective layer, particularly on areas such as adjacent the hole openings where thinning by resputtering may not be desired.
  • Another embodiment of the present invention is directed to sputter depositing an interconnect material such as copper, by combining long-throw sputtering, self-ionized plasma (SIP) sputtering and SIP resputtering in one chamber.
  • SIP self-ionized plasma
  • SIP resputtering can redistribute the deposition to promote good bottom corner coverage of deep holes.
  • SIP tends to be promoted by low pressures of less than 5 milliTorr, preferably less than 2 milliTorr, and more preferably less than 1 milliTorr.
  • SIP tends to be promoted by magnetrons having relatively small areas to thereby increase the target power density, and by magnetrons having asymmetric magnets causing the magnetic field to penetrate farther toward the substrate.
  • Such a process may be used to deposit a seed layer, promoting the nucleation or seeding of an after deposited layer, particularly useful for forming narrow and deep vias or contacts through a dielectric layer.
  • a further layer may be deposited by electrochemical plating (ECP).
  • a further layer is be deposited by chemical vapor deposition (CVD).
  • One embodiment includes an auxiliary magnet array in a magnetron sputter reactor disposed around the chamber close to the wafer and having a first vertical magnetic polarity.
  • the magnets may either be permanent magnets or an array of electromagnets having coil axes along the central axis of the chamber.
  • a rotatable magnetron having a strong outer pole of the first magnetic polarity surrounds a weaker pole of the opposite polarity.
  • the auxiliary magnets are preferably located in the half of the processing space near the wafer to pull the unbalanced portion of the magnetic field from the outer pole towards the wafer.
  • Resputtering in an SIP chamber may be promoted in multiple steps in which, in one embodiment, biasing of the wafer is increased during deposition. Alternatively, power to the target may be decreased during deposition to redistribute deposition to the bottom corners of vias and other holes.
  • FIG. 1 is a cross-sectional view of a via filled with a metallization, which also covers the top of the dielectric, as practiced in the prior art.
  • FIG. 2 is a cross-sectional view of a via during its filling with metallization, which overhangs and closes off the via hole.
  • FIG.3 is a cross-sectional view of a via having a rough seed layer deposited by ionized metal plating.
  • FIG.4 is a schematic representation of a sputtering chamber usable with an embodiment of the invention.
  • FIG.5 is a schematic representation of electrical interconnections of various components of the sputtering chamber of FIG. 4.
  • FIGS. 6-9B are cross-sectional views of a via liner and metallization and formation process for a via liner and metallization according to one embodiment of the invention.
  • FIG. 10 is a schematic cross-sectional view of a sputter reactor including an auxiliary magnet array of the invention.
  • FIG. 11 is bottom plan view of the top magnetron in the sputter reactor of FIG. 10.
  • FIG. 12 is an orthographic view of an embodiment of an assembly supporting an auxiliary magnet array.
  • FIG. 13 is a schematic cross-sectional view of a sputter reactor in which the auxiliary magnet array includes an array of electromagnets.
  • FIGS. 14A and 14B are cross-sectional views of a via seed layer and via seed layer formation process according to one embodiment of the invention.
  • FIG. 15 is a schematic representation of another sputtering chamber usable with the invention.
  • FIG. 16 is an exploded view of a portion of FIG. 15 detailing the target, shields, isolators and target O-ring.
  • FIG. 17 is a graph illustrating the relationship between the length of the floating shield and the minimum pressure for supporting a plasma.
  • FIG. 18 is a cross-sectional view of via metallization according to another embodiment of the invention.
  • FIGS. 19 and 20 are graphs plotting ion current flux across the wafer for two different magnetrons and different operating conditions.
  • FIG. 21 is a cross-sectional view of a via metallization according to another embodiment of the invention.
  • FIG. 22 is a cross-sectional view of a via metallization according to another embodiment of the invention.
  • FIG. 23 is a flow diagram of a plasma ignition sequence which reduces heating of the wafer.
  • FIG.24 is a cross-sectional view of via metallization formed in accordance with a process according to another embodiment of the invention.
  • FIG.25 is a schematic representation of a sputtering chamber in accordance with another embodiment of the invention.
  • FIG.26 is a schematic representation of electrical interconnections of various components of the sputtering chamber of FIG.25.
  • FIG. 27 is a schematic view of a integrated processing tool on which the invention may be practiced.
  • the distribution between sidewall and bottom coverage in a DC magnetron sputtering reactor can be tailored to produce a metal layer such as a liner layer having a desired profile in a hole or via in a dielectric layer.
  • a SIP film sputter deposited into a high-aspect ratio via can have favorable upper sidewall coverage and tends not to develop overhangs.
  • bottom coverage may be thinned or eliminated by ICP resputtering of the bottom of the via.
  • the advantages of both types of sputtering can be obtained in a reactor which combines selected aspects of both SIP and ICP plasma generation techniques, which may be in separate steps.
  • An example of such a reactor is illustrated generally at 150 in Fig. 4.
  • a liner layer sidewall may be protected from resputtering by sputtering an ICP coil 151 located within the chamber to deposit coil material onto the substrate.
  • the reactor 150 may also be used to sputter deposit a metal layer such as a barrier or liner layer using both SIP and ICP generated plasmas, preferably in combination, but alternatively, alternately.
  • the distribution between ionized and neutral atomic flux in a DC magnetron sputtering reactor can be tailored to produce a coating in a hole or via in a dielectric layer.
  • a SIP film sputter deposited into a high-aspect ratio hole can have favorable upper sidewall coverage and tends not to develop overhangs.
  • an ICP generated plasma can increase metal ionization such that a film sputter deposited into such a hole may have good bottom and bottom corner coverage.
  • the advantages of both types of sputtering can be obtained in a reactor, such as the reactor 150, which combines selected aspects of both deposition techniques.
  • coil material may be sputtered to contribute to the deposition layer as well, if desired.
  • the reactor 150 and various processes for forming liner, barrier and other layers is described in detail in pending U.S. application Serial No. 10/202,778, filed July 25, 2002 (attorney docket No. 4044) and is incorporated by reference in its entirety.
  • the reactor 150 of the illustrated embodiment is a DC magnetron type reactor based on a modification of the Endura PVD Reactor available from Applied Materials, Inc. of Santa Clara, California.
  • This reactor includes a vacuum chamber 152, usually of metal and electrically grounded, sealed through a target isolator 154 to a PVD target 156 having at least a surface portion composed of the material to be sputter deposited on a wafer 158.
  • the target sputtering surface is depicted as being planar in the drawings, it is appreciated that the target sputtering surface or surfaces may have a variety of shapes including vaulted and cylindrical.
  • the wafer may be different sizes including 150, 200, 300 and 450 mm.
  • the illustrated reactor 150 is capable of self-ionized sputtering (SIP) in a long-throw mode. This SIP mode may be used in one embodiment in which coverage is directed primarily directed to the sidewalls of the hole. The SIP mode may be used to achieve good bottom coverage also.
  • SIP self-ionized sputtering
  • the reactor 150 also has an RF coil 151 which inductively couples RF energy into the interior of the reactor.
  • the RF energy provided by the coil 151 ionizes a precursor gas such as argon to maintain a plasma to resputter a deposition layer using ionized argon to thin bottom coverage, or to ionize sputtered deposition material to improve bottom coverage.
  • a precursor gas such as argon
  • the pressure is preferably maintained at a substantially lower pressure, such as 1 mTorr for deposition of tantalum nitride or 2.5 mTorr for deposition of tantalum, for example.
  • a pressure in the range of .1 to 40 mTorr may be appropriate, depending upon the application.
  • the ionization rate within the reactor 150 will be substantially lower than that of the typical high density IMP process.
  • This plasma may be used to resputter a deposited layer or to ionize sputtered deposition material or, or both.
  • the coil 151 itself may be sputtered to provide a protective coating on the wafer during resputtering of the material deposited onto the wafer for those areas in which thinning of the deposited material is not desired, or to otherwise provide additional deposition material.
  • the ICP plasma may be directed to thin or eliminate bottom coverage by etching or resputtering to reduce barrier layer resistance at the bottom of the hole.
  • the coil 151 may be sputtered to deposit protective material where thinning is not desired.
  • the pressure may be kept relatively low such that the plasma density is relatively low to reduce ionization of the sputtered deposition material from the coil. As a result, sputtered coil material can remain largely neutral so as to deposit primarily onto upper sidewalls to protect those portions from thinning.
  • deposition material may be ionized not only as a result of the plasma maintained by the RF coil 151 , but also by the sputtering of the target 156 itself.
  • the combined SIP and ICP ionization processes provide sufficient ionized material for good bottom and bottom corner coverage.
  • the lower ionization rate of the low pressure plasma provided by the RF coil 151 allows sufficient neutral sputtered material to remain un-ionized so as to be deposited on the upper sidewalls.
  • the combined sources of ionized deposition material can provide both good upper sidewall coverage as well as good bottom and bottom corner coverage as explained in greater detail below.
  • a wafer clamp 160 holds the wafer 158 on a pedestal electrode 162.
  • Resistive heaters, refrigerant channels, and thermal transfer gas cavity in the pedestal 162 can be provided to allow the temperature of the pedestal to be controlled to temperatures of less than -40 degrees C to thereby allow the wafer temperature to be similarly controlled.
  • the distance between the target 156 and the wafer 158 can be increased to operate in the long-throw mode.
  • the target-to-substrate spacing is typically greater than half the substrate diameter. In the illustrated embodiment it is preferably greater than 90% wafer diameter (e.g. 190 mm spacings for a 200 mm wafer and 290 mm for a 300 mm wafer), but spacings greater than 80% including greater than 100% and greater than 140% of the substrate diameter are believed appropriate also. For many applications, it is believed that a target to wafer spacing of 50 to 1000 mm will be appropriate.
  • a darkspace shield 164 and a chamber shield 166 separated by a second dielectric shield isolator 168 are held within the chamber 152 to protect the chamber wall 152 from the sputtered material.
  • both the darkspace shield 164 and the chamber shield 166 are grounded.
  • shields may be floating or biased to a nonground level.
  • the chamber shield 166 also acts as the anode grounding plane in opposition to the cathode target 156, thereby capacitively supporting a plasma.
  • the darkspace shield is permitted to float electrically, some electrons can deposit on the darkspace shield 164 so that a negative charge builds up there. It is believed that the negative potential could not only repel further electrons from being deposited, but also confine the electrons in the main plasma area, thus reducing the electron loss, sustaining low-pressure sputtering, and increasing the plasma density, if desired.
  • the coil 151 is carried on the shield 164 by a plurality of coil standoffs 180 which electrically insulate the coil 151 from the supporting shield 164.
  • the standoffs 180 have labyrinthine passageways which permit repeated deposition of conductive materials from the target 110 onto the coil standoffs 180 while preventing the formation of a complete conducting path of deposited material from the coil 151 to the shield 164 which could short the coil 151 to the shield 164 (which is typically at ground).
  • RF power is passed through the vacuum chamber walls and through the shield 164 to ends of the coil 151.
  • Vacuum feedthroughs (not shown) extend through the vacuum chamber wall to provide RF current from a generator preferably located outside the vacuum pressure chamber.
  • RF power is applied through the shield 164 to the coil 151 by feedthrough standoffs 182 (Fig. 5), which like the coil standoffs 180, have labyrinthine passageways to prevent formation of a path of deposited material from the coil 151 to the shield 164 which could short the coil 151 to the shield 164.
  • the plasma darkspace shield 164 is generally cylindrically-shaped.
  • the plasma chamber shield 166 is generally bowl-shaped and includes a generally cylindrically shaped, vertically oriented wall 190 to which the standoffs 180 and 182 are attached to insulatively support the coil 151.
  • Fig. 5 is a schematic representation of the electrical connections of the plasma generating apparatus of the illustrated embodiment.
  • the target 156 is preferably negatively biased by a variable DC power source 200 at a DC power of 1-40 kW, for example.
  • the source 200 negatively biases the target 156 to about -400 to -600VDC with respect to the chamber shield 166 to ignite and maintain the plasma.
  • a target power of between 1 and 5kW is typically used to ignite the plasma while a power of greater than 10kW is preferred for the SIP sputtering described here.
  • a target power of 24 kW may be used to deposit tantalum nitride by SIP sputtering and a target power of 20 kW may be used to deposit tantalum by SIP sputtering.
  • the target power may be reduced to 100-200 watts, for example to maintain plasma uniformity.
  • the target power may be maintained at a high level if target sputtering during ICP resputtering is desired, or may be turned off entirely, if desired.
  • the pedestal 162 and hence the wafer 158 may be left electrically floating, but a negative DC self-bias may nonetheless develop on it.
  • the pedestal 162 may be negatively biased by a source 202 at -30 v DC to negatively bias the substrate 158 to attract the ionized deposition material to the substrate.
  • Other embodiments may apply an RF bias to the pedestal 162 to further control the negative DC bias that develops on it.
  • the bias power supply 202 may be an RF power supply operating at 13.56MHz. It may be supplied with RF power in a range of 10 watts to 5 kW, for example, a more preferred range being 150 to 300 W for a 200 mm wafer in SIP deposition.
  • One end of the coil 151 is insulatively coupled through the shield 166 by a feedthrough standoff 182 to an RF source such as the output of an amplifier and matching network 204.
  • the input of the matching network 204 is coupled to an RF generator 206, which provides RF power at approximately 1 or 1.5 kW watts for ICP plasma generation for this embodiment.
  • RF generator 206 which provides RF power at approximately 1 or 1.5 kW watts for ICP plasma generation for this embodiment.
  • a power of 1.5 kW for tantalum nitride deposition and a power of 1 kW for tantalum deposition is preferred.
  • a preferred range is 50 watts to 10 kW.
  • the RF power to the coil may be turned off if desired. Alternatively, RF power may be supplied during SIP deposition if desired.
  • the other end of the coil 151 is also insulatively coupled through the shield 166 by a similar feedthrough standoff 182 to ground, preferably through a blocking capacitor 208 which may be a variable capacitor, to support a DC bias on the coil 151.
  • the DC bias on the coil 151 and hence the coil sputtering rate may be controlled through a DC power source 209 coupled to the coil 151 , as described in U.S. Patent No. 6,375,810.
  • Suitable DC power ranges for ICP plasma generation and coil sputtering include 50 watts to 10 kWatts. A preferred value is 500 watts during coil sputtering.
  • DC power to the coil 151 may be turned off during SIP deposition, if desired.
  • a computer-based controller 224 may be programmed to control the power levels, voltages, currents and frequencies of the various sources in accordance with the particular application.
  • the RF coil 151 may be positioned relatively low in the chamber so that material sputtered from the coil has a low angle of incidence when striking the wafer.
  • coil material may be deposited preferentially on the upper corners of the holes so as to protect those portions of the hole when the hole bottoms are being resputtered by the ICP plasma.
  • the coil it is preferred that the coil be positioned closer to the wafer than to the target when the primary function of the coil is to generate a plasma to resputter the wafer and to provide the protective coating during resputtering.
  • a coil to wafer spacing of 0 to 500 mm will be appropriate. It is appreciated however that the actual position will vary, depending upon the particular application.
  • the coil may be positioned closer to the target.
  • an RF coil may also be positioned to improve the uniformity of the deposited layer with sputtered coil material.
  • the coil may have a plurality of turns formed in a helix or spiral or may have as few turns as a single turn to reduce complexity and costs and facilitate cleaning.
  • a variety of coil support standoffs and feedthrough standoffs may be used to insulatively support the coils. Since sputtering, particularly at the high power levels associated with SSS, SIP and ICP, involves high voltages, dielectric isolators typically separate the differently biased parts. As a result, it is desired to protect such isolators from metal deposition.
  • the internal structure of the standoffs is preferably labyrinthine as described in greater detail in copending application Serial No. 09/515,880, filed February 29, 2000, entitled "COIL AND COIL SUPPORT FOR GENERATING A PLASMA" and assigned to the assignee of the present application.
  • the coil 151 and those portions of the standoffs directly exposed to the plasma are preferably made of the same material which is being deposited.
  • the outer portions of the standoffs are preferably made of tantalum as well.
  • exposed surfaces of the metal may be treated by bead blasting which will reduce shedding of particles from the deposited material.
  • the coil and target may be made from a variety of deposition materials including copper, aluminum, and tungsten.
  • the labyrinth should be dimensioned to inhibit formation of a complete conducting path from the coil to the shield. Such a conducting path could form as conductive deposition material is deposited onto the coil and standoffs. It should be recognized that other dimensions, shapes and numbers of passageways of the labyrinth are possible, depending upon the particular application. Factors affecting the design of the labyrinth include the type of material being deposited and the number of depositions desired before the standoffs need to be cleaned or replaced.
  • a suitable feedthrough standoff may be constructed in a similar manner except that RF power would be applied to a bolt or other conductive member extending through the standoff.
  • the coil 151 may have overlapping but spaced ends.
  • the feedthrough standoffs 182 for each end may be stacked in a direction parallel to the plasma chamber central axis between the vacuum chamber target 156 and the substrate holder 162, as shown in FIG. 4.
  • the RF path from one end of the coil to the other end of the coil can similarly overlap and thus avoid a gap over the wafer. It is believed that such an overlapping arrangement can improve uniformity of plasma generation, ionization and deposition as described in copending application Serial No. 09/039,695, filed March 16, 1998 and assigned to the assignee of the present application.
  • the support standoffs 180 may be distributed around the remainder of the coil to provide suitable support.
  • the coils each have three hub members 504 distributed at 90 degree separations on the outer face of each coil. It should be appreciated that the number and spacing of the standoffs may be varied depending upon the particular application.
  • the coil 151 of the illustrated embodiments is each made of 2 by 1/4 inch heavy duty bead blasted tantalum or copper ribbon formed into a single turn coil.
  • other highly conductive materials and shapes may be utilized.
  • the thickness of the coil may be reduced to 1/16 inch and the width increased to 2 inches.
  • hollow tubing may be utilized, particularly if water cooling is desired.
  • the appropriate RF generators and matching circuits are components well known to those skilled in the art.
  • an RF generator such as the ENI Genesis series which has the capability to frequency hunt for the best frequency match with the matching circuit and antenna is suitable.
  • the frequency of the generator for generating the RF power to the coil is preferably 2 MHz but it is anticipated that the range can vary at other A.C. frequencies such as, for example, 1 MHz to 200 MHz and non-RF frequencies.
  • These components may be controlled by the programmable controller 224 as well.
  • the lower cylindrical portion 296 of the chamber shield 166 continues downwardly to well in back of the top of the pedestal 162 supporting the wafer 158.
  • the chamber shield 166 then continues radially inwardly in a bowl portion 302 and vertically upwardly in an innermost cylindrical portion 151 to approximately the elevation of the wafer 158 but spaced radially outside of the pedestal 162.
  • the shields 164, 166 are typically composed of stainless steel, and their inner sides may be bead blasted or otherwise roughened to promote adhesion of the material sputter deposited on them. At some point during prolonged sputtering, however, the deposited material builds up to a thickness that it is more likely to flake off, producing deleterious particles. Before this point is reached, the shields should be cleaned or more likely replaced with fresh shields. However, the more expensive isolators 154, 168 do not need to be replaced in most maintenance cycles. Furthermore, the maintenance cycle is determined by flaking of the shields, not by electrical shorting of the isolators.
  • a gas source 314 supplies a sputtering working gas, typically the chemically inactive noble gas argon, to the chamber 152 through a mass flow controller 316.
  • the working gas can be admitted to the top of the chamber or, as illustrated, at its bottom, either with one or more inlet pipes penetrating apertures through the bottom of the shield chamber shield 166 or through a gap 318 between the chamber shield 166, the wafer clamp 160, and the pedestal 162.
  • a vacuum pump system 320 connected to the chamber 152 through a wide pumping port 322 maintains the chamber at a low pressure.
  • the base pressure can be held to about 10 "7 Torr or even lower, the pressure of the working gas is typically maintained at between about 1 and 1000 milliTorr in conventional sputtering and to below about 5 milliTorr in SIP sputtering.
  • the computer-based controller 224 controls the reactor including the DC target power supply 200, the bias power supply 202, and the mass flow controller 316.
  • a magnetron 330 is positioned in back of the target 156. It has opposed magnets 332, 334 connected and supported by a magnetic yoke 336. The magnets create a magnetic field adjacent the magnetron 330 within the chamber 152. The magnetic field traps electrons and, for charge neutrality, the ion density also increases to form a high-density plasma region 338.
  • the magnetron 330 is usually rotated about the center 340 of the target 156 by a motor-driven shaft 342 to achieve full coverage in sputtering of the target 156.
  • the power density delivered to the area adjacent the magnetron 330 can be made high. This can be achieved, as described by Fu and Chiang in the above cited patents, by increasing the power level delivered from the DC power supply 200 and by reducing the area of magnetron 330, for example, in the shape of a triangle or a racetrack.
  • the inner magnetic pole represented by the inner magnet 332 and magnetic pole face should have no significant apertures and be surrounded by a continuous outer magnetic pole represented by the outer magnets 334 and pole face. Furthermore, to guide the ionized sputter particles to the wafer 158, the outer pole should produce a much higher magnetic flux than the inner pole. The extending magnetic field lines trap electrons and thus extend the plasma closer to the wafer 158. The ratio of magnetic fluxes should be at least 150% and preferably greater than 200%. Two embodiments of Fu's triangular magnetron have 25 outer magnets and 6 or 10 inner magnets of the same strength but opposite polarity.
  • magnetrons may be used with a variety of target shapes to generate self ionized plasmas.
  • the magnets may have shapes other than triangular including circular and other shapes.
  • the DC voltage difference between the target 156 and the chamber shield 166 ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target 156.
  • the ions strike the target 156 at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target 156.
  • Some of the target particles strike the wafer 158 and are thereby deposited on it, thereby forming a film of the target material.
  • nitrogen is additionally admitted into the chamber from a source 343, and it reacts with the sputtered metallic atoms to form a metallic nitride on the wafer 158.
  • FIGS. 6-9b show sequential cross-sectional views of the formation of liner layers in accordance with a one aspect of the present invention.
  • an interiayer dielectric 345 e.g. silicon dioxide
  • a first metal layer e.g., a first copper layer 347a
  • a via 349 then is etched in the interiayer dielectric 345 to expose the first copper layer 347a.
  • the first metal layer may be deposited using CVD, PVD, electroplating or other such well-known metal deposition techniques, and it is connected, via contacts, through a dielectric layer, to devices formed in the underlying semiconductor wafer.
  • any copper oxide layer 347a' and any processing residue within the via 349 may be removed.
  • a barrier layer 351 may be deposited (e.g., within the sputtering chamber 152 of FIG. 4) over the interiayer dielectric 345 and over the exposed first copper layer 347a prior to removing the copper oxide layer 347a'.
  • the barrier layer 351 preferably comprising tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride prevents subsequently deposited copper layers from incorporating in and degrading the interiayer dielectric 345 (as previously described).
  • a tantalum target 156 is employed.
  • both argon and nitrogen gas are flowed into the sputtering chamber 152 through the gas inlet 360 (multiple inlets, one for each gas, may be used), while a power signal is applied to the target 156 via the DC power supply 200.
  • a power signal may also be applied to the coil 151 via the first RF power supply 206.
  • nitrogen may react with the tantalum target 156 to form a nitride film on the tantalum target 156 so that tantalum nitride is sputtered therefrom.
  • non-nitrided tantalum atoms are also sputtered from the target, which atoms can combine with nitrogen to form tantalum nitride in flight or on a wafer (not shown) supported by the pedestal 162.
  • a throttle valve operatively coupled to the exhaust outlet 362 is placed in a mid-position in order to maintain the deposition chamber 152 at a desired low vacuum level of about 1x10 "® torr prior to introduction of the process gas(es) into the chamber.
  • a mixture of argon and nitrogen gas is flowed into the sputtering chamber 152 via a gas inlet 360.
  • DC power is applied to the tantalum target 156 via the DC power supply 200 (while the gas mixture continues to flow into the sputtering chamber 152 via the gas inlet 360 and is pumped therefrom via the pump 37).
  • the DC power applied to the target 156 causes the argon/nitrogen gas mixture to form an SIP plasma and to generate argon and nitrogen ions which are attracted to, and strike the target 156 causing target material (e.g., tantalum and tantalum nitride) to be ejected therefrom.
  • target material e.g., tantalum and tantalum nitride
  • the ejected target material travels to and deposits on the wafer 158 supported by the pedestal 162.
  • the plasma created by the unbalanced magnetron ionizes a portion of the sputtered tantalum and tantalum nitride.
  • a negative bias can be created between the substrate support pedestal 162 and the plasma.
  • the negative bias between the substrate support pedestal 162 and the plasma causes tantalum ions, tantalum nitride ions and argon ions to accelerate toward the pedestal 162 and any wafer supported thereon. Accordingly, both neutral and ionized tantalum nitride may be deposited on the wafer, providing good sidewall and upper sidewall coverage in accordance with SIP sputtering.
  • the wafer may be sputter-etched by the argon ions at the same time the tantalum nitride material from the target 156 deposits on the wafer (i.e., simultaneous deposition/sputter- etching).
  • the portion of the barrier layer 351 at the bottom of the via 349, and the copper oxide layer 347a' (and any processing residue) thereunder may be sputter-etched or resputtered via an argon plasma as shown in Fig. 7, if thinning or elimination of the bottom is desired.
  • the argon plasma is preferably generated in this step primarily by applying RF power to the ICP coil.
  • the power applied to the target 156 is preferably either removed or is reduced to a low level (e.g., 100 or 200 W) so as to inhibit or prevent significant deposition from the target 156.
  • a low target power level, rather than no target power, can provide a more uniform plasma and is presently preferred.
  • ICP argon ions are accelerated toward the barrier layer 351 via an electric field (e.g., the RF signal applied to the substrate support pedestal 162 via the second RF power supply 41 of FIG. 4 which causes a negative self bias to form on the pedestal), strike the barrier layer 351 , and, due to momentum transfer, sputter the barrier layer material from the base of the via aperture and redistribute it along the portion of the barrier layer 351 that coats the sidewalls of the via 349.
  • the argon ions are attracted to the substrate in a direction substantially perpendicular thereto. As a result, little sputtering of the via sidewall, but substantial sputtering of the via base, occurs.
  • the bias applied to the pedestal and the wafer may be 400 watts, for example.
  • the ICP coil 151 may be formed of liner material such as tantalum in the same manner as the target 156 and sputtered to deposit tantalum nitride onto the wafer while the via bottoms are resputtered.
  • the ionization rate of the deposition material sputtered from the coil 151 is relatively low.
  • the sputtered material deposited onto the wafer is primarily neutral material.
  • the coil 151 is placed relatively low in the chamber, surrounding and adjacent to the wafer.
  • the trajectory of the material sputtered from the coil 151 tends to have a relatively small angle of incidence.
  • the sputtered material from the coil 151 tends to deposit in a layer 364 on the upper surface of the wafer and around the openings of the holes or vias in the wafer rather than deep into the wafer holes.
  • This deposited material from the coil 151 may be used to provide a degree of protection from resputtering so that the barrier layer is thinned by resputtering primarily at the bottom of the holes rather than on the sidewalls and around the hole openings where thinning of the barrier layer may not be desired.
  • the argon ions strike the copper oxide layer 347a', and the oxide layer is sputtered to redistribute the copper oxide layer material from the via base, some or all of the sputtered material being deposited along the portion of the barrier layer 351 that coats the sidewalls of the via 349. Copper atoms 347a", as well, coat the barrier layer 351 and 364 disposed on the sidewalls of the via 349.
  • the copper atoms 347a" are substantially immobile within the barrier layer 351 and are inhibited from reaching the interiayer dielectric 345.
  • the copper atoms 347a" which are deposited onto the sidewall therefore, generally do not generate via-to-via leakage currents as they would were they redistributed onto an uncoated sidewall.
  • a second liner layer 371 of a second material such as tantalum may be deposited (Fig. 8) on the previous barrier layer 351 in the same chamber 152 or a similar chamber having both an SIP and ICP capabilities.
  • a tantalum liner layer provides good adhesion between the underlying tantalum nitride barrier layer and a subsequently deposited metal interconnect layer of a conductor such as copper.
  • the second liner layer 371 may be deposited in the same manner as the first liner layer 351.
  • the tantalum liner 371 may be deposited in a first SIP step in which the plasma is generated primarily by the target magnetron 330. However, nitrogen is not admitted so that tantalum rather than tantalum nitride is deposited. In accordance with SIP sputtering, good sidewall and upper sidewall coverage may be obtained. RF power to the ICP coil 151 may be reduced or eliminated, if desired.
  • the portion of the liner layer 371 at the bottom of the via 349 (and any processing residue) thereunder may be sputter-etched or resputtered via an argon plasma in the same manner as the bottom of the liner layer 351 , as shown in Fig. 9a, if thinning or elimination of the bottom is desired.
  • the argon plasma is preferably generated in this step primarily by applying RF power to the ICP coil.
  • the power applied to the target 156 is preferably either removed or is reduced to a low level (e.g., 500 W) so as to inhibit or prevent significant deposition from the target 156 during thinning or elimination of the bottom coverage of the second liner layer 371.
  • the coil 151 is preferably sputtered to deposit liner material 374 while the argon plasma resputters the layer bottom to protect the liner sidewalls and upper portions from being thinned substantially during the bottom portion resputtering.
  • SIP deposition of target material on the sidewalls of the vias occurs primarily in one step and ICP resputtering of the via bottoms and ICP deposition of coil 151 material occurs primarily in a subsequently step. It is appreciated that deposition of both target material and coil material on the sidewalls of the via 349 can occur simultaneously, if desired. It is further appreciated that ICP sputter-etching of the deposited material at the bottom of the via 349 can occur simultaneously with the deposition of target and coil material on the sidewalls, if desired. Simultaneous deposition/sputter-etching may be performed with the chamber 152 of FIG.
  • the plasma can sputter a wafer with a low relative bias on the wafer (less than that needed to sustain the plasma).
  • the ratio of the RF power applied to the wire coil 151 (“RF coil power") as compared to the DC power applied to the target 156 ('DC target power") affects the relationship between sputter-etching and deposition. For instance, the higher the RF:DC power ratio the more sputter-etching will occur due to increased ionization and subsequent increased ion bombardment flux to the wafer.
  • Increasing the wafer bias e.g., increasing the RF power supplied to the support pedestal 162 will increase the energy of the incoming ions which will increase the sputtering yield and the etch rate.
  • increasing the voltage level of the RF signal applied to the pedestal 162 increases the energy of the ions incident on the wafer, while increasing the duty cycle of the RF signal applied to the pedestal 162 increases the number of incident ions.
  • both the voltage level and the duty cycle of the wafer bias can be adjusted to control sputtering rate.
  • keeping the DC target power low will decrease the amount of barrier material available for deposition.
  • a DC target power of zero will result in sputter-etching only.
  • a low DC target power coupled with a high RF coil power and wafer bias can result in simultaneous via sidewall deposition and via bottom sputtering. Accordingly, the process may be tailored for the material and geometries in question.
  • a DC target power of 500 W to 1 kW, at an RF coil power of 2 to 3kW or greater, with a wafer bias of 250 W to 4OO W or greater applied continuously (e.g., 100% duty cycle) can result in barrier deposition on the wafer sidewalls and removal of material from the via bottom.
  • a 2 kW RF coil power level on the coil 151 and a 250 W RF wafer power level with 100% duty cycle on the pedestal 162, for example may be used for simultaneous deposition/sputter-etching. It may be desirable to initially (e.g., for several seconds or more depending on the particular geometries/materials in question) apply no wafer bias during simultaneous deposition/sputter-etching to allow sufficient via sidewall coverage to prevent contamination of the sidewalls by material sputter-etched from the via bottom.
  • initially applying no wafer bias during simultaneous deposition/sputter-etching of the via 349 can facilitate formation of an initial barrier layer on the sidewalls of the interiayer dielectric 345 that inhibits sputtered copper atoms from contaminating the interiayer dielectric 345 during the remainder of the deposition/sputter-etching operation.
  • deposition/sputter-etching may be performed "sequentially" within the same chamber or by depositing the barrier layer 351 within a first processing chamber and by sputter-etching the barrier layer 351 and copper oxide layer 347a' within a separate, second processing chamber (e.g., a sputter-etching chamber such as Applied Materials' Preclean II chamber).
  • a second metal layer 347b is deposited (Fig. 9b) to form the copper interconnect 348.
  • the second copper layer 347b may deposited either as a coating or as a copper plug 347b' as shown in FIG. 9b over the second liner layer 371 and over the portion of the first copper layer 347a exposed at the base of each via.
  • the copper layer 347b may include a copper seed layer. Because the first and second copper layers 347a, 347b are in direct contact, rather than in contact through the barrier layer 351 or the second liner layer 371 , the resistance of the copper interconnect 348 can be lower as can via-to-via leakage currents as well. However, it is appreciated that in some applications, it may be desired to leave a coating of the liner layer or the barrier layer or both at the bottom of the via.
  • the interconnect layer may be deposited in a sputter chamber having a target of the different conductor metal.
  • the sputter chamber may be an SIP type or an ICP type.
  • at present deposition of a copper seed layer is preferred in a chamber of the type described below in connection with FIG. 10.
  • the metal interconnect may be deposited by other methods in other types of chambers and apparatus including CVD and electrochemical plating.
  • a copper seed layer may be deposited by another plasma sputtering reactor 410 as illustrated in the schematic cross-section view of FIG. 10.
  • the reactor 410 and various processes for forming seed and other layers is described in copending application Serial No. 09/993,543, filed November 14, 2001 (attorney docket No. 6265) which is incorporated herein by reference in its entirety.
  • a vacuum chamber 412 includes generally cylindrical sidewalls 414, which are electrically grounded. Typically, unillustrated grounded replaceable shields are located inside the sidewalls 414 to protect them from being sputter coated, but they act as chamber sidewalls except for holding a vacuum.
  • a sputtering target 416 composed of the metal to be sputtered is sealed to the chamber 412 through an electrical isolator 418.
  • a pedestal electrode 422 supports a wafer 424 to be sputter coated in parallel opposition to the target 416.
  • a processing space is defined between the target 416 and the wafer 424 inside of the shields.
  • a sputtering working gas preferably argon
  • argon is metered into the chamber from a gas supply 426 through a mass flow controller 428.
  • An unillustrated vacuum pumping system maintains the interior of the chamber 412 at a very low base pressure of typically 10 "8 Torr or less.
  • the argon pressure is supplied in an amount producing a chamber pressure of approximately 5 milliTorr, but as will be explained later the pressure is thereafter decreased.
  • a DC power supply 434 negatively biases the target 416 to approximately -600VDC causing the argon working gas to be excited into a plasma containing electrons and positive argon ions.
  • the positive argon ions are attracted to the negatively biased target 416 and sputter metal atoms from the target.
  • the invention is particularly useful with SIP sputtering in which a small nested magnetron 436 is supported on an unillustrated back plate behind the target 416.
  • the chamber 412 and target 416 are generally circularly symmetric about a central axis 438.
  • the SIP magnetron 436 includes an inner magnet pole 440 of a first vertical magnetic polarity and a surrounding outer magnet pole 442 of the opposed second vertical magnetic polarity. Both poles are supported by and magnetically coupled through a magnetic yoke 444.
  • the yoke 444 is fixed to a rotation arm 446 supported on a rotation shaft 448 extending along the central axis 4438.
  • a motor 450 connected to the shaft 448 causes the magnetron 436 to rotate about the central axis 438.
  • the outer pole 442 has a total magnetic flux integrated over its area that is larger than that produced by the inner pole 440, preferably having a ratio of the magnetic intensities of at least 150%.
  • the opposed magnetic poles 440, 442 create a magnetic field inside the chamber 412 that is generally semi-toroidal with strong components parallel and close to the face of the target 416 to create a high-density plasma there to thereby increase the sputtering rate and increase the ionization fraction of the sputtered metal atoms. Because the outer pole 442 is magnetically stronger than the inner pole 440, a fraction of the magnetic field from the outer pole 442 projects far towards the pedestal 422 before it loops back to behind the outer pole 442 to complete the magnetic circuit.
  • An RF power supply 454 for example, having a frequency of 13.56MHz is connected to the pedestal electrode 422 to create a negative self-bias on the wafer 424.
  • the bias attracts the positively charged metal atoms across the sheath of the adjacent plasma, thereby coating the sides and bottoms of high aspect- ratio holes in the wafer, such as, inter-level vias.
  • the magnetron In SIP sputtering, the magnetron is small and has a high magnetic strength and a high amount of DC power is applied to the target so that the plasma density rises to above 10 10 cm "3 near the target 416. In the presence of this plasma density, a large number of sputtered atoms are ionized into positively charged metal ions. The metal ion density is high enough that a large number of them are attracted back to the target to sputter yet further metal ions. As a result, the metal ions can at least partially replace the argon ions as the effective working species in the sputtering process. That is, the argon pressure can be reduced.
  • the reduced pressure has the advantage of reducing scattering and deionization of the metal ions.
  • SSS sustained self-sputtering
  • aluminum or tungsten sputtering SSS is not possible, but the argon pressure can be substantially reduced from the pressures used in conventional sputtering, for example, to less than 1 milliTorr.
  • an auxiliary array 460 of permanent magnets 462 is positioned around the chamber sidewalls 414 and is generally positioned in the half of the processing space towards the wafer 424.
  • the auxiliary magnets 462 have the same first vertical magnetic polarity as the outer pole 442 of the nested magnetron 436 so as to draw down the unbalanced portion of the magnetic field from the outer pole 442.
  • the auxiliary magnet array is generally symmetrically disposed about the central axis 438 to produce a circularly symmetric magnetic field.
  • the nested magnetron 436 has a magnetic field distribution is asymmetrically disposed about the central axis 438 although, when it is averaged over the rotation time, it becomes symmetric.
  • the simplest though less preferred form has a button center pole 440 surround by an circularly annular outer pole 442 such that its field is symmetric about an axis displaced from the chamber axis 438 and the nested magnetron axis is rotated about the chamber axis 438.
  • the preferred nested magnetron has a triangular shape, illustrated in the bottom plan view of FIG. 11 , with an apex near the central axis 438 and a base near the periphery of the target 416. This shape is particularly advantageous because the time average of the magnetic field is more uniform than for a circular nested magnetron.
  • a semi-toroidal field B M provides a strong horizontal component close to and parallel to the face of the target 416, thereby increasing the density of the plasma, the rate of sputtering, and the ionization fraction of sputtered particles.
  • An auxiliary field B A ⁇ , B ⁇ is the sum of the field from the auxiliary magnet array 460 and from the unbalanced portion of the field of the nested magnetron 436.
  • the component B A ⁇ from the unbalanced portion of the field of the nested magnetron 436 predominates, and it does not extend far towards the wafer 424.
  • the auxiliary magnet 462 is strongly coupled to the outer magnet pole 442, resulting in a magnetic field component B A2 that projects far towards the wafer 424.
  • the magnetic field component is an combination of the two components B A ⁇ , B A2 .
  • This structure effects the result that a strong vertical magnetic field is produced near to and along a substantial length of the chamber sidewall 414 in a region beneath the nested magnetron 436 sweeping about it because of the alignment of the magnetic polarities of the auxiliary magnets 442 and the strong outer magnetic poles 442.
  • a strong vertical magnetic field on the exterior side of the chamber 412 adjacent the area of the target 416 being most strongly sputtered.
  • This projecting field is effective for both extending the region of the plasma and for guiding the ionized particles to the wafer 424.
  • the auxiliary magnet array 460 may be implemented by the use of two semi-circular magnet carriers 470, one of which is illustrated orthographically in FIG. 12.
  • Each carrier 470 includes four recesses 472 facing its interior and sized to receive a respective magnet assembly 474 including one magnet 462.
  • the magnet assembly 474 includes an arc-shaped upper clamp member 476 and a lower clamp member 478, which capture the cylindrically shaped magnet 462 into recesses when two screws 480 tighten the two clamp members 476, 478 together.
  • the carriers 470 and clamp members 476, 478 may be formed of non-magnetic material such as aluminum.
  • the lower clamp member 478 has a length to fit into the recess 472 but the upper clamp member 476 has end portions extending beyond the recess 472 and through which are drilled two through holes 482.
  • Two screws 484 pass through respective through holes to allow the screws 484 to be fixed in tapped holes 486 in the magnet carrier 470, thereby fixing the magnet 462 in position on the magnet carrier 470.
  • Two so assembled semi-circular magnet carrier 470 are placed in a ring around the chamber wall 414 and fixed to it by conventional fastening means. This structure places the magnets 462 directly adjacent the exterior of the chamber wall 414.
  • the solenoidal magnetic field created inside the electromagnetic coil of Wei Wang is substantially more uniform across the diameter of the reactor chamber than is the peripheral dipole magnetic field created by an annular array of permanent magnets. However, it is possible to create a similarly shaped dipole field by replacing the permanent magnets 462 with, as illustrated in the cross-sectional view of FIG.
  • an annular array of electromagnetic coils 490 arranged around the periphery of the chamber wall.
  • the coils 490 are typically wrapped as helices about respective axes parallel to the central axis 438 and are electrically powered to produce nearly identical magnetic dipole fields inside the chamber.
  • Such a design has the advantage of allowing the quick adjustment of the auxiliary magnetic field strength and even the polarity of the field.
  • This invention has been applied to SIP sputtering of copper. While a conventional SIP reactor sputters a copper film having a non-uniformity of 9% determined by sheet resistance measurements, it is believed that the auxiliary magnetron can be optimized to produce a non-uniformity of only 1% in some embodiments. The improvement in uniformity may be accompanied by a reduced deposition rate in some applications, for the deposition of thin copper seed layers in deep holes, which may be desirable for improved process control in some applications. [0098] Although the invention has been described for use in an SIP sputter reactor, the auxiliary permanent magnet array can be advantageously applied to other target and power configurations such as the annularly vaulted target of the SIP + reactor of U.S.
  • Patent 6,251 ,242 the hollow cathode target of U.S. Patent 6,179,973 or "Ionized Physical-vapor deposition Using a Hollow-cathode Magnetron Source for Advanced Metallization" by Klawuhn et al, J. Vac. Sci Technology, Jul/Aug 2000, the inductively coupled IMP reactor of U.S. Patent 6,045,547 or a self ion sputtering (SIS) system which controls ion flux to a substrate using an ion reflector as described, for example, in "Cu Dual Damascene Process for 0.13 micrometer Technology Generation using Self Ion Sputtering (SIS) with Ion Reflector" by Wada et al., IEEE, 2000.
  • SIS self ion sputtering
  • auxiliary magnets may be parallel or anti-parallel to the magnetic polarity of the outer pole of the top magnetron.
  • Other materials may be sputtered including Al, Ta, Ti, Co, W etc. and the nitrides of several of these which are refractory metals.
  • the auxiliary magnet array thus provides additional control of the magnetic field useful in magnetron sputtering. However, to achieve deeper hole coating with a partially neutral flux, it is desirable to increase the distance between the target 416 and the wafer 424, that is, to operate in the long-throw mode. As discussed above in connection with the chamber of Fig.
  • the target- to-substrate spacing is typically greater than half the substrate diameter.
  • it is preferably greater than 140% wafer diameter (e.g. 290 mm spacing) for a 200 mm wafer and greater than 130% (e.g. 400 mm spacing) for a 300 mm wafer, but spacings greater than 80% including greater than 90% and greater than 100% of the substrate diameter are believed appropriate also.
  • a target to wafer spacing of 50 to 1000 mm will be appropriate. Long throw in conventional sputtering reduces the sputtering deposition rate, but ionized sputter particles do not suffer such a large decrease.
  • a seed copper layer 492 is deposited by the chamber of FIG. 10 in the via hole 494 over the liner layers formed in the chamber of FIG. 4, which may include one or more barrier and liner layers such as the aforementioned TaN barrier 351 , 364 and Ta liner layers 371 , 374 under conditions promoting SIP and ICP.
  • the SIP copper layer 492 may be deposited, for example, to a blanket thickness of 50 to 300 nm or more preferably of 80 to 200nm.
  • the SIP copper seed layer 492 preferably has a thickness in the range of 2 to 20nm on the via sidewalls, more preferably 7 to 15nm. In view of the narrow holes, the a sidewall thickness in excess of 50nm may not be optimal for some applications.
  • the quality of the film can in some applications be improved by decreasing the pedestal temperature to less than 0 degrees C and preferably to less than -40 degrees C. In such applications quick SIP deposition is advantageous.
  • the sputtering chamber 410 is configured for deposition of copper layers
  • a copper target 416 is employed.
  • a throttle valve operatively coupled to the chamber exhaust outlet is placed in a mid-position in order to maintain the deposition chamber 410 at a desired low vacuum level of about 1x10 ⁇ 8 torr prior to introduction of the process gas(es) into the chamber.
  • argon gas is flowed into the sputtering chamber 410 via a gas inlet 428.
  • a very low pressure is preferred, such as 0 - 2 mTorr.
  • a pressure of 0.2 mTorr is suitable.
  • DC power is applied to the copper target 416 via the DC power supply 434 (while the gas mixture continues to flow into the sputtering chamber 410 via the gas inlet 360 and is pumped therefrom via a suitable pump).
  • the power applied to the target 416 may range for a copper target in a range of 20 - 60 kWatts for a 200 mm wafer.
  • the power supply 434 can apply 38 kWatts to the copper target 416 at a voltage of -600 VDC. For larger wafers such as 300 mm wafers, it is anticipated that larger values such as 56 kWatts may be appropriate. Other values may also be used, depending upon the particular application.
  • the DC power applied to the target 416 causes the argon to form an SIP plasma and to generate argon ions which are attracted to, and strike the target 416 causing target material (e.g., copper) to be ejected therefrom.
  • target material e.g., copper
  • the ejected target material travels to and deposits on the wafer 424 supported by the pedestal 422.
  • the plasma created by the unbalanced magnetron ionizes a portion of the sputtered copper.
  • a negative bias can be created between the substrate support pedestal 422 and the plasma.
  • the power applied to the pedestal 422 may range for copper seed deposition in a range of 0 - 1200 watts.
  • the RF power supply 454 can apply 300 watts to the pedestal 422 for a 200 mm wafer.
  • the negative bias between the substrate support pedestal 422 and the plasma causes copper ions and argon ions to accelerate toward the pedestal 422 and any wafer supported thereon. Accordingly, both neutral and ionized copper may be deposited on the wafer, providing good bottom, sidewall and upper sidewall coverage in accordance with SIP sputtering.
  • the wafer may be sputter- etched by the argon ions at the same time the copper material from the target 416 deposits on the wafer (i.e., simultaneous deposition/sputter-etching).
  • the portion of the seed layer 492 at the bottom 496 of the via 494 may be sputter-etched or resputtered via an argon plasma as shown in Fig. 14B, if redistribution of the bottom is desired.
  • the bottom 496 may be redistributed to increase coverage thickness of the bottom corner areas 498 of the copper seed layer as shown in FIG. 14B. In many applications, it is preferred that the copper seed layer bottom 496 not be completely removed to provide adequate seed layer coverage throughout the via.
  • the argon plasma is preferably generated in this resputtering step as SIP plasma by applying power to the target and to the pedestal.
  • SIP argon ions are accelerated toward the seed layer 492 via an electric field (e.g., the RF signal applied to the substrate support pedestal 422 via the second RF power supply 454 of FIG. 10 which causes a negative self bias to form on the pedestal), strike the seed layer 492, and, due to momentum transfer, sputter the seed layer material from the base of the via aperture and redistribute it along the portion 498 of the seed layer 492 that coats the bottom corners of the via 349.
  • an electric field e.g., the RF signal applied to the substrate support pedestal 422 via the second RF power supply 454 of FIG. 10 which causes a negative self bias to form on the pedestal
  • the power applied to the pedestal 422 may be increased to a higher value, such as 600 - 1200 watts , or 900 watts, for example, to facilitate redistribution of the copper seed layer bottom.
  • the pedestal power is raised from a level below 600 watts (e.g. 300 watts) to a level greater than 600 watts (e.g.
  • the power applied to the target 416 may be reduced to a lower value, such as below 30 kWatts or 28 kWatts, for example, so as to inhibit deposition from the target 416 to facilitate redistribution of the copper seed layer bottom.
  • a low target power level rather than no target power, can provide a more uniform plasma and is presently preferred in those embodiments in which target power is reduced for seed layer bottom redistribution.
  • the target power is lowered from a level above 30000 (e.g. 38 kwatts) to a level lower than 30000 watts, (e.g. 28 kWatts) to enhance resputtering.
  • the resputtering of the copper seed layer bottom may be performed simultaneously throughout the copper seed layer deposition such that the target and pedestal power levels may be maintained relatively constant (such as 38 kWatts and 300 watts, respectively) during the seed layer deposition.
  • target power reductions may be alternated or combined with pedestal power increases to facilitate seed layer bottom redistribution.
  • the particular values of the resputtering process parameters may vary depending upon the particular application. Copending or issued applications 08/768,058; 09/126,890; 09/449,202; 09/846,581 ; 09/490,026; and 09/704,161, describe resputtering processes and are incorporated herein by reference in their entireties.
  • the SIP copper seed layer 492 has good bottom and sidewall coverage and enhanced bottom corner coverage. After the copper seed layer 492 is deposited, the hole is filled with a copper layer 18, as in FIG. 1 , preferably by electrochemical plating using the seed layer 492 as one of the electroplating electrodes. Alternatively, the smooth structure of the SIP copper seed layer 492 also promotes reflow or higher-temperature deposition of copper by standard sputtering or physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • the chambers of FIGS. 4 and 10 utilize both ionized and neutral atomic flux.
  • the distribution between ionized and neutral atomic flux in a DC magnetron sputtering reactor can be tailored to produce an advantageous layer in a hole in a dielectric layer.
  • Such a layer can be used either by itself or in combination with a copper seed layer deposited by chemical vapor deposition (CVD) over a sputtered copper nucleation layer.
  • a copper liner layer is particularly useful as a thin seed layer for electroplated copper.
  • the DC magnetron sputtering reactors of the prior art have been directed to either conventional, working gas sputtering or to sustained self-sputtering.
  • the two approaches emphasize different types of sputtering.
  • the reactor for the copper liner combine various aspects of the prior art to control the distribution between ionized copper atoms and neutrals.
  • An example of such a reactor 550 is illustrated in the schematic cross-sectional view of FIG. 15.
  • the reactors of FIGS. 4, 10 and 13 may utilize these aspects of the reactor of FIG. 15 which is also based on a modification of the Endura PVD Reactor available from Applied Materials, Inc. of Santa Clara, California.
  • the reactor 550 includes a vacuum chamber 552, usually of metal and electrically grounded, sealed through a target isolator 554 to a PVD target 556 having at least a surface portion composed of the material, in this case copper or a copper alloy, to be sputter deposited on a wafer 558.
  • the alloying element is typically present to less than 5 wt %, and essentially pure copper may be used if adequate barriers are otherwise formed.
  • a wafer clamp 560 holds the wafer 558 on a pedestal electrode 562. Unillustrated resistive heaters, refrigerant channels, and thermal transfer gas cavity in the pedestal 562 allow the temperature of the pedestal to be controlled to temperatures of less than -40 degrees C to thereby allow the wafer temperature to be similarly controlled.
  • a floating shield 564 and a grounded shield 566 separated by a second dielectric shield isolator 568 are held within the chamber 552 to protect the chamber wall 552 from the sputtered material.
  • the grounded shield 566 also acts as the anode grounding plane in opposition to the cathode target 556, thereby capacitively supporting a plasma.
  • Some electrons deposit on the floating shield 564 so that a negative charge builds up there.
  • the negative potential not only repels further electrons from being deposited, but also confines the electrons in the main plasma area, thus reducing the electron loss, sustaining low-pressure sputtering, and increasing the plasma density.
  • the target 556 includes an aluminum or titanium backing plate 570 to which is soldered or diffusion bonded a copper target portion 572.
  • a flange 573 of the backing plate 570 rests on and is vacuum sealed through a polymeric target O-ring 574 to the target isolator 554, which is preferably composed of a ceramic such as alumina.
  • the target isolator 554 rests on and is vacuum sealed through an adaptor O-ring 575 to the chamber 552, which in fact may be an aluminum adaptor sealed to the main chamber body.
  • a metal clamp ring 576 has on its inner radial side an upwardly extending annular rim 577.
  • Unillustrated bolts fix the metal clamp ring 576 to an inwardly extending ledge 578 of the chamber 552 and capture a flange 579 of the grounded shield 566. Thereby, the grounded shield 566 is mechanically and electrically connected to the grounded chamber 552.
  • the shield isolator 568 freely rests on the clamp ring 576 and may be machined from a ceramic material such as alumina. It is compact but has a relatively large height of approximately 165mm compared to a smaller width to provide strength during the temperature cycling of the reactor.
  • the lower portion of the shield isolator 568 has an inner annular recess fitting outside of the rim 577 of the clamp ring 576.
  • the rim 577 not only acts to center inner diameter of the shield isolator 568 with respect to the clamp ring 576 but also acts as a barrier against any particles generated at the sliding surface 580 between the ceramic shield isolator 568 and the metal ring clamp 576 from reaching the main processing area.
  • a flange 581 of the floating shield 564 freely rests on the shield isolator 568 and has a tab or rim 582 on its outside extending downwardly into an annular recess formed at the upper outer comer of the shield isolator 568.
  • the tab 582 centers the floating shield 564 with respect to the target 556 at the outer diameter of the shield isolator 568.
  • the shield tab 582 is separated from the shield isolator 568 by a narrow gap which is sufficiently small to align the plasma dark spaces but sufficiently large to prevent jamming of the shield isolator 568, and the floating shield 581 rests on the shield isolator 568 in a sliding contact area 583 inside and above the tab 582.
  • a narrow channel 584 is formed between a head 585 of the floating shield 564 and the target 556. It has a width of about 2mm to act as a plasma dark space.
  • the narrow channel 584 continues in a path extending even more radially inward than illustrated past a downwardly projecting ridge 586 of the backing plate flange 574 to an upper back gap 584a between the shield head 585 and the target isolator 554.
  • the structure of these elements and their properties are similar to those disclosed by Tang et al. in U.S. Patent Application 09/191 ,253, filed October 30, 1998.
  • the upper back gap 584a has a width of about 1.5mm at room temperature. When the shield elements are temperature cycled, they tend to deform.
  • the upper back gap 584a having a smaller width than the narrow channel 584 next to the target 556, is sufficient to maintain a plasma dark space in the narrow channel 584.
  • the back gap 584a continues downwardly into a lower back gap 584b between the shield isolator 568 and the ring clamp 576 on the inside and the chamber body 552 on the outside.
  • the lower back gap 584b serves as a cavity to collect ceramic particles generated at the sliding surfaces 580, 583 between the ceramic shield isolator 568 and the clamp ring 576 and the floating shield 564.
  • the shield isolator 568 additionally includes a shallow recess 583a on its upper inner corner to collect ceramic particles from the sliding surface 583 on its radially inward side.
  • the floating shield 564 includes a downwardly extending, wide upper cylindrical portion 588 extending downwardly from the flange 581 and connected on its lower end to a narrower lower cylindrical portion 590 through a transition portion 592.
  • the grounded shield 566 has an wider upper cylindrical portion 594 outside of and thus wider than the upper cylindrical portion 588 of the floating shield 564.
  • the grounded upper cylindrical portion 594 is connected on its upper end to the grounded shield flange 580 and on its lower end to a narrowed lower cylindrical portion 596 through a transition portion 598 that approximately extends radially of the chamber.
  • the grounded lower cylindrical portion 596 fits outside of and is thus wider than the floating lower cylindrical portion 590; but it is smaller than the floating upper cylindrical portion 564 by a radial separation of about 3mm.
  • the two transition portions 592, 598 are both vertically and horizontally offset.
  • a labyrinthine narrow channel 600 is thereby formed between the floating and grounded shields 564, 566 with the offset between the grounded lower cylindrical portion 596 and floating upper cylindrical portion 564 assuring no direct line of sight between the two vertical channel portions.
  • a purpose of the channel 600 is to electrically isolate the two shields 564, 566 while protecting the clamp ring 576 and the shield isolator 568 from copper deposition.
  • the lower portion of the channel 600 between the lower cylindrical portions 590, 596 of the shields 564, 566 has an aspect ratio of 4:1 or greater, preferably 8:1 or greater.
  • the lower portion of the channel 600 has an exemplary width of 0.25cm and length of 2.5cm, with preferred ranges being 0.25 to 0.3cm and 2 to 3cm.
  • the two adjacent 90 degrees turns or bends in the channel 600 between the two transition portions 592, 598 further isolate the shield isolator 568 from the copper plasma.
  • a similar but reduced effect could be achieved with 60 degrees bends or even 45 degrees bends but the more effective 90 degrees bends are easier to form in the shield material.
  • the 90 degrees turns are much more effective because they increase the probability that copper particles coming from any direction will have at least one high angle hit and thereby lose most their energy to be stopped by the upper grounded cylindrical portion 594.
  • the 90 degrees turns also shadow the clamp ring 576 and shield isolator 568 from being directly irradiated by copper particles.
  • the convolute channel 600 collects ceramic particles generated from the shield isolator 568 during processing on the horizontal transition portion 598 of the grounded shield 566. It is likely that such collected particles are pasted by copper also collected there.
  • the lower cylindrical portion 596 of the grounded shield 566 continues downwardly to well in back of the top of the pedestal 562 supporting the wafer 558.
  • the grounded shield 566 then continues radially inwardly in a bowl portion 602 and vertically upwardly in an innermost cylindrical portion 604 to approximately the elevation of the wafer 558 but spaced radially outside of the pedestal 562.
  • the shields 564, 566 are typically composed of stainless steel, and their inner sides may be bead blasted or otherwise roughened to promote adhesion of the copper sputter deposited on them. At some point during prolonged sputtering, however, the copper builds up to a thickness that it is likely to flake off, producing deleterious particles. Before this point is reached, the shields should be cleaned or more likely replaced with fresh shields. However, the more expensive isolators 554, 568 do not need to be replaced in most maintenance cycles. Furthermore, the maintenance cycle is determined by flaking of the shields, not by electrical shorting of the isolators.
  • the floating shield 564 accumulates some electron charge and builds up a negative potential. Thereby, it repels further electron loss to the floating shield 564 and thus confines the plasma nearer the target 556.
  • Ding et al. have disclosed a similar effect with a somewhat similar structure in U.S. Patent 5,736,021.
  • the floating shield 564 of FIG. 16 has its lower cylindrical portion 590 extending much further away from the target 556 than does the corresponding part of Ding et al., thereby confining the plasma over a larger volume.
  • the floating shield 564 electrically shields the grounded shield 566 from the target 556 so that is should not extend too far away from the target 556.
  • a selectable DC power supply 610 negatively biases the target 556 to about -400 to -600VDC with respect to the grounded shield 566 to ignite and maintain the plasma.
  • a target power of between 1 and 5kW is typically used to ignite the plasma while a power of greater than 10kW is preferred for the SIP sputtering described here.
  • the pedestal 562 and hence the wafer 558 are left electrically floating, but a negative DC self-bias nonetheless develops on it.
  • some designs use a controllable power supply 612 to apply a DC or RF bias to the pedestal 562 to further control the negative DC bias that develops on it.
  • the bias power supply 612 is an RF power supply operating at 13.56MHz. It may be supplied with up to 600W of RF power, a preferred range being 350 to 550W for a 200mm wafer.
  • a gas source 614 supplies a sputtering working gas, typically the chemically inactive noble gas argon, to the chamber 552 through a mass flow controller 616. The working gas can be admitted to the top of the chamber or, as illustrated, at its bottom, either with one or more inlet pipes penetrating apertures through the bottom of the shield grounded shield 566 or through a gap 618 between the grounded shield 566, the wafer clamp 560, and the pedestal 562.
  • a vacuum pump system 620 connected to the chamber 552 through a wide pumping port 622 maintains the chamber at a low pressure. Although the base pressure can be held to about 10 "7 Torr or even lower, the pressure of the working gas is typically maintained at between about 1 and 1000 milliTorr in conventional sputtering and to below about 5 milliTorr in SIP sputtering.
  • a computer-based controller 624 controls the reactor including the DC target power supply 610, the bias power supply 612, and the mass flow controller 616.
  • a magnetron 630 is positioned in back of the target 556. It has opposed magnets 632, 634 connected and supported by a magnetic yoke 636. The magnets create a magnetic field adjacent the magnetron 630 within the chamber 552. The magnetic field traps electrons and, for charge neutrality, the ion density also increases to form a high-density plasma region 638.
  • the magnetron 630 is usually rotated about the center 640 of the target 556 by a motor-driven shaft 642 to achieve full coverage in sputtering of the target 556.
  • the power density delivered to the area adjacent the magnetron 630 must be made high. This can be achieved, as described by Fu in the above cited patents, by increasing the power level delivered from the DC power supply 610 and by reducing the area of magnetron 630, for example, in the shape of a triangle or a racetrack.
  • a 601 triangular magnetron which is rotated with its tip approximately coincident with the target center 640, covers only about 1/6 of the target at any time. Coverage of 1/4 is the preferred maximum in a commercial reactor capable of SIP sputtering.
  • the inner magnetic pole represented by the inner magnet 632 and unillustrated magnetic pole face should have no significant apertures and be surrounded by a continuous outer magnetic pole represented by the outer magnets 634 and unillustrated pole face. Furthermore, to guide the ionized sputter particles to the wafer 558, the outer pole should produce a much higher magnetic flux than the inner pole. The extending magnetic field lines trap electrons and thus extend the plasma closer to the wafer 558. The ratio of magnetic fluxes should be at least 150% and preferably greater than 200%. Two embodiments of Fu's triangular magnetron have 25 outer magnets and 6 or 10 inner magnets of the same strength but opposite polarity.
  • the DC voltage difference between the target 556 and the grounded shield 566 ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target 556.
  • the ions strike the target 556 at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target 556.
  • Some of the target particles strike the wafer 558 and are thereby deposited on it, thereby forming a film of the target material.
  • nitrogen is additionally admitted into the chamber, and it reacts with the sputtered metallic atoms to form a metallic nitride on the wafer 558.
  • the illustrated chamber is capable of self-ionized sputtering of copper including sustained self-sputtering.
  • the supply of argon may be cut off in the case of SSS, and the copper ions have sufficiently high density to resputter the copper target with a yield of greater than , unity.
  • some argon may continue to be supplied, but at a reduced flow rate and chamber pressure and perhaps with insufficient target power density to support pure sustained self-sputtering but nonetheless with a significant but reduced fraction of self-sputtering. If the argon pressure is increased to significantly above 5 milliTorr, the argon will remove energy from the copper ions, thus decreasing the self-sputtering.
  • the wafer bias attracts the ionized fraction of the copper particle deep into the hole.
  • the target-to-substrate spacing is typically greater than half the substrate diameter. When used, it is preferably greater than 90% wafer diameter, but spacings greater than 80% including 100% and 140% of the substrate diameter are believed appropriate also.
  • the throws mentioned in the examples of the embodiment are referenced to 200mm wafers. Long throw in conventional sputtering reduces the sputtering deposition rate, but ionized sputter particles do not suffer such a large decrease.
  • SSS sustained self-sputtering
  • a seed copper layer 650 is deposited in the via hole 22 over the barrier layer 24 using, for example, the long-throw sputter reactor of FIG. 15 and under conditions promoting SIP.
  • the SIP copper layer 650 may be deposited, for example, to a blanket thickness of 50 to 300nm or more preferably of 80 to 200nm.
  • the SIP copper seed layer 650 preferably has a thickness in the range of 2 to 20nm on the via sidewalls, more preferably 7 to 15nm. In view of the narrow holes, the sidewall thickness should not exceed 50nm.
  • the quality of the film is improved by decreasing the pedestal temperature to less than 0 degrees C and preferably to less than -40 degrees C so that the coolness afforded by the quick SIP deposition becomes important.
  • the SIP copper seed layer 650 has good bottom coverage and enhanced sidewall coverage. It has been experimentally observed to be much smoother than either IMP or CVD copper deposited directly over the barrier layer 24. After the copper seed layer 650 is deposited, the hole is filled with a copper layer 118, as in FIG. 1, preferably by electro-chemical plating using the seed layer 650 as one of the electroplating electrodes. However, the smooth structure of the SIP copper seed layer 650 also promotes reflow or higher-temperature deposition of copper by standard sputtering or physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • the higher bottom coverage at higher power indicates a higher ionization fraction.
  • the deposited copper film is observed to be much smoother than seen for IMP or CVD copper.
  • the SIP deposition is relatively fast, between 0.5 to 1.0 ⁇ m/min in comparison to an IMP deposition rate of no more than 0.2 ⁇ m/min.
  • the fast deposition rate results in a short deposition period and, in combination with the absence of argon ion heating, significantly reduces the thermal budget. It is believed that the low-temperature SIP deposition results in a very smooth copper seed layer.
  • a 290mm throw was used with the standard triangular magnetron of
  • the spatial dependences are approximately the same with the ionization fraction varying between about 10% and 20% with a direct dependence on the DC target power.
  • the relatively low ionization fraction demonstrate that SIP without long throw would has a large fraction of neutral copper flux which would have the unfavorable deep filling characteristics of conventional PVD. Results indicate that operation at higher power is preferred for better step coverage due to the increased ionization. [00137] The tests were then repeated with the number of inner magnets in the
  • Fu magnetron being reduced to six. That is, the second magnetron had improved uniformity in the magnetic flux, which promotes a uniform sputtered ion flux toward the wafer.
  • the results are plotted in FIG. 20.
  • Curve 668 displays the ion current flux for 12kW of target power and 0 milliTorr pressure; curve 670, for 18kW. Curves for 14kW and 16kW are intermediate.
  • the modified magnetron produces a more uniform ion current across the wafer, which is again dependent on the target power with higher power being preferred.
  • a SIP film deposited into a high-aspect ratio hole has favorable upper sidewall coverage and tends not to develop overhangs.
  • an IMP film deposited into such a hole has better bottom and bottom corner coverage, but the sidewall film tends to have poor coverage and be rough.
  • the advantages of both types of sputtering can be combined by using a two-step copper seed sputter deposition.
  • copper is deposited in an IMP reactor producing a high- density plasma, for example, by the use of RF inductive source power.
  • Exemplary deposition conditions are 20 to 60 milliTorr of pressure, 1 to 3kW of RF coil power, 1 to 2kW of DC target power, and 150W of bias power.
  • the first step provides good though rough bottom and bottom sidewall coverage.
  • copper is deposited in an SIP reactor of the sort described above producing a lesser degree of copper ionization.
  • Exemplary deposition conditions are 1 Torr pressure, 18 to 24kW of DC target power and 500W of bias power.
  • the second step provides good smooth upper sidewall coverage and further smoothes out the already deposited IMP layer.
  • the blanket deposition thicknesses for the two steps preferably range from 50 to 100nm for the IMP deposition and 100 to 200nm for the SIP layer. Blanket thicknesses may be a ratio of 30:70 to 70:30.
  • the SIP layer can be deposited before the IMP layer. After the copper seed layer is sputter deposited by the two-step process, the remainder of the hole is filled, for example, by electroplating.
  • the SIP sidewall coverage may become a problem for very narrow, high-aspect ratio vias. Technology for 0.13 ⁇ m vias and smaller is being developed. Below about 100nm of blanket thickness, the sidewall coverage may become discontinuous. As shown in the cross-sectional view of FIG. 21 , the unfavorable geometry may cause a SIP copper film 680 to be formed as a discontinuous films including voids or other imperfections 682 on the via sidewall 30.
  • the imperfection 682 may be an absence of copper or such a thin layer of copper that it cannot act locally as an electroplating cathode. Nonetheless, the SIP copper film 680 is smooth apart from the imperfections 682 and well nucleated.
  • a copper CVD seed layer 684 over the SIP copper nucleation film 680. Since it is deposited by chemical vapor deposition, it is generally conformal and is well nucleated by the SIP copper film 680.
  • the CVD seed layer 684 patches the imperfections 682 and presents a continuous, non-rough seed layer for the later copper electroplating to complete the filling of the hole 22.
  • the CVD layer may be deposited in a CVD chamber designed for copper deposition, such as the CuxZ chamber available from Applied Materials using the previously described thermal process.
  • the CVD layer 684 may be deposited to a thickness, for example, in the range of 5 to 20nm. The remainder of the hole may then be filled with copper by other methods.
  • the very smooth seed layer produced by CVD copper on top of the nucleation layer of SIP copper provides for efficient hole filling of copper by electroplating or conventional PVD techniques in the narrow vias being developed. In particular for electroplating, the smooth copper nucleation and seed layer provides a continuous and nearly uniform electrode for powering the electroplating process.
  • CVD filling is that it eliminates the need for a separate electroplating step. Also, electroplating requires fluid flows which may be difficult to control at hole widths below 0.13 ⁇ m.
  • An advantage of the copper bilayer of this embodiment of the invention is that it allows the copper deposition to be performed with a relatively low thermal budget. Tantalum tends to dewet from oxide at higher thermal budgets.
  • IMP has many of the same coverage advantages for deep hole filling, but IMP tends to operate at a much higher temperature because it produces a high flux of energetic argon ions which dissipate their energy in the layer being deposited. Further, IMP invariably implants some argon into the deposited film.
  • the relatively thin SIP layer is deposited at a relatively high rate and the SIP process is not inherently hot because of the absence of argon. Also, the SIP deposition rates are much faster than with IMP so that any hot deposition is that much shorter, by up to a factor of a half.
  • the thermal budget is also reduced by a cool ignition of the SIP plasma.
  • a cool plasma ignition and processing sequence is illustrated in the flow diagram of FIG. 23.
  • the load lock valve is closed, and in step 690 gas pressures are equilibrated.
  • the argon chamber pressure is raised to that used for ignition, typically between 2 and about 5 to 10 milliTorr, and the argon backside cooling gas is supplied to the back of the wafer at a backside pressure of about 5 to10 Torr.
  • the argon is ignited with a low level of target power, typically in the range of 1 to 5kW.
  • the chamber pressure is quickly ramped down, for example over 3s, with the target power held at the low level. If sustained self-sputtering is planned, the chamber argon supply is turned off, but the plasma continues in the SSS mode. For self-ionized plasma sputtering, the argon supply is reduced. The backside cooling gas continues to be supplied.
  • the target power is quickly ramped up to the intended sputtering level, for example, 10 to 24kW or greater for a 200mm wafer, chosen for the SIP or SSS sputtering. It is possible to combine the steps 694, 696 by concurrently reducing pressure and ramping up the power.
  • step 698 the target continues to be powered at the chosen level for a length of time necessary to sputter deposit the chosen thickness of material.
  • This ignition sequence is cooler than using the intended sputtering power level for ignition.
  • the higher argon pressure facilitates ignition but would deleteriously affect the sputtered neutrals if continued at the higher power levels desired for sputter deposition.
  • the pedestal cooling keep the wafer chilled through the ignition process.
  • the invention is particularly useful at the present time for copper inter-level metallization and barrier and liner deposition, the different aspects of the invention may be applied to sputtering other materials and for other purposes.
  • the interconnect layer or layers may also be deposited in a sputter chamber similar to the chamber 152 (FIG. 4) which generates both SIP and ICP plasmas. If deposited in a chamber such as the chamber 152, the target 156 would be formed of the deposition material, such as copper, for example. In addition, the ICP coil 151 may be formed of the same deposition material as well, particularly if coil sputtering is desired for some or all of the interconnect metal deposition.
  • the illustrated chamber 152 is capable of self-ionized sputtering of copper including sustained self-sputtering.
  • the supply of argon may be cut off in the case of SSS, and the copper ions have sufficiently high density to resputter the copper target with a yield of greater than unity.
  • some argon may continue to be supplied, but at a reduced flow rate and chamber pressure and perhaps with insufficient target power density to support pure sustained self-sputtering but nonetheless with a significant but reduced fraction of self-sputtering. If the argon pressure is increased to significantly above 5 milliTorr, the argon will remove energy from the copper ions, thus decreasing the self-sputtering.
  • SIP self-ionized plasma
  • ICP inductively coupled plasma
  • SSS sustained self-sputtering
  • a structure in accordance with the present invention is a via illustrated in cross-section in Fig. 24.
  • a copper seed layer 700 is deposited in a via hole 702 over the liner layer 704 (which may include one or more barrier and liner layers such as the aforementioned TaN barrier and Ta liner layers) using, for example, a long-throw sputter reactor of the type shown in FIG. 4 and under conditions promoting combined SIP and ICP and/or alternating SIP and ICP.
  • the reactor would have a target which includes the copper or other seed layer deposition material.
  • the SIP-ICP copper layer 700 may be deposited, for example, to a blanket thickness of 50 to 300nm or more preferably of 80 to 200nm.
  • the SIP- ICP copper seed layer 700 preferably has a thickness in the range of 2 to 20nm on the via sidewalls, more preferably 7 to 15nm. In view of the narrow holes, the sidewall thickness should not exceed 50nm.
  • the quality of the film is improved by decreasing the pedestal temperature to less than 0 degrees C and preferably to less than -40 degrees C so that the coolness afforded by the quick SIP deposition becomes important.
  • the SIP-ICP copper seed layer 700 will have good bottom coverage and enhanced sidewall coverage.
  • the copper seed layer 700 may be resputtered either in a separate step or during the initial deposition to redistribute the copper deposition material to increase coverage at the inside bottom corners of the via while usually leaving a thinner coverage in the central portion of the via bottom.
  • the hole may be filled with a copper layer similar to the copper layer 347b' of FIG.14b, preferably by electro-chemical plating using the seed layer 700 as one of the electroplating electrodes.
  • an SIP-ICP layer may be formed in a process which combines selected aspects of both SIP and ICP deposition techniques in one step, referred to herein generally as an SIP-ICP step.
  • a reactor 715 in accordance with an alternative embodiment has a second coil 716 in addition to the coil 151 as shown in FIG. 25.
  • one end of the coil 716 is insulatively coupled through a darkspace shield 164' by a feedthrough standoff 182 to the output of an amplifier and matching network 717 (FIG. 26).
  • the input of the matching network 717 is coupled to an RF generator 718.
  • the other end of the coil 716 is insulatively coupled through the shield 164' by a feedthrough standoff 182 to ground, via a blocking capacitor 719, to provide a DC bias on the coil 716.
  • the DC bias may be controlled by a separate DC source 721.
  • RF energy is applied to one or both of the RF coils 151 and 716 at 1-3 kW and a frequency of 2Mhz, for example.
  • the coils 151 and 716 when powered, inductively couple RF energy into the interior of the reactor.
  • the RF energy provided by the coils ionizes a precursor gas such as argon to maintain a plasma to ionize sputtered deposition material.
  • the pressure is preferably maintained at a substantially lower pressure, such as 2 mTorr, for example.
  • a substantially lower pressure such as 2 mTorr
  • the illustrated reactor 150 is also capable of self-ionized sputtering in a long-throw mode.
  • deposition material may be ionized not only as a result of the low pressure plasma maintained by the RF coil or coils, but also by the plasma self-generated by the DC magnetron sputtering of the target. It is believed that the combined SIP and ICP ionization processes can provide sufficient ionized material for good bottom and bottom corner coverage.
  • the lower ionization rate of the low pressure plasma provided by the RF coils 151 and 716 allows sufficient neutral sputtered material to remain un-ionized so as to be deposited on the upper sidewalls by the long-throw capability of the reactor.
  • the combined SIP and ICP sources of ionized deposition material can provide both good upper sidewall coverage as well as good bottom and bottom corner coverage.
  • the power to the coils 151 and 716 may be alternated such that in one step, the power to the upper coil 726 is eliminated or reduced relative to the power applied to the lower coil 151. In this step, the center of the inductively coupled plasma is shifted away from the target and closer to the substrate.
  • the layer may be formed in two or more steps in which in one step, referred to herein generally as an SIP step, little or no RF power is applied to either coil.
  • the pressure would be maintained at a relatively low level, preferably below 5 mTorr, and more preferably below 2 mTorr such as at 1 mTorr, for example.
  • the power applied to the target would be relatively high such as in the range of 18-24 kW DC, for example.
  • a bias may also be applied to the substrate support at a power level of 500 watts for example. Under these conditions, it is believed that ionization of the deposition material would occur primarily as a result of (SIP) self-ionization plasma. Combined with the long-throw mode arrangement of the reactor, it is believed that good upper sidewall coverage may be achieved with low overhang.
  • the portion of the layer deposited in this initial step may be in the range of 1000-2000 angstroms, for example.
  • RF power may be applied to one or both of the coils 151 and 716.
  • the pressure may be raised substantially such that a high density plasma may be maintained.
  • the pressure may be raised to 20-60 mTorr, the RF power to the coil raised to a range of 1-3 kW, the DC power to the target reduced to 1-2 kW and the bias to the substrate support reduced to 150 watts.
  • the ionization of the deposition material would occur primarily as a result of high-density ICP.
  • the remainder of the hole may be filled by the same or another process.
  • the remainder of the hole may be filled by electroplating or CVD.
  • the coils 151 and 516 may be operated independently or together.
  • the coils may be operated together in which the RF signal applied to one coil is phase shifted with respect to the other RF signal applied to the other coil so as to generate a helicon wave.
  • the RF signals may be phase shifted by a fraction of a wavelength as described in U.S. pat. No. 6,264,812.
  • One embodiment of present invention includes an integrated process preferably practiced on an integrated multi-chamber tool, such as the Endura 5500 platform schematically illustrated in plan view in FIG. 27.
  • the platform is functionally described by Tepman et al. in U.S. Patent, 5,186,718.
  • Wafers which have been already etched with via holes or other structure in a dielectric layer are loaded into and out of the system through two independently operated load lock chambers 732, 734 configured to transfer wafers into and out of the system from wafer cassettes loaded into the respective load lock chambers.
  • the chamber is pumped to a moderately low pressure, for example, in the range of 10 "3 to 10 "4 Torr, and a slit valve between that load lock chamber and a first wafer transfer chamber 736 is opened. The pressure of the first wafer transfer chamber 736 is thereafter maintained at that low pressure.
  • a first robot 738 located in the first transfer chamber 736 transfer the wafer from the cassette to one of two degassing/orienting chambers 740, 742, and then to a first plasma pre-clean chamber 744, in which a hydrogen or argon plasma cleans the surface of the wafer. If a CVD barrier layer is being deposited, the first robot 738 then passes the wafer to a CVD barrier chamber 746. After the CVD barrier layer is deposited, the robot 738 passes the wafer into a pass through chamber 748, from whence a second robot 750 transfers it to a second transfer chamber 752. Slit valves separate the chambers 744, 746, 748 from the first transfer chamber 736 so as to isolate processing and pressure levels.
  • the second robot 750 selectively transfers wafers to and from reaction chambers arranged around the periphery.
  • a first IMP sputter chamber 754 may be dedicated to the deposition of copper.
  • An SIP sputter chamber 756 similar to the chamber 410 described above is dedicated to the deposition of an SIP copper seed or nucleation layer. This chamber combines SIP for bottom and sidewall coverage and resputtering for improved bottom corner coverage in either a one step or a multi- step process as discussed above.
  • an SIP-ICP sputter chamber 760 is dedicated to a sputtering a refractory metal, possibly in a reactive nitrogen plasma.
  • the same SIP- ICP chamber 760 may be used for depositing the refractory metal and its nitride.
  • a CVD chamber 758 is dedicated to the deposition of a copper nucleation, seed or liner layer or to complete the filling of the hole or both.
  • Each of the chambers 754, 756, 758, 760 is selectively opened to the second transfer chambers 752 by slit valves. It is possible to use a different configuration.
  • an IMP chamber 754 may be replaced by a second CVD copper chamber, particularly if CVD is used to complete the hole filling.
  • the second robot 750 transfers the wafer to an intermediately placed thermal chamber 762, which may be a cool down chamber if the preceding processing was hot or may be a rapid thermal processing (RTP) chamber is annealing of the metallization is required.
  • thermal chamber 762 may be a cool down chamber if the preceding processing was hot or may be a rapid thermal processing (RTP) chamber is annealing of the metallization is required.
  • RTP rapid thermal processing
  • the first robot 738 withdraws the wafer and transfers it back to a cassette in one of the load lock chambers 732, 734.
  • RTP rapid thermal processing
  • the entire system is controlled by a computer-based controller 770 operating over a control bus 772 to be in communication with sub-controllers associated with each of the chambers.
  • Process recipes are read into the controller 770 by recordable media 774, such as magnetic floppy disks or CD-ROMs, insertable into the controller 770, or over a communication link 776.

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Abstract

La présente invention concerne un réacteur de pulvérisation à magnétron (410) et son procédé d'utilisation, favorisant une pulvérisation par plasma auto-ionisé (SIP) et une pulvérisation par plasma à couplage inductif (ICP). Cette invention concerne un ensemble d'aimants auxiliaires qui se trouvent dans une autre enceinte et qui sont placés le long de parois latérales (414) d'un réacteur de pulvérisation à magnétron, sur un côté, en direction de la plaquette de la cible. Le magnétron (436) est de préférence petit, avec un pôle externe fort (442) d'une première polarité, entourant un pôle interne plus faible (440) d'une seconde polarité, le tout placé sur un collier de déviation (444), et tourne autour de l'axe (438) de l'enceinte au moyen de systèmes de rotation (446, 448, 450). Les aimants auxiliaires (462) présentent de préférence la première polarité afin de tirer le champ magnétique non équilibré (460) vers la plaquette (424) qui se trouve sur un socle (422) sous tension (454). De l'argon (426) est apporté à travers une vanne (428). La cible (416) est sous tension (434).
PCT/US2002/036940 1999-10-08 2002-11-14 Plasma auto-ionise et a couplage inductif destine a une pulverisation et a une repulverisation WO2003042424A1 (fr)

Priority Applications (14)

Application Number Priority Date Filing Date Title
KR1020107009485A KR101179726B1 (ko) 2001-11-14 2002-11-14 스퍼터링 및 재스퍼터링을 위한 자기-이온화 및 유도 결합 플라즈마
JP2003544237A JP5296956B2 (ja) 2001-11-14 2002-11-14 金属を堆積させる方法、金属を堆積させるツール、配線を形成する方法及びプラズマスパッタリアクタ
US10/495,506 US8696875B2 (en) 1999-10-08 2002-11-14 Self-ionized and inductively-coupled plasma for sputtering and resputtering
KR1020127010137A KR101312690B1 (ko) 2001-11-14 2002-11-14 스퍼터링 및 재스퍼터링을 위한 자기-이온화 및 유도 결합 플라즈마
KR1020047007317A KR100993046B1 (ko) 2001-11-14 2002-11-14 스퍼터링 및 재스퍼터링을 위한 자기-이온화 및 유도 결합플라즈마
CN028271017A CN1656243B (zh) 2001-11-14 2002-11-14 用于溅射和再溅射的自离子化及电感耦合等离子体
KR1020107009487A KR101179727B1 (ko) 2001-11-14 2002-11-14 스퍼터링 및 재스퍼터링을 위한 자기-이온화 및 유도 결합 플라즈마
US10/608,306 US7041201B2 (en) 2001-11-14 2003-06-26 Sidewall magnet improving uniformity of inductively coupled plasma and shields used therewith
US11/124,524 US7569125B2 (en) 2001-11-14 2005-05-05 Shields usable with an inductively coupled plasma reactor
US11/184,615 US20050255691A1 (en) 1999-10-08 2005-07-19 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US11/933,157 US8668816B2 (en) 1999-10-08 2007-10-31 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US12/182,988 US20090233438A1 (en) 1999-10-08 2008-07-30 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US14/205,260 US10047430B2 (en) 1999-10-08 2014-03-11 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US16/033,166 US20180327893A1 (en) 1999-10-08 2018-07-11 Self-ionized and inductively-coupled plasma for sputtering and resputtering

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US09/685,978 US6582569B1 (en) 1999-10-08 2000-10-10 Process for sputtering copper in a self ionized plasma
US09/993,543 2001-11-14
US09/993,543 US6610184B2 (en) 2001-11-14 2001-11-14 Magnet array in conjunction with rotating magnetron for plasma sputtering
US60/342,608 2001-12-21
US10/202,778 2002-07-25
US10/202,778 US20030116427A1 (en) 2001-08-30 2002-07-25 Self-ionized and inductively-coupled plasma for sputtering and resputtering

Related Parent Applications (5)

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US09/414,614 Division US6398929B1 (en) 1999-10-08 1999-10-08 Plasma reactor and shields generating self-ionized plasma for sputtering
US09/685,978 Continuation-In-Part US6582569B1 (en) 1999-10-08 2000-10-10 Process for sputtering copper in a self ionized plasma
US09/993,543 Continuation-In-Part US6610184B2 (en) 1999-10-08 2001-11-14 Magnet array in conjunction with rotating magnetron for plasma sputtering
US10/202,778 Continuation-In-Part US20030116427A1 (en) 1999-10-08 2002-07-25 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US10/202,778 Continuation US20030116427A1 (en) 1999-10-08 2002-07-25 Self-ionized and inductively-coupled plasma for sputtering and resputtering

Related Child Applications (8)

Application Number Title Priority Date Filing Date
US10/495,506 A-371-Of-International US8696875B2 (en) 1999-10-08 2002-11-14 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US10/608,306 Continuation US7041201B2 (en) 2001-11-14 2003-06-26 Sidewall magnet improving uniformity of inductively coupled plasma and shields used therewith
US10/608,306 Continuation-In-Part US7041201B2 (en) 2001-11-14 2003-06-26 Sidewall magnet improving uniformity of inductively coupled plasma and shields used therewith
US49550604A Continuation-In-Part 1999-10-08 2004-05-12
US49550604A Continuation 1999-10-08 2004-05-12
US11/184,615 Continuation US20050255691A1 (en) 1999-10-08 2005-07-19 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US11/933,157 Continuation US8668816B2 (en) 1999-10-08 2007-10-31 Self-ionized and inductively-coupled plasma for sputtering and resputtering
US14/205,260 Division US10047430B2 (en) 1999-10-08 2014-03-11 Self-ionized and inductively-coupled plasma for sputtering and resputtering

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JP2008500457A (ja) * 2004-05-26 2008-01-10 アプライド　マテリアルズ　インコーポレイテッド スパッタ反応装置内で金属バリアを形成するために特にマルチステッププロセスで使用される可変四重電磁石アレー
US9062372B2 (en) 2002-08-01 2015-06-23 Applied Materials, Inc. Self-ionized and capacitively-coupled plasma for sputtering and resputtering
US10047430B2 (en) 1999-10-08 2018-08-14 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
CN108780742A (zh) * 2016-03-05 2018-11-09 应用材料公司 用于在物理气相沉积工艺中控制离子分数的方法和设备
CN114574829A (zh) * 2022-03-08 2022-06-03 松山湖材料实验室 一种微深孔内镀膜工艺及镀膜装置

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US5907220A (en) * 1996-03-13 1999-05-25 Applied Materials, Inc. Magnetron for low pressure full face erosion
US6077403A (en) * 1997-06-06 2000-06-20 Anelva Corporation Sputtering device and sputtering method
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Cited By (12)

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US10047430B2 (en) 1999-10-08 2018-08-14 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
US9062372B2 (en) 2002-08-01 2015-06-23 Applied Materials, Inc. Self-ionized and capacitively-coupled plasma for sputtering and resputtering
WO2005004189A2 (fr) * 2003-06-26 2005-01-13 Applied Materials, Inc. Aimant lateral desstine a ameliorer l'uniformite d'un plasma couple par induction et ecrans utilises avec celui-ci
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JP2008500457A (ja) * 2004-05-26 2008-01-10 アプライド　マテリアルズ　インコーポレイテッド スパッタ反応装置内で金属バリアを形成するために特にマルチステッププロセスで使用される可変四重電磁石アレー
CN108780742A (zh) * 2016-03-05 2018-11-09 应用材料公司 用于在物理气相沉积工艺中控制离子分数的方法和设备
CN108780742B (zh) * 2016-03-05 2023-07-18 应用材料公司 用于在物理气相沉积工艺中控制离子分数的方法和设备
CN114574829A (zh) * 2022-03-08 2022-06-03 松山湖材料实验室 一种微深孔内镀膜工艺及镀膜装置
CN114574829B (zh) * 2022-03-08 2023-10-27 松山湖材料实验室 一种微深孔内镀膜工艺及镀膜装置

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