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JPH11509049A - 高アスペクト比を有するコンタクトホールに平坦な配線膜及びプラグを形成する改善された成膜装置及び成膜方法 - Google Patents

高アスペクト比を有するコンタクトホールに平坦な配線膜及びプラグを形成する改善された成膜装置及び成膜方法

Info

Publication number
JPH11509049A
JPH11509049A JP9538711A JP53871197A JPH11509049A JP H11509049 A JPH11509049 A JP H11509049A JP 9538711 A JP9538711 A JP 9538711A JP 53871197 A JP53871197 A JP 53871197A JP H11509049 A JPH11509049 A JP H11509049A
Authority
JP
Japan
Prior art keywords
substrate
target
film
contact hole
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9538711A
Other languages
English (en)
Japanese (ja)
Inventor
エー ワイス コリー
ギトルマン ブルース
エム バルソン ジェフリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of JPH11509049A publication Critical patent/JPH11509049A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04Coating on selected surface areas, e.g. using masks
    • C23C14/046Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
JP9538711A 1996-04-26 1997-04-15 高アスペクト比を有するコンタクトホールに平坦な配線膜及びプラグを形成する改善された成膜装置及び成膜方法 Pending JPH11509049A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63829096A 1996-04-26 1996-04-26
US08/638,290 1996-04-26
PCT/IB1997/000522 WO1997041598A1 (fr) 1996-04-26 1997-04-15 Appareil et procede permettant un depot ameliore de couches minces de revetement et de fiches conformes dans des contacts a fort allongement

Publications (1)

Publication Number Publication Date
JPH11509049A true JPH11509049A (ja) 1999-08-03

Family

ID=24559418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9538711A Pending JPH11509049A (ja) 1996-04-26 1997-04-15 高アスペクト比を有するコンタクトホールに平坦な配線膜及びプラグを形成する改善された成膜装置及び成膜方法

Country Status (7)

Country Link
EP (1) EP0843890A1 (fr)
JP (1) JPH11509049A (fr)
KR (1) KR19990028451A (fr)
AU (1) AU2400497A (fr)
CA (1) CA2225446A1 (fr)
TW (1) TW417223B (fr)
WO (1) WO1997041598A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005082873A (ja) * 2003-09-10 2005-03-31 Applied Materials Inc 膜形成方法
JP2011500967A (ja) * 2007-10-26 2011-01-06 オーツェー・エリコン・バルザース・アーゲー 3次元半導体パッケージングにおける貫通シリコンビアのメタライゼーションへのhipimsの適用
JP2012506638A (ja) * 2008-10-22 2012-03-15 アプライド マテリアルズ インコーポレイテッド 強化された銅のイオン化を伴うpvd銅シードオーバーハング再スパッタ

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002007198A2 (fr) * 2000-07-18 2002-01-24 Applied Materials, Inc. Depot de films de tantale de faible contrainte

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4925542A (en) * 1988-12-08 1990-05-15 Trw Inc. Plasma plating apparatus and method
KR960026261A (ko) * 1994-12-14 1996-07-22 제임스 조셉 드롱 재 도입형 콘택 홀을 피복시키거나 또는 충진시키기 위한 방법 및 장치

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005082873A (ja) * 2003-09-10 2005-03-31 Applied Materials Inc 膜形成方法
JP2011500967A (ja) * 2007-10-26 2011-01-06 オーツェー・エリコン・バルザース・アーゲー 3次元半導体パッケージングにおける貫通シリコンビアのメタライゼーションへのhipimsの適用
JP2012506638A (ja) * 2008-10-22 2012-03-15 アプライド マテリアルズ インコーポレイテッド 強化された銅のイオン化を伴うpvd銅シードオーバーハング再スパッタ

Also Published As

Publication number Publication date
KR19990028451A (ko) 1999-04-15
TW417223B (en) 2001-01-01
AU2400497A (en) 1997-11-19
WO1997041598A1 (fr) 1997-11-06
CA2225446A1 (fr) 1997-11-06
EP0843890A1 (fr) 1998-05-27

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